JP3014356B2 - MPEG-II audio encoding device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus using MPEG-II including image and audio coding, which is a compression algorithm used for next-generation digital video media such as HDTV and DVD. The present invention relates to an MPEG-II audio encoding device for implementing a speech compression algorithm in the configuration.

[0002]

2. Description of the Related Art The MPEG-II audio coding method is a standard for high-quality audio compression, and is based on a subband analysis and a psychoacoustic model. Such an encoding method involves a large amount of calculation, and therefore, has many difficulties in realizing real-time processing. When an existing DSP structure is used, the complexity of the system may increase. For this reason, the present invention relates to an application specific processor.
It is configured as an MPEG-II audio encoding device based on.

[0003]

SUMMARY OF THE INVENTION The present invention
The present invention relates to the structure of an arithmetic and logic unit suitable for a dedicated DSP for MPEG-II audio encoding. The present invention
More specifically, it shows a structure that can quickly perform the arithmetic and logic operations required to support MPEG-II audio coding that supports multiple channels using a single DSP core in real time. It is.

The above MPEG-II audio encoding process includes an analysis filter and a 1024-point FFT (Fast Fourier).
Transform (Fast Fourier Transform), which consists of various types of work such as psychoacoustic model creation, bit allocation, quantization, multi-channel processing, and bit string formation. This process is performed for five input channels. Since all of them have to be applied, realization of real-time processing is difficult due to a large amount of calculation.

[0005] To solve the above problems, the present invention utilizes a special processor core that can control the system and effectively perform complex algorithms.
It is intended to implement an audio encoder. The present invention further aims at increasing the efficiency of the processor and increasing the computing power by adding an FFT and an analysis filter engine. It is a further object of the present invention to maximize system usage by configuring each module to process independent routines to form a pipeline.

[0006]

According to the present invention, there is provided an MPEG-II audio encoding apparatus comprising: an A / D converter for A / D converting audio data signals input to a plurality of channels; (6), a memory (7) for storing the audio data converted by the A / D converter on a frame basis for subsequent processing, and an FFT operation for each channel which receives the audio data stored in the memory and receives the audio data. An FFT unit (1) for performing analysis filtering simultaneously with the FFT operation by receiving the audio data stored in the memory, and outputting the processing result to the memory again; A psychoacoustic operation is performed from the result, a scale factor is calculated based on the output of the analysis filter unit (2), and a bit is allocated using the result of the psychoacoustic operation. A core unit (4) for packing the final output bit sequence and outputting the final output bit sequence, and an output buffer unit (8) for outputting the final output bit sequence of the core unit to the outside. It is characterized by comprising.

Further, according to the present invention, the FFT section (1) and the analysis filter section (2) are designed in a hard-wired logic, and the FFT section (1) receives an audio data signal through seven channels. It is characterized by that.

Further, according to the present invention, the MPEG-II audio encoding apparatus processes input signals of seven channels by one FFT unit (1), analysis filter unit (2) and core unit (4). The FFT unit (1) outputs an FFT operation result of the first channel, performs a psychoacoustic operation on the first channel in the core unit using the FFT operation result, and simultaneously outputs the second channel by the FFT unit. Is performed, and a psychoacoustic operation for the second channel is performed in the core unit using the result of the FFT operation for the second channel. By repeating such an operation, the psychoacoustic operation for the seventh channel is completed. The processing of the analysis filter unit (2) is performed by the FFT so that the analysis filtering for the seven channels by the analysis filter unit (2) is completed.
The processing is performed in parallel with the processing of the section (1) and the core section (4).

Further, the present invention provides an FFT unit (1), an analysis filter unit (2), and a core to complete analysis filtering for seven channels within one frame time simultaneously with the psychoacoustic calculation of the seven channels. Processing is performed by a pipeline structure using the unit (4) and the memory (7).

Further, according to the present invention, the core portion (4)
Program memory (1) for storing internal control programs
2), a data memory (13) for storing data necessary for control, a program sequencer unit (10, 11) for controlling program fetch, a data address generator (15) for controlling data input / output, and an arithmetic operation An arithmetic and logic operation unit (14) for performing a logical operation, a program memory address bus (16) and a program memory data bus (1);
7), a data memory address bus (18), a data memory data bus (19), and a control unit (9) for generating an external data input / output control signal and an internal control signal. And

[0011]

In the present invention, since the MPEG-II audio encoding process requires a large amount of calculation, the present invention divides the entire encoding process into several auxiliary blocks and processes them in order to realize this in real time.
In order to achieve the above-mentioned object, the present invention has a large amount of calculation, but has an analysis filter (Analysis Filter) and an FFT routine that repeat the same operation, and a psychoacoustic modeling and The entire system is divided into three blocks: a core that processes the bit string generation routine.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings. FIG. 1 is a system diagram showing an overall configuration of an embodiment of an MPEG-II audio encoder to which the present invention is applied. In the drawing, a portion indicated by a dotted line is embodied in one chip.

In the psychoacoustic modeling of the MPEG-II audio system, the calculation of the signal masking curve from the FFT output requires a number of calculations next to the analysis filter and the FFT routine. In the bit string generation routine, a scale factor (Scale
Factor), multi-channel processing is performed, bits are allocated using a masking curve obtained by psychoacoustic modeling, and a series of processings for generating a final bit sequence based on the bit allocation information is performed last in the core block.

The processing of the three blocks described above is based on ISO /
The processing is performed for each frame defined in the IEC, 13818-3, and the MPEG-II standard, and the processing of one frame is completed by a routine of an analysis filter and an FFT, and a routine of generating a bit string through a psychoacoustic model.

The analysis filter and the FFT routine that perform only the operations given iteratively are hardwired.
Wired) Although the work can be effectively performed by using a module and a controller designed in logic, the psychoacoustic modeling and the bit string generation routine other than this routine are work in which the operation mode changes depending on input data. And the microprogrammed controller works more effectively than the controller made in hardwired logic.

[0016] Further, the MPEG-
Due to the characteristics of II, an algorithm implementation method using five processors can be proposed. In this case, a controller for exchanging information and synchronizing between the five processors is additionally required, and the system complexity is increased. Increase. Therefore,
Instead of using multiple processor elements, etc., the system complexity can be reduced by using only one fast and effective DSP core. In the present embodiment, the MP
In consideration of such characteristics of the EG-II coding algorithm, the analysis filter and the FFT routine are created in separate blocks so that the input signal is processed in parallel.
A special processor core capable of effectively executing a complicated algorithm used for MPEG-II encoding is designed so that one processor core processes a psychoacoustic model and a bit string generation routine. Accordingly, a system that is effective in terms of complexity and cost / performance can be realized.

In FIG. 1, A / D-converted data of six channels of left, right, center, left surround, right surround, and low frequency enhancement (Low Frequency Enhancement) are stored in a memory control unit (Memory Management Unit). )
The data is input to the SRAM (7), which is an external memory of the chip, via (5), and is stored therein as data corresponding to one frame. Here, the A / D conversion module (6), which is an A / D converter, uses serial A / D, and one A / D converter handles two channels.

When one frame of data is stored in the external memory (7), the FFT module (1), which is an FFT unit,
Data is received from the external memory (7) via the memory control unit (5) in units of 1024 samples, and FFT operation is performed for one channel. On the other hand, the analysis filter module (2), which is an analysis filter unit, receives data from the external memory (7) via the memory control unit (5) in units of 32 samples, performs an operation, and stores the resulting data in the unit of 32 samples. The data is stored for each channel in the external memory (7) through the control unit (5).

The core module (4) includes an external memory (7) via the memory control unit (5) for storing the result data obtained by the analysis filtering by the analysis filter module (2) and the result data obtained by the FFT operation processing by the FFT module (1). And perform various kinds of tasks such as psychoacoustic model creation, bit allocation, quantization, multi-channel processing, and bit string formation. The packed bit string is output in byte units via the FIFO (8).

Each module of the MPEG-II audio encoder embodied in this embodiment includes a memory used for calculation and a buffer for data exchange between modules. FFT module (FFT computing unit) (1)
Has a 1K × 16 bit ROM and a 1K × 32 bit memory, and the analysis filter module (2) has a 1.5K × 16 bit ROM and a 2.5K × 16 bit memory. The core module (4), which is a processor core unit, has a 2048 × 25-bit program ROM, 3072 × 16-bit data ROM, and a 2048 × 16-bit memory as memories.
Further, an external memory (7) is provided for storing the audio data input through the A / D conversion module (6) and the output subjected to the analysis filtering.

FIG. 2 is a diagram for explaining the operation timing for the MPEG-II audio encoder of FIG.
The operation process is as follows. Analysis filter module
(2) works on up to 5 channels for 1152 input samples per channel, and the FFT unit (1) works on up to 7 channels for 1024 samples per channel. While the above two blocks work, the processor core unit (4) performs the work of the psychoacoustic model creation processing using the FFT output.
When all the routines are completed, the processor core unit (4) generates a bit string using the output of the analysis filter and the output of the psychoacoustic model.

In the above operation, the analysis filter, the FFT routine, and the psychoacoustic model are processed in parallel at the beginning of the frame. In particular, the processing of the FFT routine and the psychoacoustic model is pipelined for each channel. Done. This is described below by setting the calculation time of the FFT routine in the unit of execution.

In the first time section of FIG. 2, the FFT module (1) performs an FFT routine for the first channel (CH0). In the second time interval, the processor core unit (4) performs a psychoacoustic model operation using the result of the FFT operation for the first channel, and at the same time, the FFT module (1) executes the operation for the second channel (CH1). FFT
Perform the routine. In this manner, in the seventh time section, the psychoacoustic model calculation for the sixth channel (CH5) and the FFT calculation for the seventh channel (CH6) are performed, and finally, in the eighth time section, the seventh By performing the psychoacoustic model computation for the channel (CH6), the FFT computation and the psychoacoustic model computation for all channels are completed. Further, the analysis filtering operation for five channels is performed within the end time of the FFT operation for seven channels. The reason for using such a calculation algorithm is that the psychoacoustic model calculation requires the result of the FFT calculation, but the analysis filtering calculation can be performed independently of the calculation results of other calculation units. . That is, there is no data exchange with other operation units.

In order for the above-mentioned pipeline to be performed effectively, the work corresponding to each stage is completed at the same time,
It is necessary to eliminate the input / output congestion caused by the difference in processing time. That is, when the execution time of the psychoacoustic model for one channel and the processing time of the FFT routine are equal, the maximum processing efficiency can be obtained. Implementation time of the psychoacoustic model is 27MH
Approximately 43000 cycles (cycle) converted to z clock
Required, 1024 points per channel
The FFT operation is completed in about 45,000 cycles.

In the remaining six time periods in the latter half of the frame shown in FIG. 2, the processor core unit (4) generates a bit string from the output of the analysis filter module (2) and the output of the psychoacoustic model. When the calculation of the psychoacoustic model is completed, the processor core unit (4) performs a bit string generation operation on the output of the analysis filter module (2). Analysis filtering is performed for five channels.

FIG. 3 shows a DSP for MPEG-II audio encoding.
It is a block diagram of a core. For MPEG-II audio encoding
The DSP core uses only one DSP core to implement the algorithm in terms of reducing system complexity, and is therefore designed with the following considerations.
First, the instruction execution time is shortened, and the instruction execution capability of the DSP core is maximized. That is, it is designed to execute a large number of possible instructions in a unit time. Second,
Functions that are frequently used to implement the algorithm are resolved by using specially prepared commands as much as possible. Accordingly, the total amount of execution time can be reduced by reducing the absolute amount of the command word required for implementing the algorithm.

FIG. 3 is a block diagram of a processor core having three independent units which can be one embodiment of the DSP core of the present invention.
Itecture) is embodied in an instruction-level pipeline to achieve fast execution speed. According to the present invention, a read stage is added to a pipeline structure having two stages (Stage) of instruction word prefetch and execute to execute prefetch, operand read, and execution. The architecture is designed as a three-stage pipeline structure.

In order to implement a pipeline, each stage must be completely independent. That is, at each stage of prefetch, read, and implementation,
Must not be shared. This requires three independent units. First, in order to make instruction word fetch and data manipulation (Manipulation) independent, a Harvard Archite architecture is used.
cture: a memory structure embodied so as to be able to be accessed independently and simultaneously using several independent memories in order to increase the memory input / output bandwidth. In this embodiment, the program memory (12) and the data memory (13) are used. Independently configured). More specifically, a program sequencer (11) for generating a program address for program prefetch and a data address generator unit (1) which is a data address generator for generating an address for data reading.
5) and an arithmetic processing unit (14), which is an arithmetic logic operation unit (arithmetic anc logic unit) that processes data (executes an instruction word).

The block of the program sequencer (11) is responsible for instruction word fetch. The program sequencer (11) prefetches the next instruction word to be executed for each clock. The block of the data address generator (15) is
The address of the data used in the reading stage is created using a unit that performs a simple addition operation. The block of the arithmetic logic unit (14) performs all operations required from the MPEG-II audio encoder. Basically, addition, subtraction, and multiplication are performed, and logical operations of AND, OR, XOR, and NOT are performed to create a system control signal. In particular, MAC (Multiply &
Accumulate) For calculation, a multiplier and an adder are connected in series. In the MPEG-II algorithm, an operation having a high frequency is used, but the operation can be performed up to one clock with a special instruction word. That is,
Such application specific instructions (Application Specific Instr.)
MPEG with one processor core via auction)
Realization of real-time processing of the II audio encoder is enabled.

[0030]

As described in detail above, the present invention provides
The MPEG-II audio encoder is connected to a single application specific digital signal processor (Application Specific Digital Signal Pr
ocessor) to perform irregular operations, and other operations such as FFT and analysis filtering, which are regular and iterative operations, are implemented by a dedicated processor employing hard-wired logic, and data between each processing block. Adopted a pipeline structure that considers the input / output relationship, and implemented an MPEG-II audio coding algorithm that requires large-scale computation using an economical structure that enables real-time processing using parallel processing. Things.

The above-described preferred embodiments of the present invention have been disclosed for the purpose of illustration, and those skilled in the art can make various modifications, changes, additions, etc. within the spirit and scope of the present invention. Such modifications and changes are to be considered as belonging to the appended claims.

[Brief description of the drawings]

FIG. 1 is a system diagram showing an overall configuration of an embodiment of an MPEG-II audio encoder to which the present invention is applied.

FIG. 2 is a diagram for explaining operation timing for the MPEG-II audio encoder of FIG. 1;

FIG. 3 is a block diagram of a DSP core for MPEG-II audio encoding.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 FFT part (FFT module) 2 Analysis filter part (analysis filter module) 3 Control part 4 Processor core part (core module) 5 Memory control part 6 A / D conversion part (A / D conversion module) 7 External memory (SRAM) 8 First-in first-out buffer unit (FIFO) 9 Control unit 10 Program sequencer control unit 11 Program sequencer 12 Program memory 13 Data memory 14 Arithmetic and logic operation unit (Operation processing unit) 15 Data address generation unit 16 Program memory address bus 17 Program memory data Bus 18 data memory address bus 19 data memory data bus

Continuation of the front page (72) Inventor Sumihiro Gon 100 Sejong-ro, Jongno-gu, Seoul, Republic of Korea (56) References JP-A-8-242174 (JP, A) JP-A-9-134200 (JP, A) (58) ) Surveyed field (Int.Cl. ⁷ , DB name) H03M 7/30

Claims (5)

(57) [Claims] In an MPEG-II audio encoding apparatus, audio data signals input to a plurality of channels are converted to A /
An A / D conversion unit for performing D conversion, a memory for storing the audio data converted by the A / D conversion unit on a frame basis for subsequent processing, and an FFT for each channel that receives the audio data stored in the memory and is inputted. An FFT unit for performing a calculation (Fast Fourier Transform), an analysis filter unit for receiving the audio data stored in the memory, performing analysis filtering simultaneously with the FFT calculation, and outputting the processing result to the memory again; A psychoacoustic operation is performed from the processing result of the FFT unit, a scale factor is calculated based on the output of the analysis filter unit, and bits are allocated using the result of the psychoacoustic operation, and the result of the allocation is used as a final output bit sequence. A core unit that packs and outputs the final output bit sequence, and an output buffer that outputs the final output bit sequence of the core unit to the outside. MPEG-II audio coding apparatus characterized by comprising; and a § portion. 2. The MPEG-FFT unit according to claim 1, wherein the FFT unit and the analysis filter unit are designed as hard-wired logic, and the audio data signal is input to seven channels to the FFT unit. II audio encoding device. 3. The MPEG-II audio encoding device,
Each of the FFT units, the analysis filter unit, and the core unit processes the input signals of seven channels. The FFT unit outputs the result of the FFT operation of the first channel,
Using the result of the FFT operation, the core unit performs a psychoacoustic operation on the first channel, and simultaneously performs the second
Performs an FFT operation on the channel and calculates the FF of the second channel.
Using the result of the T operation, the core unit performs a psychoacoustic operation on the second channel, and by repeating such an operation, the psychoacoustic operation on the 7 channels is completed, and at the same time, the analysis filtering on the 7 channels by the analysis filter unit is performed. 3. The MPEG-II audio encoding apparatus according to claim 1, wherein the processing of the analysis filter unit is performed in parallel with the processing of the FFT unit and the core unit so as to be completed. 4. A pipeline structure using an FFT unit, an analysis filter unit, a core unit, and a memory, in order to complete the analysis filtering for the seven channels within one frame time simultaneously with the psychoacoustic calculation of the seven channels. 4. The MPEG-II audio encoding device according to claim 3, wherein the encoding is performed. 5. The core unit includes a program memory for storing an internal control program, a data memory for storing data required for control, a program sequencer for controlling program fetch, and a data address for controlling data input / output. A generator, an arithmetic and logic unit for performing an arithmetic and logic operation, a program memory address bus and a program memory data bus, a data memory address bus and a data memory data bus, and an external data input / output control signal and an internal control signal. 4. The MPEG-II audio encoding device according to claim 3, further comprising a control unit for generating the audio data.