JP3001206B2 - Information processing device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an information processing apparatus.

[Conventional technology]

In recent years, as the degree of integration of semiconductor memories has increased, the capacity of semiconductor memories per chip has been increasing, and in many cases, the capacity of control memories in information processing apparatuses has been exceeded.

[Problems to be solved by the invention]

Generally, in a semiconductor memory, if only the number of words is increased or only the number of bits in one word is increased in order to increase the degree of integration, an access time is increased or power consumption is increased. Therefore, the number of words and the number of bits are generally balanced and expanded.

When a semiconductor memory as described above is used as an internal memory such as a control memory or a directory memory of an information processing apparatus, one internal memory is configured using a plurality of semiconductor memory chips while the degree of integration of the semiconductor memory is low. However, in recent years, not only one internal memory has been completely inserted into one semiconductor memory chip, but also a drawback that less than half of the capacity of the semiconductor memory has been effectively used has been generated.

[Means for solving the problem]

An information processing apparatus according to the present invention includes an instruction register for holding an instruction word, a control storage in which the same data group is stored in a plurality of areas, and indexed by the instruction word held in the instruction register. Detecting means for detecting an error in the indexed data; specifying means for cycling the plurality of areas of the control storage when the detecting means detects an error in the data; and specifying the switching means; Means for suppressing updating of the instruction register when a data error is detected.

[Action]

Therefore, it is possible to effectively use the memory portion that has not been used conventionally and improve the reliability of the information processing device.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a part for decoding an instruction code (OP code) of an information processing apparatus according to an embodiment of the present invention, and FIG. 2 is a time chart showing the operation of the present embodiment.

The instruction register 1 is a register for holding an instruction word. When the signal line 13 becomes "1", the held instruction word is held. The OP code decoder 2 is a decoder indexed by an 8-bit instruction code portion (OP code) of the instruction register 1, and is constituted by a 1K word RAM. OP in register 3
Data output from the code decoder 2 is temporarily stored. The parity check circuit 4 detects whether there is any abnormality in the output data from the register 3, and outputs “1” to the signal line 13 if the parity of the output data is incorrect. The counter 5 counts up the value held by the output 13 from the parity check circuit 4 by +1.
When power is turned on, it is reset and holds “0”. The inverter 6 inverts the output from the parity check circuit 4. The V flip-flop 7 is a flip-flop to which the output of the inverter 6 is input, and indicates that the contents of the register 3 are correct. The arithmetic circuit 8 receiving the outputs of the signal lines 15 and 16 receives the control data of the signal line 16 when the V bit of the signal line 15 is "1", and receives the control data of the signal line 16 when the V bit is "0". Is configured to ignore. The opcode decoder 2 is indexed by a 10-bit address, of which the lower 8 bits are supplied from the OP code section of the instruction register 1 and the upper 2 bits are supplied from the counter 5. Since the OP code is 8 bits, the OP code decoder 2 has 25 bits.
It takes 6 words, but some of these OP code decoders 2
56 words are repeated 4 times, and 1K words are written in advance. That is, the same control data is written to addresses 0, 256, and 768. Now, it is assumed that the OP code of the instruction in the instruction register 1 is input to the OP code decoder 2 through the input line 11. In the OP code decoder 2, the input 8-bit
RA using OP code and 2-bit counter output as address
M is indexed, and the control data specified by the OP code is output via the read line 12. The signal line 12 branches, and one is input to the register 3. The register 3 is connected to the signal line 12
Is temporarily stored, and the data in the register 3 is on standby until called by another signal. The other line separated from the signal line 12 is input to the parity check circuit 4. In parity check circuit 4, signal line
Judge whether the data entered from step 12 is incorrect or not. If not incorrect, signal line 13 is set to “0”
, And the output is inverted by the inverter 6 and set in the V flip-flop 7. If the output 15 from the V flip-flop 7 is "1", the control data stored in the register 3 is used by the arithmetic circuit 8.

Next, the operation in the case of an error will be described with reference to FIG. 1 and FIG.

If the control data indexed by the instruction set in the instruction register 1 in the machine cycle 0 is incorrect, the parity check circuit 4 outputs "1" to the signal line 13 and the instruction register 1 The instruction word including the code (OP code) is held as it is, and the next clock outputs the same OP code as in the previous clock.
The other one branched from the signal line 13 is input to the counter 5 and counts up the counter 5 by one. In the next machine cycle 1, the output of the counter 5 and the held OP code from the instruction register 1 are supplied from the signal lines 14 and 11, respectively, are input to the OP code decoder 2 and are different from the RAM used before. Next R counted up
AM, that is, the RAM whose address is +256 is indexed and output, and is set in the register 3 in the next machine cycle 2, and at the same time, its control data is checked by the parity check circuit 4 and set in the V flip-flop 7. .

When a failure occurs in the OP code decoding in this way, by automatically switching to an extra word, it is possible to escape from the influence of the failure and avoid downtime of the information processing apparatus. In this embodiment, since the RAM of 1K word is used four times as much as the required amount of 256 words, even if a fixed fault occurs, the fault does not go down to three times. Further, if the fault is a temporary intermittent fault, it can be expected that the fault has been recovered by the time the counter 5 makes a round and returns to the original state.

〔The invention's effect〕

As described above, the present invention has a memory that is twice as large as a required memory, and when an abnormality is detected in a memory, successively indexes the memory to improve reliability without delaying access time. This has the effect.

[Brief description of the drawings]

FIG. 1 is a block diagram of an instruction decoding unit of an information processing apparatus according to one embodiment of the present invention, and FIG. 2 is a time chart showing an operation of the present embodiment. 1 ... instruction register, 2 ... OP code decoder, 3 ... register, 4 ... parity check circuit, 5 ... counter, 6 ... inverter, 7 ... V flip-flop, 8 ... arithmetic circuit.

 ──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Kazuhiko Gomi 1-17-114 Marunouchi, Kofu City, Yamanashi Prefecture Inside Kofu NEC Corporation (56) References JP-A-57-162193 (JP, A) JP-A-59-119761 (JP, A) JP-A-55-84099 (JP, A) JP-A-58-211400 (JP, A)

Claims (1)

(57) [Claims] An instruction register for holding an instruction word, a control memory in which the same data group is stored in a plurality of areas, and indexed by the instruction word held in the instruction register; Detecting means for detecting a data error; designating means for circulating the plurality of areas of the control storage to specify switching when the detecting means detects the data error; and detecting the data error. Inhibiting means for inhibiting the updating of the instruction register when detecting an error.