JP3000297B2 - memory - Google Patents

Description

The present invention relates to the field of semiconductor memories.

[Prior Art] In semiconductor technology, static memories are widely used. For example, this memory is often used for cache memory. Typically, this memory is manufactured from a plurality of bistable circuits (flip-flops), each forming one cell that stores one bit of data. In a memory array, bit lines are precharged to read data from cells. The bit lines are also used during writing by driving them to a desired state determined by the input data.

In the prior art, a two-port static memory is also known. One example of such a cell is U.S. Pat.
No.

As can be seen from the following description, the present invention
A two-port static memory is provided such that a modify-write operation can be performed in one memory cycle. The memory further includes circuitry for resolving write data conflicts that occur when one cell is accessed at both ports.

[Summary of the Invention] Improvement of a bistable memory cell will be described. The complementary node of the memory cell is connected to the complementary bit line of the memory array via the first field effect transistor. The gates of those transistors couple to word lines in the array. Employ a separate write line that couples to the complementary node of the cell. When the first transistor is off, the write line is cut off from the bit line. When the first transistor conducts, data is read from the cell to the bit line. During a read-modify-write operation, the bit line may be disconnected from the cell by the first transistor, so that after the data is read from the cell, the bit line may be precharged. Thus, data can be written to the cell from the write line without preventing the precharge of the bit line. After precharging, the bit line is immediately ready for a read operation during the next memory cycle.

The cell node is selectively coupled to ground during writing via a second transistor controlled by the write line. The second transistors are connected in series with a third transistor controlled by an extended word line (control) signal. This signal ends at the start of the next memory cycle. According to this configuration, the write line can be cut off from the cell under the control of the extended word line signal, so that reading is performed during the next memory cycle.

A circuit is disclosed for resolving any data conflicts presented to a two-port cell.

[Embodiment] A two-port memory employing a static memory cell will be described. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without such specific details. Will. Also, in some cases, to avoid unnecessarily obscuring the present invention,
Well-known circuits such as decoders are shown in the form of block diagrams, and detailed descriptions of other well-known matters are omitted.

Memory Overview In the currently preferred embodiment, the memory is part of a cache memory. The memory is manufactured using well-known complementary metal oxide semiconductor (CMOS) processing techniques. In the drawings, when a p-channel field effect transistor is indicated,
There is a small circle above the gate of the transistor, and no circle above the gate for n-channel field effect transistors. The memory employs normal bistable (flip-flop) cells.

Currently designed 2-port arrays have 4
There are 128 cell groups that include this cell. FIG. 1 shows one cell group as the cell group 10. Each cell group of four cells has two word lines, two extended word lines,
Pairs of first (complementary) write lines, four pairs of second (complementary) write lines, four pairs of first (complementary) bit lines, and four pairs of second (complementary) lines. ) Coupled to the bit line. FIG. 2 shows one of the four cell groups. The cell is coupled to two word lines, two extended word lines, first and second pairs of write lines, and first and second pairs of bit lines.

In FIG. 1, the word lines are collectively shown as WL1 (signal line 30) and WL2 (signal line 30). In FIG. 2, the word WL1
One of the signal lines is shown as a word line 310, and one of the word lines WL2 is shown as a word line 300. In FIG. 1, the extended word lines are collectively shown as EWL1 (signal line 33) and EWL2 (signal line 32). In FIG. 2, one signal line among the extended word lines is shown as a signal line 320, and another signal line is shown as a signal line 330. Signal lines 22, 23, 24 and 25, which are two pairs of write lines, are shown in both FIG. 1 and FIG. As described above, the write signal is generated inside the driving logic 17 via the signal line 19 inside the driving logic 17,
It is extracted from the input data supplied to the drive logic 17 via the signal line 19. FIG. 2 shows bit lines 51, 52, 53 and 54.
Are also shown.

The memory is coupled to receive two addresses, denoted as A1 (signal line 35) and A2 (signal line 36). Each address is decoded (decoder 1 for A1
3. Decoder 14 for A2. These decoders select word lines as usual. Decoder 13 has 128 WL1
One of the lines is selected, and the decoder 14 selects one of the 128 WL2 lines.

It is extended word line control signal generators 11 and 12 that generate extended word line signals. One such generator is shown in FIG. The generator 11 supplies an EWL1 signal via a signal line 33, and the generator 12 supplies an EWL2 signal via a signal line 32. There is one extended word line generator associated with each of the extended word lines, each generator coupled to an associated word line, as can be seen with reference to FIG. In practice, if a word line signal is present, it is expanded.

Data is transferred from cell to sense amplifier / precharge circuit
It is read out to the bit line via 18. Prior to sensing the data on the bit line, the bit line is precharged, as is well known in the art. The output data is supplied to the signal line 15. This output data is also coupled to the drive logic 17 for timing definition. Drive logic 17 couples the input data to the write line via the circuit shown in FIG. 5 when data is output during a read-modify-write operation.

The reset / set signal on lines 28 and 29 is
And supplied to 12. The signals are shown in FIG.
Hereinafter, description will be made with reference to FIG.

FIG. 2 shows one memory cell surrounded by a dashed line 40 in FIG. (Conventional static memory cells are often referred to as six-transistor cells and include a bistable circuit, shown in dashed line 40, and a pair of transfer transistors connecting the cells to complementary bit lines. In this application, the memory cell is defined as not including such a transistor because the complementary node of the flip-flop is coupled to a separate bit line and write line. The cell has transistors 41 and 42 cross-coupled with transistors 43 and 44. Node 45, which is the connection point between transistor 41 and transistor 42, is coupled to the gates of transistors 43 and 44. Similarly, transistors
The common connection point (node 46) between 43 and transistor 44 is coupled to the gates of transistors 41 and 42. node
45 is coupled to bit line 51 (BL1 #) via transistor 55 and bit line 52 (BL1 #) via transistor 56.
The signal ("#") coupled to 2 #) is used to indicate the complementary binary state, or the signal line carrying that state. ) Complementary node 46 is coupled to bit line 53 (BL2) via transistor 57 and to bit line 54 (BL1) via transistor 58.
Since the gates of transistors 58 and 55 are coupled to signal line 310, when this signal line 310 is positive, ie, high, the state of the cell can be sensed by BL1 and BL1 #. The gates of transistors 56 and 57 are coupled to signal line 300, and when this word line is high, data can be sensed on BL2 and BL2 #.

Nodes 45 and 46 are also coupled to write lines 22, 23, 24 and 25. One terminal of transistors 60 and 61 is coupled to node 45. The gate of transistor 61 is coupled to signal line 24. Node 46 is coupled to one terminal of transistors 62 and 63. The gate of transistor 62 is coupled to signal line 23, and the gate of transistor 63 is coupled to signal line 22. The other terminals of transistors 60 and 63 are coupled to ground via transistor 65. The gate of the transistor 65 is connected to the signal (EWL1
One of the signals). Similarly, the other terminals of transistors 61 and 62 are coupled to ground through transistor 64. The gate of this transistor is coupled to signal line 320 (and thus receives one of the EWL2 signals).

It should be noted that transistors 63 and 65 are coupled in series, like transistors 60 and 65. Similarly, transistors 62 and 64 and transistors 61 and 64 are coupled in series. Thus, for example, in the case of a write (data) transferred from the signal line 22 to the cell node 46, both transistors 63 and 65 must be conducting (associated with the write 1 # signal).
High with the EWL1 signal). As described below,
After the potential on the word line has risen in preparation for the next memory cycle, to prevent the bit line from coupling to ground,
This conduction is important because the EWL signal ends at the beginning of the cycle.

When the signal line 310 is selected, data is transferred from the cell via one port to BL1 and BL1 # (signal line 54, respectively).
Is read out to the signal line 51). When the signal line 300 is selected, data is similarly read from the cell to the bit lines BL1 and BL2 #. Address A1 and
Since A2 can be the same, the same cell or group of cells is selected. In the case of reading, this does not cause a problem since the data of the cell is read out to two pairs of bit lines.

Data is written to the cell from the write line. For example, if the EWL1 signal on signal line 330 is applied when the Write 1 signal is high and the Write 1 # signal is low, node 45 will be coupled to ground via transistors 60 and 65 and connected to the ground of the cell. Set the state. Similarly, data can be written to the cell from signal line write 2 and write 2 #.

In practice, data is written to cells via a "backdoor". That is, instead of via a bit line,
Usually, it is transferred via a transistor. This method may be used for a one-port memory cell using only a pair of bit lines and a pair of write lines. Also, depending on the memory, it may be advantageous to use one (non-complementary) bit line and one write line.

As described above, signal lines 300, 310, 320 and 330 are connected to cell 40.
Similarly, the bit and write lines are coupled to other cells located along the column containing cell 40.

Extended Word Line Generator Each extended word line includes one extended word line generator coupled to the associated word line. One such generator is shown in FIG. The generator basically consists of a bistable circuit (transistors 67, 68, 69 and 70). One node 74 provides the output (extended word line signal), and the other node 75 of the circuit is coupled via transistor 73 to the reset line 29. The gate of transistor 73 is coupled to (or is part of) the associated word line. Reset line 29 is also coupled to the gate of transistor 72. It is also coupled to the gate of transistor 72. This transistor pulls to ground node 74 when the reset signal is high. Set line 28 is coupled to the gate of transistor 71. When the set signal is high, node 75 couples to ground.

Every time a memory cycle begins, all word line generators are reset. This occurs when the potential on reset line 29 rises and the potential on set line 28 remains low. At this point, no potential appears on any of the word lines. The potential of the reset line 29 is a transistor
With 72 conducting, the bistable circuit is set such that node 74 is low, ie, no extended word line signal is applied. During a memory operation, such as a read-modify-write operation, the reset signal on reset line 29 remains low after a memory cycle is initiated and the potential on the selected word line is raised. When a word line signal is applied, transistor 73 conducts, pulling node 75 to ground potential via the reset line. In this case, the extended word line signal is applied as if during a read-modify-write operation. If no word line is selected,
Throughout the remainder of the cycle, node 74 remains at ground potential. (The set signal on set line 28 may be used to apply an extended word line signal. For example, this would be done when initializing all memory cells of the memory.) Operation and Timing During a normal read cycle, an address is applied to the address decoder to select one or two word lines. The selected cell or cells are then coupled to a bit line to provide an output. The bit line is first precharged, as is commonly done, so that the sense amplifier can sense the state of the cell faster. In the case of the illustrated memory organization, when the addresses are different,
One cell is coupled to one set of bit lines and another cell is coupled to another bit line, but the same address would connect one cell to both sets of bit lines. In the second case, the same data is read to two sets of bit lines.

Line 78 in FIG. 4 shows the waveforms 83 and 84 of the clock signal each starting one memory cycle. Line 79 is
7 shows a word line signal following address decoding after the generation of a clock signal. For example, the rising edge of waveform 85 (above time) is later than the rising edge of waveform 83 by time 86. Line 80 shows the extended word line signal. The EWL signal requires a word line signal to generate, so the EWL signal
Follows the L signal. As shown, the rising edge of waveform 87 is delayed by time 88 from the rising edge of waveform 85.

During a write operation, input data on signal line 19 is coupled to write lines 22, 23, 24 and 25. The extended word line generator associated with the selected word line is shown at line 80 in FIG.
Supply EWL signal. This signal continues until the point in time at which the potential of the word line signal drops in the cycle. This allows the write line to be coupled to the cell and set the cell to an appropriate state. Hereinafter, read-change-
Regarding the write operation, the timing of the EWL signal will be described.

Significantly, the present invention allows a read-modify-write operation to be performed on one or more selected cells in a single memory cycle, as described below.

When the potential of the word line rises in common with the read operation and the first part of the read-modify-write operation, the state of the cell can be sensed by the bit line that has been precharged. When the EWL signal is applied, transistor 64 or transistor 65, or possibly the two transistors, conduct. However, in a read-modify-write operation, no cells are written as a result. The drive circuit that supplies the write line signal does not supply data until the sense amplifier latches the output data. Thus, the output of the sense amplifier is also coupled to drive circuit 17. When the drive circuit senses that there is data on the output data line 15, the write line is activated. At this point, for example, data is written to the cell because transistors 60 and 65 are both conducting. The data output is represented by waveform 89 on line 81 in FIG. 4 and the write signal is represented by waveform 90 on line 82. The write signal is delayed by a time 91 from the rising edge of the data output signal.

If data is sensed, the potential on the word line drops, isolating the bit line from the cell. As a result, the bit lines are precharged in preparation for the next memory cycle. The next clots signal is generated. It is important that the EWL generator is reset so that the EWL signal falls. This is indicated by line 92. It is important to note that the potential of the EWL signal drops before the next word line signal appears. Note the time point 93 between the falling edge of waveform 87 and the rising edge of waveform 94. This can prevent the charge on the bit line from being dispersed by the write operation. Therefore, the read-modify-write operation can be performed in one memory operation, and in fact, in the memory according to the present invention, the read-modify-write operation can be performed one after another.

Alternatively, the write line can be clamped when a clock is generated in the next cycle.

Resolving Data Conflicts As mentioned above, in the currently preferred embodiment,
A1 and A2 may select the same cell, and in a write operation, conflicting data is applied to a write line. The circuit of FIG. 5 senses that such a situation has occurred and places the cell in a predetermined state when a data conflict occurs.

The circuit for resolving the conflict includes address lines A1 and
A comparator 99 is provided for generating an output signal on the signal line 100 when the address of A2 is the same. The signal on signal line 100 is applied to the input terminals of NAND gates 105 and 106. NAND gate
The other terminal of 106 is coupled to receive the Write 1 input signal. The other terminal of NAND gate 105 is coupled to receive a write 2 # input signal. The write 1 input signal is applied through serial inverters 101 and 102 to generate a write 1 signal on signal line 25.
The write 1 # input signal is applied to one input terminal of the NAND gate 103. The output of inverter 101 is NAND gate 103
It is also an input to. The third input to this gate is NAND
This is the output of the gate 105. The output of gate 103 is an inverter
Combined via 104 to generate a 1 # signal written to signal line 22. The write 2 # input signal is applied to one input terminal of the NAND gate 107. The output of NAND gate 106 is N
Form another input of AND gate 107. Write 2 input signal is coupled to gate 1 after being coupled through inverter 109.
This is the third input to 07. After passing through the inverter 108, the output of the NAND gate 107 is written to the signal line 23 and appears as a 2 # signal. Write 2 input signal is inverter 10
Combined via 9 and 110 to write to signal line 24 2
Generate a signal.

First, it is assumed that the address lines A1 and A2 are different. The potential of the signal line 101 is low, and the conditions of the NAND gates 105 and 106 are not satisfied. Since these gates are NAND gates, a high input is provided to NAND gates 103 and 107. As a result, gates 105 and 106 and their outputs are effectively excluded from the rest of the circuit. For example, regardless of the input of the write 1 input line, NA
The output of ND gate 106 remains high.

When the circuit of FIG. 5 is considered without the NAND gates 105 and 106, it can be easily understood that the write 1 signal appears on the signal line 25 without changing its state because it passes through two inverters. Similarly, the write 2 input signal is
After passing through 109 and 110, it appears on signal line 24 unchanged. If the write 1 # input signal is high, the input from the inverter 101 goes low because the write 1 input signal and the write 1 # input signal are complementary. In this way, all the conditions of the NAND gate 103 are met and the output of this gate goes low. Similarly, as long as the addresses do not match, the write 2 # input signal appears on signal line 23 unchanged.

Next, consider a case where an address match occurs and both the write 1 input signal and the write 2 input signal are high. (This is the case when the data is not conflicting.) Since the inputs to NAND gates 105 and 106 are both high, the outputs of these gates are both low. Therefore, the conditions of NAND gates 103 and 107 are not met and the outputs of these two gates are high. After the output of the gate 103 passes through the inverter 104, a low write 1 #
Form a signal. The output of gate 107 goes high, and after passing through inverter 108, a low signal appears on signal line 23. Thus, in the case of non-conflicting data, the write 1 signal and the write 2 signal are high, and the write 1 # signal and the write 2 # signal are low.

Another case where the data does not conflict occurs when the write 1 input signal and the write 2 input signal are low. When the Write 1 input signal is low,
The condition of NAND gate 106 is not satisfied, and gate 107 to gate 10
A high input is applied to 6. Write 2 # input signal is N
Like the output of AND gate 109, it is high. That is, all the conditions of the gate 107 are satisfied, and a low output is generated from this gate. This output generates a high output on the signal line 23 after passing through the inverter 108. Similarly, a high output appears on the signal line 22.

In the event of a data conflict, if a match occurs, the positive signal on either the write 1 input signal line or the write 2 input signal line will prevail, setting the flip-flop to a predetermined state (cell node 45 low). ). For example, if Write 1 input signal is high and Write 2
When the input signal is low, the output of the NAND gate 106 is low because the condition of the NAND gate 106 is satisfied. As a result, the output of gate 107 goes high and the output of gate 108 goes low. Essentially, the high signal of the write 2 # input signal is gate 10
7, the data conflict is suppressed. The same is true if the Write 2 input signal is high and the Write 1 input signal is low. At that time, the output of gate 105 is low,
Gate 103 suppresses the high write 1 # input signal.

Thus, data conflicts are resolved to bring the cells into a predetermined state.

Thus, a memory has been described that allows a read-modify-write cycle operation to be performed in a single memory cycle.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the general layout of a memory employing the present invention, and FIG. 2 shows a presently preferred embodiment of one two-port static memory cell, with two pairs of bit lines and two pairs of bit lines. FIG. 3 is a wiring diagram showing a state of coupling to a pair of write lines, two word lines, and two extended word lines; FIG. 3 is a wiring diagram of an extended word line control signal generator;
FIG. 4 is a timing diagram showing some waveforms associated with the operation of the memory of the present invention, and FIG. 5 is used to resolve data conflicts when two addresses select one two-port cell. FIG. 2 is a wiring diagram showing a circuit to be used. 10 ... cell group, 11, 12 ... extended word line control signal generator, 13, 14 ... address decoder, 17 ... drive logic, 18
…… Sense amplifier / precharge circuit, 22,23,24,25…
... Write line (WL), 28 ... Set line, 29 ... Reset line, 30,300,31,310 ... Word line (WL1, WL2), 32,320,3
3,330 …… Extended word lines (EWL1, EWL2), 41,42,43,44…
… Transistors, 45, 46 …… Complementary nodes, 51, 52, 53, 54
…… Bit lines (BL), 55, 56, 57, 58, 60, 61, 62, 63, 64, 6
5,67,68,69,70,71,72,73 …… Transistor, 74,75…
Ground point nodes, 101, 102, 104, 108, 109, 110 ... inverters, 103, 105, 106, 107 ... NAND gates.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G11C 11/41

Claims (2)

(57) [Claims] 1. A memory having at least one bistable memory cell, wherein said memory cell is coupled to a bit line via a first transistor having a gate coupled to the word line. The word line signal of the line enables reading of data from the memory cell in the active state, and separates the memory cell from the bit line in the inactive state. A write line for receiving the new data in one of two states to be written to the memory cell, so that writing of the new data to the memory cell can be performed in a single memory cycle; Is selectively coupled to the memory cell, and the new data is transferred according to the new data of the write line. Coupling means including first and second switching means for taking an extended state; and a signal generator for generating an extended word line signal for controlling the second switching means. A line signal for coupling the new data to the memory cell as indicated by the state of the first switching means without disturbing the precharge when the bit line is precharged. A signal for controlling the means, wherein the signal becomes active in response to the active state of the word line signal, stays active even when the word line signal is inactive, and immediately before the start of a new memory cycle, A memory in an inactive state for separating new data from the memory cells. 2. A memory having a bistable memory cell having a first port and a second port, the memory comprising:
The first port is provided with a first bit line coupled to the memory cell and a first word line coupled to the memory cell, the first word line being active. And the memory cell are selected, and the second port is provided with a second bit line coupled to the memory cell and a second word line coupled to the memory cell. The memory cell is selected when the word line is active, a) comprising a first write line associated with the first port for receiving first data to be written to the memory cell; b) First coupling means for selectively coupling the first data to the memory cells in response to a first extended word line signal; c) a first generating the first extended word line signal Extended word line signal generator A first extended word line signal generator for activating the first extended word line signal in response to an active state of the first word line signal; d) associated with the second port. And a second write line for receiving second data to be written to the memory cell; e) selectively coupling the second data to the memory cell according to a second extended word line signal. F) a second extended word line signal generator for generating the second extended word line signal, wherein the second extended word line signal generator generates the second extended word line signal according to an active state of the second word line signal. A second extended word line signal generator for activating an extended word line signal; g) being coupled to said memory cell, said first word line and said second word line being active; The first data A memory for conflict resolution means for suppressing the second data when the data is not the same as the second data.