JP2998334B2 - ECL type semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ECL circuit, and more particularly to an emitter follower for driving a load capacitance.

[0002]

2. Description of the Related Art A conventional ECL circuit, as shown in FIG.
One terminal of each of the two collector resistors 36 is connected to the power supply voltage VCC (or GND) terminal 45, and the other terminal is connected to the collector of the transistor 39 and the transistor 40.
, The base of the transistor 39 becomes the input voltage V _IN terminal 34 and the transistor 40
Base is a reference power supply V _R terminal 37. The emitters of the transistors 39 and 40 are connected to each other, and the emitters of the transistors 39 and 40 are connected to the collector of a transistor 41 whose base is the constant current reducing power supply V _CSI terminal 37. One terminal of a resistor R _CS is connected to the emitter of the transistor 41, and the other terminal is connected to a power supply voltage VEE terminal 46 to form an ECL basic gate circuit.

The collector of a transistor 42 has a power supply voltage V
CC (or GND), the base is connected to the collector of the transistor 39, the emitter is connected to one terminal of the resistor 43, and the other terminal of the resistor 43 is connected to the power supply voltage VEE terminal to form an emitter follower. Further, a wiring load capacitance 44 is connected to the emitter of the transistor 42, and an ECL including a basic gate circuit and an emitter follower is provided.
Circuit.

In this conventional ECL circuit, the collector output of the transistor 39 is input to the emitter follower, the transistor 42 is turned on, the output signal of the emitter follower is changed from low level to high level, and the transistor 42 is turned off to load the wiring. By discharging the charge of the capacitor through the resistor 43, the load is driven from the high level to the low level to drive the load.

[0005]

In this conventional ECL circuit, the electric charge of the wiring load capacitance is discharged through a resistor connected to the emitter of the transistor of the emitter follower.
There is a problem that it takes more time to fall than the rise of the output signal charged by the transistor, and as a result, the propagation delay time of the output signal becomes longer.

An object of the present invention is to provide an ECL type semiconductor integrated circuit device capable of preventing a delay in propagation time of an output signal.

[0007]

An ECL circuit according to the present invention comprises a push-pull circuit in which a resistor connected to the emitter of an emitter follower is replaced with a transistor, a clamp transistor for biasing the base of a pull-down transistor, a high-resistance bias resistor or A reverse bias diode and a capacitor for coupling the input voltage terminal and the base of the pull-down transistor are provided.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 shows an ECL circuit according to a first embodiment of the present invention.
One terminal of each of the two collector resistors 3 is connected to the power supply voltage VCC (or GND) terminal 15, the other terminal is connected to the collector of the transistor 8 and the collector of the transistor 9, respectively, and the base of the transistor 8 is connected to the input voltage. V _iN terminal 1, and the base of the transistor 9 becomes a reference power supply V _R terminal 2. The emitters of the transistors 9 and 10 are connected to each other, and the collector of the transistor 10 whose base is the constant current reducing power supply V _CSI terminal 7 is connected to the common emitter of the transistors 9 and 10. One terminal of the resistor 4 is connected to the emitter of the transistor 10, and the other terminal is connected to the power supply voltage VEE terminal 16 to form an ECL basic gate circuit.

The collector of the transistor 12 has a power supply voltage V
CC (or GND), the base is connected to the collector of the transistor 9, the emitter is connected to the collector of the transistor 13, and the emitter of the transistor 13 is connected to the power supply voltage VEE terminal. The collector of the transistor 11 whose base is the clamp voltage V _CLAMP terminal 6 is connected to VCC 15, and the emitter is connected to the base of the transistor 1. One of the bias resistors 14 is connected to the emitter of the transistor 11 and the other is connected to the VEE terminal 16. Further, one terminal of the coupling capacitor 5 is connected to VIN.
ECL connected to terminal 1 and the other terminal being an emitter follower connected to the base of transistor 13
Make up the circuit.

In this ECL circuit, the base-emitter voltage V _BE of the transistor 13 is constantly biased by the clamping transistor 11 in order to speed up the impulse response of the transistor 13 for pull-down. When the input voltage changes, a current flows through the coupling capacitor 5, and this current flows into the base of the transistor 13,
This base potential is raised. And the wiring load capacitance 17
By driving the electric charge to the transistor 13 at high speed and discharging the electric charge, the fall time of the output signal can be shortened.

FIG. 2 shows an ECL circuit according to a second embodiment of the present invention. In the second embodiment, a part of the bias current of the pull-down transistor 13 flows through the bias resistor 14 by several tens μA because the bias resistor 14 shown in FIG. Therefore, in this embodiment, as shown in FIG. 2, the collector of the transistor 47 is connected to the emitter of the transistor 28, and the base and the emitter of the transistor 47 are both connected to the power supply voltage VEE terminal 32.

Since the base and the emitter of the transistor 47 are always at the same potential, the transistor 47 is always off, and the emitter node of the transistor 28 and the VEE terminal 32 are equivalent to the open state. Therefore, all of the emitter current of the clamping transistor 28 flows into the base of the transistor 30 and can be driven at a higher speed than in the first embodiment.
The output signal propagation delay time can be reduced as compared with the CL circuit.

FIG. 3 shows a circuit configuration in which both an in-phase output and an opposite-phase output with respect to an input signal are output from an emitter follower circuit. In the figure, when a signal or reference voltage is applied to the base electrode of the bipolar transistor 2-1 or 2-2, the emitter followers 2-3 and 2-4
Bipolar transistors 2-5 and 2-6 are connected to the base of the output so that a signal having the same phase as the input signal is input to the base via a capacitor. The operating principle is the same as in FIG.

FIG. 4 is a detailed circuit including a bias circuit, and is a fourth embodiment using the basic circuit of FIG. In FIG. 1, the emitter follower circuit shown in FIG. 1 is specifically composed of bipolar transistors 4-1 and 4-2 and a resistor 4-.
3. An input signal is applied to an input terminal 4-9, and a reference voltage is applied to a reference voltage application terminal 4-10. A constant voltage 4-4 from a constant voltage circuit is applied to the base of the bipolar transistor 4-2, and a constant current flows through the emitter follower.

Further, a collector of the bipolar transistor 4-5 is connected to the output terminal 4-13 of the emitter follower, the emitter is connected to the power supply 4-12, and the base is connected to the input signal via the capacitor 4-8. It is connected to an output current switching circuit. The base of the bipolar transistor 4-5 is connected to the anode electrode of the diode 4-6 and the resistor 4-7, the cathode electrode of the diode is connected to the power source 4-12, and the other electrode of the resistor is connected to the power source 4-11. Have been.

The reason why the diode 4-6 is inserted between the base and the emitter of the bipolar transistor 4-5 is to provide a temperature guarantee to this circuit. Even when the temperature changes, a current always equal to the product of the current flowing through the diode 4-6 and the ratio of the diode 4-6 and the area coefficient of the bipolar transistor 4-5 flows through the transistor 4-5. Power supply 4-11
The current flowing through the resistor 4-7, the diode 4-6, and the power supply 4-12 is set to a very small current.

The first reason is that this bias circuit simply supplies a constant voltage to the base of the bipolar transistor 4-5, so that a large current is not required. Second,
This is because the impedance when viewing the bias circuit side (node 4-14) from the base of the bipolar transistor 4-5 needs to be set sufficiently higher than the input impedance of the bipolar transistor 4-5. This is because if the impedance of the node 4-14 is lowered, the electric charge flowing into the base of the bipolar transistor 4-5 via the capacitor 4-8 according to the change of the input signal does not flow to the base side, but the resistance 4-7 and the diode This is because the distribution is performed according to the ratio of the parallel impedance of the forward impedance of 4-6 to the input impedance of the base.

In this state, the bipolar transistor 4-
5 cannot be biased high enough (bipolar transistor 4-5 will not be active) and the charge on the parasitic capacitance will not be completely discharged through bipolar transistor 4-5. In order to supply a minute current to this bias circuit, the resistance value of the resistor 4-7 is increased to allow the minute current to flow. At this time, a minute current flows through the diode 4-6, and the impedance in the quasi-direction of the diode can be increased to some extent in the minute current region as shown in FIG. 5, so that the impedance of the node 4-14 can be increased. FIG. 5 shows the current-voltage characteristics of the diode. It can be seen that the forward impedance can be increased to some extent in the low current region.

FIG. 6 shows the relationship of the propagation delay time when the capacitance applied to the output terminal 4-13 in the circuit of FIG. 4 is changed. A curve 6-1 shows a conventional ECL circuit, and shows how the delay time increases as the parasitic capacitance increases. This is because, as described above, the discharge time when the output potential becomes a constant potential is determined by the time constant of the product of the output impedance of the emitter-follower and the parasitic capacitance, and the delay time is proportional to the increase in the parasitic amount. Becomes longer.

On the other hand, curve 6-2 is the result of the circuit of FIG. 4 according to the present invention. Unlike the conventional circuit, the discharge when the output potential becomes a constant potential flows through the transistor shown in FIG. 4, so that the delay time does not increase much even if the parasitic capacitance increases.

FIG. 7 shows a fifth embodiment of the present invention. First
The point different from the embodiment is the configuration of the emitter-follower. The emitter of a bipolar transistor 7-1 forming an emitter-follower is connected to a power supply 7-3 via a resistor 7-2.
It is connected to the. The power supply of the current switching circuit is 7-4, and normally 7-3 is set higher than 7-4. This is because the emitter follower operates at a voltage obtained by adding a certain voltage to the logic amplitude. By doing so, power consumption can be reduced.

Bipolar transistor 7-5 shown in FIG.
Is connected to the output node 7-6, and the operating principle is exactly the same as in the first embodiment.

[0023]

As described above, according to the present invention, the collector of a bipolar transistor is connected to the output of an emitter-follower circuit which outputs a signal having a phase opposite to that of an input signal. A circuit configuration in which the output signal is connected to the base of the bipolar transistor via a capacitor, the emitter of the bipolar transistor is connected to the power supply, and the base and the emitter of the bipolar transistor are biased so that a slight current flows through the bipolar transistor. By doing
Even if the parasitic capacitance of the wiring or the like increases, there is an effect that the increase in the delay time is reduced.

Further, in the load circuit according to the present invention, almost no current flows in the steady state, and the current flows only during the transition time showing the effect of the present invention, so that the increase in power consumption can be suppressed.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a third embodiment of the present invention.

FIG. 4 is a circuit diagram showing a fourth embodiment of the present invention.

FIG. 5 is a diagram showing current-voltage characteristics of a diode.

FIG. 6 is a diagram illustrating delay times in the present invention and a conventional example.

FIG. 7 is a circuit diagram showing a fifth embodiment of the present invention.

FIG. 8 is a circuit diagram showing a conventional example.

[Explanation of symbols]

 1,18,34 Input voltage V_INTerminals 2, 19, 35 Reference voltage V_RTerminals 3, 20, 36 Collector resistance R_C  4,21,38 Resistance R_CS  6,23 Clamp voltage V_CLAMPTerminals 7, 24, 37 Power supply V for constant current source_CSI  14 Bias resistor R_BIAS  15, 31, 45 Power supply voltage VCC (GND) terminal 16, 32, 46 Power supply voltage VEE terminal 43 Resistance R_E  17, 33, 44 Wiring load capacitance C_L

Claims (2)

(57) [Claims] 1. One terminal of each of a first resistor and a second resistor is connected to a high-potential power supply, and the other terminal of the first resistor is connected to the collector of a first transistor, and the other terminal of the second resistor is connected to a second transistor. A base of the first transistor is connected to an input voltage terminal, and a base of the second transistor is connected to a reference voltage;
The emitters of the first and second transistors are connected to each other, the common emitter is connected to the collector of a third transistor, and the emitter of the third transistor is connected to one terminal of a third resistor and is connected to the other terminal. ECL with terminal connected to low power supply and base connected to constant voltage power supply
The basic gate circuit, the collector of the fourth transistor is connected to the high power supply, the base is connected to the collector of the first transistor, the emitter is connected to the collector of the fifth transistor, and the emitter of the fifth transistor is connected to the low power supply; The collector of the transistor is connected to the higher power supply, the emitter is connected to the base of the fifth transistor, the emitter of the sixth transistor is connected to one terminal of a fourth resistor or diode, and the other terminal is connected to the lower power supply. And an emitter follower having one terminal connected to the input voltage terminal and the other connected to the base of the fifth transistor.
L-type semiconductor integrated circuit device. 2. An ECL type semiconductor integrated circuit device having an emitter-coupled type current switching switch circuit and an emitter follower circuit, wherein a collector of a bipolar transistor is connected to an output of the emitter follower circuit which outputs a signal having a phase opposite to that of an input signal. An output signal having the same phase as an input signal of the current switching switch circuit is connected to the base of the bipolar transistor via a capacitor, an emitter of the bipolar transistor is connected to a power supply, and the bipolar transistor is connected between the base and the emitter of the bipolar transistor. An ECL-type semiconductor integrated circuit device, comprising: means for biasing a voltage at which a slight current flows through a transistor.