JP2996832B2 - Microcomputer for PWM waveform control - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer having a function of outputting a PWM waveform signal, and more particularly to a microcomputer for controlling a three-phase AC motor by a PWM waveform signal.

[0002]

2. Description of the Related Art There is a type in which the rotation speed of a three-phase AC motor for driving a compressor or the like is inverter-controlled by a one-chip microcomputer. A microcomputer used for this purpose includes a CPU having a system operation control function and a circuit for generating a PWM waveform signal for controlling an inverter. A circuit for generating a PWM waveform signal includes a digital circuit unit for setting a pulse width and a P circuit.
And an analog circuit for forming and outputting a WM waveform signal.

[0003] When an inverter is controlled for a three-phase AC motor, each of the three windings is connected to the minus side of the power supply.
Side, two transistors (power transistors) for connecting to the + side and the-side of the power supply are connected to the winding (see FIG. 1), and one of them is connected to the rotation angle of the rotor. Only the transistor is turned on.

In order to drive the motor with a high driving force (ideally), it is preferable to turn off one transistor and turn on the other transistor at the same time. However, the transistor takes a certain amount of time to shut off. If both transistors are turned on / off at the same time, both transistors are turned on simultaneously at the switching timing, and the power supply is short-circuited. Therefore, the on-timing of the other transistor is delayed by a predetermined time (delay time) from the off-timing of the one transistor to create an all-off period d (see FIG. 2).

The length (delay time) of the all-off period d
Is stored in the register of the digital circuit as the count number of the clock signal, and is read when the pulse width is set.

[0006]

On the other hand, the analog circuit of the one-chip microcomputer is susceptible to temperature and the like, and the generated PWM waveform signal sometimes has a deviation in pulse width.

[0007] When a shift occurs, there is a problem that the all-off period becomes too short or too long. If the all-off period becomes too short, a period occurs in which the two transistors are simultaneously turned on as described above, and at this time, the power supply current may flow short-circuited through these two transistors, adversely affecting the system. On the other hand, when the all-off period is too long, there is a disadvantage that the driving force of the motor is reduced.

However, in a conventional drive control system for a three-phase AC motor, a current monitoring device is provided in a power supply system, and when the current monitoring device detects an overcurrent or the like, the system is determined to be abnormal. However, it was possible to detect only when the all-off period greatly fluctuated. For this reason, it is not possible to prevent a minute shift during the all-off period and a leak due to the shift, and there is a risk that reliability with respect to noise, durability, and the like may be reduced.

The present invention relates to a PW generated by an analog circuit.
It is an object of the present invention to provide a microcomputer capable of promptly responding by detecting a shift in the pulse width of the M waveform signal internally.

[0010]

SUMMARY OF THE INVENTION The present invention is a microcomputer for turning on / off first and second switch means for selectively connecting a load terminal to a positive electrode or a negative electrode of a power supply with a PWM waveform signal. After switching the PWM waveform signal output to one switch means from the ON signal to the OFF signal, and after a predetermined all-off period has elapsed, the PWM waveform signal output to the other switch means is changed from the OFF signal to the ON signal. In the switching microcomputer, an allowable time setting means for setting an allowable minimum time and an allowable maximum time of the all-off period, and a PWM waveform signal output to the first and second switch means, both of which are off signals Monitoring whether the all-off period is within the normal range between the minimum allowable time and the maximum allowable time. A period monitoring unit, an abnormal signal output unit that counts up the number of times that the all-off period monitoring unit detects that the all-off period is not in the normal range, and generates and outputs an abnormal signal when the count value reaches a predetermined value; , Are incorporated in one chip.

Further, in the present invention, the abnormal signal output means includes means for counting down the count value when the all-off period monitoring means detects that the all-off period is within the normal range a predetermined number of times. It is characterized by the following.

[0012]

One of the two PWM waveform signals output to the first and second switch means is switched from an ON signal to an OFF signal, and the other is switched from an OFF signal to an ON signal after an all-off period has elapsed. Be replaced. The all-off period monitoring means monitors whether or not the all-off period is within an allowable range (between the shortest allowable time and the longest allowable time), and counts up the number of times the all-off period is out of the normal range.
When the count value reaches a predetermined value, an abnormal signal is generated and output assuming that the PWM waveform signal (all-off period) is not normal. Based on this abnormality signal, the control can perform a predetermined abnormality response operation. By setting the allowable minimum time and the allowable maximum time in a narrow range, a minute shift can be detected.

Further, in the present invention, the count value is subtracted according to the number of times that the all-off period is within the normal range. This cancels the rare error,
Output of an abnormal signal due to accumulation of such errors can be prevented.

[0014]

FIG. 1 is a block diagram of a compressor control circuit using a microcomputer for controlling a PWM waveform according to an embodiment of the present invention. FIG. 2 is a timing chart of a PWM waveform signal for driving the three-phase AC motor 5 in the compressor control circuit.

The three windings 5a, 5b, 5c of the three-phase AC motor 5, which is the power source of the compressor, are connected to the positive terminal of the power source 3 via transistors 4-1 to 4-3, respectively. And transistors 4-0, 4-2,
It is connected to the negative pole of the power supply 3 via 4-4. Each winding 5
a, 5b, 5c, two transistors (4-0, 4-1), (4-2, 4-3), (4-4,
4-5) are paired, and are controlled so that only one of them is turned on. That is, control is performed so that one transistor is turned off and then the other transistor is turned on (see FIG. 2). In this control, the timing to turn on the other transistor is delayed by a minute time d from the timing to turn off one transistor so that the two transistors are not turned on at the same time due to the delay of the shut-off time of the transistor. This minute time d is the all-off period. This avoids a short-circuit state in which one transistor is not completely turned off and the other transistor is turned on, so that a current flows directly from the positive pole to the negative pole of the power supply 3.

The PWM waveform signal shown in FIG.

PW output from microcomputer
After the M waveform signal is isolated by the photocoupler 2, each of the transistors 4-0, 4-1, 4-2, 4-3,
Input to bases 4-4 and 4-5.

FIG. 3 is a diagram showing the configuration of the microcomputer 1. The microcomputer 1 includes a CPU 10 as a control unit, and further includes a digital circuit and an analog circuit for forming a PWM waveform signal. The digital circuit is composed of an all-off period setting register 11, an all-off period setting counter 12, and a PWM waveform setting circuit 13, and the analog circuit is a PWM circuit.
It comprises a waveform generating circuit 14. In addition, the microcomputer 1 has a built-in abnormality detection circuit 15 for detecting an abnormality in the PWM waveform signal.

The CPU 10 receives a compressor control signal from outside. In the case of an air conditioner, a compressor control signal is generated based on the indoor temperature, a set temperature, and the like. CPU 10 determines ON / OFF and rotation speed of motor 5 based on the input compressor control signal, and outputs a PWM waveform control signal. This PWM waveform control signal is input to the PWM waveform setting circuit 13. PWM
The waveform setting circuit 13 generates a pulse width signal based on this signal. The pulse width signal determines the polarity of the voltage applied to each of the windings 5a, 5b, 5c of the three-phase AC motor 5, and includes transistors 4-0 / 4-1 and 4-
This is for instructing the switching timing of the ON signal to be output to 2 / 4-3, 4-4 / 4-5. Three pulse width signals are generated corresponding to each of the windings 5a, 5b, 5c.

The pulse width signal is input to the PWM waveform generation circuit 14. Six PWM waveform generating circuits 14 are provided in parallel corresponding to the six transistors 4-0 to 4-5. Further, an all-off period setting counter 12 is connected to the PWM waveform generating circuit 14. The all-off period setting counter 12 outputs a count end signal to the PWM waveform generation circuit 14. PWM waveform generation circuit 14
Is based on the pulse width signal and the count end signal.
Generate a WM waveform signal. That is, when a pulse width signal (OFF signal) is input, the PWM waveform is immediately changed to “H”.
When a pulse width signal (ON signal) is input,
After the count-off signal is input from the all-off period setting counter 12, the PWM waveform is set to "L".

Here, the all-off period setting counter 12
Is connected to an all-off period setting register 11. The all-off period setting register 11 stores the count number of the all-off period d. The all-off period setting counter 12 starts counting when a pulse width signal (a signal for inverting the polarity of the winding) is input from the PWM waveform setting circuit 13, and starts counting when the count number corresponding to the all-off period d is counted. A count-up signal is output to the PWM waveform generation circuit 14 which turns on the transistor (drops the PWM waveform to "L") based on the pulse width signal thus obtained. The all-off period setting register 11
Is set by the CPU 10 at the time of startup.

The PWM waveform signals PWM0 to PWM5 formed and output as described above are applied to the bases of the transistors 4-0 to 4-5 via the photocoupler 2 and are sent to the abnormality detection circuit 15 in the microcomputer 1. Is entered. The abnormality detection circuit 15 includes the PWM waveform generation circuit 1
4 are provided in parallel, whereas each winding 5a,
Three are provided corresponding to 5b and 5c (transistor pair). Two PWM waveform signals PWMi, PWMi + 1 (i = 0, 2, 4) are input to each abnormality detection circuit 15, respectively. The abnormality detection circuit 15 measures the all-off period from the two input PWM waveform signals, and monitors whether the period is equal to or longer than the allowable minimum time and equal to or shorter than the allowable maximum time.
When it is detected that the all-off period is out of the allowable range, the counter is counted up, and an abnormal signal is output to the CPU 10 when the counted number becomes a predetermined value or more.

FIG. 4 is a configuration diagram of the abnormality detection circuit. FIGS. 5 to 7 are timing charts of signals of various parts of the abnormality detection circuit. PWM waveform signals (PWMi, PWM
Mi + 1) is input to the AND circuit 21 and the XOR circuit 27. PWM waveform signal is active low (see Fig. 2)
Therefore, during the all-off period, PWMi, PWMi +
1 are both “H”, and the AND circuit 21 is “H”
(All-off detection signal). The XOR circuit 27 outputs “H” when only one PWM waveform signal is “H”.
(Normal operation detection signal). The normal operation detection signal of the XOR circuit 27 is input to the AND circuit 28 and input to the shortest all-off period monitoring counter 24 and the longest all-off period monitoring counter 32 as a load signal LD.

The shortest all-off period monitoring counter 24
When the load signal LD is inputted, the count value of the allowable minimum time stored in the shortest all-off period monitoring register 23 is loaded. Further, when the load signal LD is input, the longest all-off period monitoring counter 32 loads the count value of the allowable maximum time stored in the longest all-off period monitoring register 31.

The all-off detection signal of the AND circuit 21 is transmitted to the AND circuit 22 and the reset pulse generation circuit 26.
Is input to The clock signal CLK is input to another input terminal of the AND circuit 22. Therefore, the clock signal CLK is output through the AND circuit 22 only during the all-off period. This clock signal is output to the shortest all-off period monitoring counter 24 and the AND circuit 30.

The shortest all-off period monitoring counter 24 is a down counter, and counts down the loaded value (the count value of the allowable minimum time) by inputting the clock signal CLK, and outputs the borrow signal BR1 when the countdown is completed. Therefore, this borrow signal BR
1 is a signal indicating that the all-off period is longer than the allowable minimum time. This borrow signal BR1 is latched by the latch circuit 25.

The latched signal is input to an AND circuit 30, and is inverted and then input to an AND circuit 28. The other input terminal of the AND circuit 28 has the XO
The normal operation detection signal of the R circuit 27 is input. Therefore, even when the AND circuit 28 shifts to the normal operation from the all-off period, when the borrow signal BR1 is not input from the latch circuit 25, the AND circuit 28 determines that the all-off period is too short and outputs the "H" signal (the short-circuit abnormality detection signal). ) (FIG. 6)
reference).

This short-circuit abnormality detection signal is input to the abnormality detection counter 34 via the OR circuit 29. The abnormality detection counter 34 updates the count value each time an abnormality detection signal is input. This count value is input to the comparison circuit 36. The value stored in the abnormality detection register 35 is input to the comparison circuit 36. The comparison circuit 36 outputs an abnormality signal to the CPU 10 when the count value of the abnormality detection counter 34 becomes larger than the value stored in the abnormality detection register 35.

On the other hand, as described above, the borrow signals BR 1, BR 1,
Further, a clock signal CLK output only during the all-off period from the AND circuit 22 is input. Therefore,
The AND circuit 30 outputs the clock CLK after the elapse of the minimum allowable time and until the all-off period ends. This clock signal CLK is the longest all-off period monitoring counter 3
2 is input. Longest all-off period monitoring counter 32
Calculates the value loaded from the longest all-off period monitoring register 31 (the count value of the allowable maximum time) as the clock signal LC.
Count down by K. If no clock signal is input before the countdown of this value is completed, the longest all-off period monitoring counter 32 does not output the borrow signal BR2 because the all-off period is within the allowable maximum time.

On the other hand, the longest all-off period monitoring counter 3
If the clock signal CLK has been input to the period 2 in which the count value of the maximum allowable count value has been counted down, the longest all-off period monitoring counter 32 outputs the borrow signal BR2. Therefore, this borrow signal BR2
Means that the all-off period is too long. The borrow signal BR2 is latched by the latch circuit 33. The borrow signal BR2 latched by the latch circuit 33 is input to the abnormality detection counter 34 via the OR circuit 29 as an excessively long abnormality detection signal.

The latch circuits 25 and 33 are reset by a reset pulse generated by a reset pulse generating circuit 26. This reset pulse generation circuit 26
A reset pulse is generated based on the all-off detection signal of the ND circuit 21.

As described above, when the all-off period is shorter than the allowable minimum time, the shortest all-off period monitoring counter 2
4 does not output the borrow signal BR1, the abnormality is detected. When the all-off period is longer than the allowable maximum time, the abnormality is detected by the longest all-off period monitoring counter 32 outputting the borrow signal BR2.

It is assumed that the count value stored in the shortest all-off period monitoring register 23 and the longest all-off period monitoring register 31 is set to be as narrow as necessary and sufficient for the transistor 4 to turn off. Thus, even a slight deviation during the all-off period can be detected as an abnormality in the microcomputer.

In this circuit, the abnormality detection counter 3
4 counts the short-term abnormality detection signal and the excessive-length abnormality detection signal together, but these may be counted by separate counters. Further, these count values may be added up for the three abnormality detection circuits.

Further, in the abnormality detection circuit 15 of this embodiment, the abnormality detection counter 34 only adds the abnormality detection signal. However, if the normal state continues, the count value may be decremented. Good. As a result, a rarely occurring abnormality can be canceled. In order to realize such a circuit, the abnormality detection counter 34 is constituted by an up / down counter, and is in a normal state (a state in which an abnormality detection signal is not output at the time of reset: the output of the OR circuit 29 is inverted. ) Is provided, and a carry signal of the normal number counter may be input to a countdown terminal of the up / down counter. The count number of the normal number counter is set to an appropriate number of one or more. Further, when the abnormality detection signal is output, the normal number counter may be reset.

[0036]

As described above, according to the present invention, the PWM
The case where the all-off period of the waveform signal is shorter or longer than the allowable range can be detected in the microcomputer, and it is possible to take measures before the system is adversely affected.

[Brief description of the drawings]

FIG. 1 is a block diagram of a compressor control device according to an embodiment of the present invention.

FIG. 2 is a diagram showing an example of a PWM waveform signal of the compressor control device.

FIG. 3 is a block diagram of a microcomputer of the compressor control device.

FIG. 4 is a block diagram of an abnormality detection circuit of the microcomputer.

FIG. 5 is a timing chart of signals of various parts of the abnormality detection circuit.

FIG. 6 is a timing chart of signals of various parts of the abnormality detection circuit.

FIG. 7 is a timing chart of signals of various parts of the abnormality detection circuit.

[Explanation of symbols]

 1-microcomputer 3-power supply 4-transistor 5-three-phase AC motor 5a, 5b, 5c-winding 15-abnormality detection circuit

Claims (2)

(57) [Claims] 1. A microcomputer which turns on / off first and second switch means for selectively connecting a load terminal to a positive electrode or a negative electrode of a power supply with a PWM waveform signal, and outputs the signal to one of the switch means. A microcomputer which switches a PWM waveform signal from an off signal to an on signal after switching a PWM waveform signal from an on signal to an off signal and then waiting for a predetermined all-off period to elapse, and further comprising: Allowable time setting means for setting an allowable minimum time and an allowable maximum time of a period; and PWM output to the first and second switch means
An all-off period monitoring unit that receives a waveform signal and monitors whether an all-off period in which both of them are off signals is within a normal range between the allowable minimum time and the allowable maximum time, and the all-off period An abnormal signal output unit that counts up the number of times that the monitoring unit detects that the all-off period is not in the normal range and generates and outputs an abnormal signal when the count value reaches a predetermined value; Microcomputer for waveform control. 2. The abnormal signal output means includes means for counting down the count value when the all-off period monitoring means detects a predetermined number of times that an all-off period is within the normal range. A microcomputer for PWM waveform control.