JP2994359B1 - Integrated circuit layout design support apparatus and layout design support method - Google Patents

Abstract

An object of the present invention is to perform a floor plan in consideration of a wiring area in a floor plan of an integrated circuit regardless of the shape of a block to be arranged and without increasing the design period of the floor plan. SOLUTION: A block arrangement processing unit 21 arranges blocks according to an instruction of an input device 1 via a GUI, and then a wiring graph creation unit 22 performs processing on the blocks arranged by the block arrangement processing unit 21. Create a wiring graph. When the arranged block is the second or subsequent block, the shortest route calculation unit 23 calculates the shortest route of all the wires connected to the block. Then, the mapping unit 24 converts the wiring graph created by the wiring graph
The shortest wiring route calculated by the wiring route calculation unit 23 is mapped. The wiring area calculation unit 25 estimates the wiring area based on the result of the mapping unit 24 on the wiring graph of the wiring path, and displays the wiring area on the output device 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a layout design support apparatus and a layout design support method for an integrated circuit in a floor plan which is an initial step of designing an integrated circuit.

[0002]

2. Description of the Related Art An integrated circuit is manufactured after a logical design, a net list creation, a floor plan, a detailed layout design, a wiring design, and an artwork process. In this work procedure, the floor plan is to determine a rough chip layout of an integrated circuit by using a block as an arrangement unit in an interactive manner with a computer. An example of a conventional layout design support technology of this kind for an integrated circuit is disclosed in Japanese Unexamined Patent Publication No.
No. 06478 describes this as a “man-machine interactive system”. FIG. 21 is a configuration diagram created based on the description of the gazette. This man-machine interactive system uses an input device 101 such as a keyboard, a data processing device 102 such as a computer that operates under program control, and a display device and the like. And a data processing device 102. The data processing device 102 further includes a temporary block placement processing unit 121, an intra-block congestion degree display unit 122, an inter-block coupling degree display unit 123, a block replacement processing unit 124, and a wiring path change processing unit. 125.

[0003] The block temporary arrangement processing unit 121 is provided with an input device 1
Blocks are arranged in accordance with the instruction by 01. The intra-block congestion degree display unit 122 receives the result of the temporary arrangement by the block temporary arrangement processing unit 121, estimates the wiring congestion degree in the block, and displays it on the output device 103. Similarly, the inter-block coupling degree display unit 123 also receives the result of the temporary placement by the block temporary placement processing unit 121 as an input,
The coupling degree between blocks is displayed on the output device 103. The block replacement processing unit 124 performs a block replacement process on the result of the temporary placement by the block temporary placement processing unit 121 according to an instruction from the input device 101, and displays the result of the replacement on the output device 103. Wiring path change processing unit 12
5 performs a wiring path change process on the result of the temporary placement by the block temporary placement processing unit 121 in accordance with an instruction from the input device 101, and outputs the result of the change to the output device 103.
To be displayed. Next, based on these configurations, the operation of this example will be specifically described.

FIG. 22 is an operation flow of the layout design support apparatus described above. First, a designer of an integrated circuit (hereinafter, a designer) selects an arrangement block arbitrarily using the input device 101 (step S11 in FIG. 22). Next, the designer determines the temporary arrangement position of the block based on the connection strength information provided by the GUI by the floor plan design tool (S12). Then, the data processing device 102 operates, and first, the block provisional placement processing unit 121 determines the placement position (S13), and when all the blocks to be placed have been placed, the block placement on the floor plan ends once ( S14).

Next, the intra-block congestion degree display unit 122
If the designer instructs from the input device 101, the internal wiring congestion degree for each block is calculated based on the block arrangement result, and the congestion degree of the result is expressed in three shades of color and output. It is displayed on the device 103 (S15). FIG. 23 illustrates this state. FIG. 23 shows that as the color becomes darker, the congestion degree of the wiring in the block becomes higher.

Next, the inter-block coupling degree display section 123
If there is an instruction from the input device 101 by the designer, the degree of interconnection between the arranged blocks is calculated based on the result of the block arrangement, and the degree of connection of the result is calculated based on the width of the line.
(S16). FIG. 24 shows this state. In FIG. 24, as the line width increases,
This indicates that the degree of connection between the blocks is high.

[0007] Upon receiving the display of the intra-block congestion degree and the inter-block coupling degree described above, the designer instructs replacement of a block with a high congestion degree and a block with a low congestion degree based on the result. Upon receiving this instruction, the block replacement processing unit 124 performs a block replacement process, then recalculates the congestion degree, and redisplays the result on the output device 103 (S17). FIG. 25 shows a state after the replacement of the block. In the case of this example, since the wiring congestion degree is high and the connection strength is low, the blocks C and E which are considered to be relatively likely to have no wiring are replaced. The connection strength is the number of blocks connecting the blocks. Next, the designer instructs the wiring path of the inter-block connection wiring in a form close to the actual wiring image while observing the connection strength and the wiring congestion degree in FIG. In response to this instruction, the wiring path change processing unit 125 outputs the specified wiring path to the output device 1.
03 is displayed (S18). FIG. 26 shows this state.

At this time, the designer can instruct the division of the wiring. For example, the wiring (a) shown in FIG.
Is the most congested wiring through blocks A, D, C, F and I, but in FIG.
The wiring is divided into a wiring passing through F and I (b) and a wiring passing through A, B, E, F and I (c). The wiring path change processing unit 125 displays the state of the instructed divided wiring on the output device 103 as shown in FIG. 27 (S19). Finally, if instructed by the designer, the data processing device 102 calculates the overall congestion of each block based on the congestion of the intra-block wiring and the congestion of the inter-block wiring, and is shown in FIG. As described above, the congestion degree of the result is expressed by three levels of shades of color and displayed on the output device 103. FIG. 28 is different from FIG.
It can be seen that the congestion degree of the wiring is averaged.

[0009] By the above-described series of operations, the occurrence of unwiring in the wiring design process of integrated circuit design can be suppressed, thereby shortening the design period of the integrated circuit and improving the efficiency of the integrated circuit. The effect that the development can be promoted can be obtained.

[0010]

However, a first problem of the above-mentioned prior art is that it is not easy to average the overall congestion degree of each block. The reason for this is that, since the shape of each block usually varies in size and shape, it is not always possible to replace blocks depending on the degree of congestion. Also,
When there is a complicated block shape or when there are a large number of blocks, it is very difficult for the designer to determine whether to replace blocks, and it becomes difficult to converge the floor plan. The second problem is that all floor plan information at the time of provisional arrangement is wasted. The reason is,
Once all the blocks have been placed, the changed contents of the floor plan information at the time of the temporary placement are applied to the entire chip to replace blocks, specify wiring routes, and divide wiring. This is because, when non-arrangement due to a shortage of the wiring area is detected, the designer must return to the floor plan phase and perform the design from the floor plan to the wiring again. This also leads to an increase in the design time required for the floor plan. Therefore, an object of the present invention is to estimate a wiring area every time one block is arranged at the time of floor planning, display the wiring area in a GUI, and suppress the occurrence of unwired or dead space detected at the time of wiring. In addition, an object of the present invention is to provide an integrated circuit layout design support apparatus and a layout design support method that improve the efficiency of integrated circuit design.

[0011]

[Means for Solving the Problems] The present inventionCollection ofIntegrated circuit ray
Out-design support device is an initial process of integrated circuit design
Layout design support equipment for integrated circuits in floor plans
Input means having various instruction functions;
Block to place blocks according to the instruction by force means
Block arrangement processing means and only the arranged blocks
To create a rectangular wiring graph that surrounds the
Rough creation means and the placed block is the second or later
If it is the one connected to the block,
Shortest path calculation means for calculating the shortest path of all wirings
And the calculated shortest path in the created wiring graph.
RoadWiringMapping, Mapped wiringNumber of
Mapping means for counting
Based on the processing results of the
A wiring area calculating means for estimating a required wiring area;
Displays the stacked wiring area, and displays a GUI together with the input means.
And output means for achieving the following. further,
Preferred of the integrated circuit layout design support apparatus of the present invention
In the embodiment, the shortest path search algorithm is
At the time of wiring design through detailed placement design after lower plan
It is characterized by being close to that used for wiring programs
You. Further, a layout design support device for an integrated circuit according to the present invention is provided.
In a preferred embodiment, the position is indicated by the input means.
For specifying the specified specific wiring route on the GUI.
Line mapping means, and the mapping means includes
Perform mapping to the wiring graph for the line path,
Also, at the time of the mapping, a specific wiring that takes a large wiring area is used.
For line routes,LineGreat for counting
It is characterized by weighting. Further, the collection of the present invention
Preferred Embodiment of Integrated Circuit Layout Design Support Apparatus
Means that the mapping means is the calculated wiring route
Search for the nearest branch of the wiring graph, and
Data represented by points, branches and intersections of the wiring graph
By performing the mapping by storing
Features. Also, the layout design of the integrated circuit of the present invention
The support method is a floor plug which is an initial process of integrated circuit design.
Of layout design support for integrated circuits
And selecting a wiring target block.
Procedure for arranging blocks and only the arranged blocks
Create a rectangular wiring graph that encloses to include
Procedure and the placed block is the second or later
In some cases, all distributions connected to the block
A procedure for calculating the shortest path of the wire;
Roughly calculated shortest routeWiringMapping,
Mapped wiringCounting the number of
Based on the processing result by the mapping means,
Steps to estimate the wiring area required for lock wiring,
Displaying the estimated wiring area.
Features.

[Operation] In the present invention, the wiring graph creating unit creates a wiring graph for the tentatively arranged blocks. The wiring shortest path calculation unit calculates the shortest path of the wiring connected to the tentatively arranged block, maps the wiring path calculated by the mapping unit onto the wiring graph of the next wiring path to the wiring graph, and performs wiring. Count the number of lines. Finally, the wiring area calculation unit calculates a wiring area required for wiring from the number of wirings mapped on the wiring graph, and displays the result on a GUI of a computer. By this function, the integrated circuit designer can obtain a guideline on how much wiring area is required at the time of block placement and how much it needs to be placed with a gap from the placed block. is there.

[0013]

Embodiments of the present invention will now be described in detail with reference to the drawings. Referring to FIG. 1, an integrated circuit layout design support apparatus according to the present invention includes an input device 1 such as a keyboard, a data processing device 2 such as a computer that operates under program control, and an output device 3 such as a display device. . Further, the data processing device 2 includes a block placement processing unit 21 and a wiring graph creation unit 2
2, the shortest route calculation unit 23, and the mapping unit 24
And a wiring area calculation unit 25.

The block arrangement processing section 21 temporarily arranges blocks according to an instruction from the input device 1. The wiring graph creating unit 22 creates a wiring graph for the blocks arranged by the block arrangement processing unit 21, and the wiring shortest path calculating unit 23 connects to the block when the arranged block is the second or later. Calculate the shortest paths of all the wirings. The mapping unit 24 maps the shortest wiring route calculated by the wiring shortest route calculating unit 23 onto the wiring graph created by the wiring graph creating unit 22, and counts the number of each wiring graph. Wiring area calculator 25
Estimates the wiring area based on the result of processing by the mapping unit 24 on the wiring graph of the wiring path, and displays the result on the output device 3.

Next, the operation of the layout design support apparatus will be described with reference to the flowchart of FIG. 2 and the state diagrams of FIGS. First, the designer gives an instruction from the input device 1 in FIG. 1 and arbitrarily selects a block to be arranged (S1 in FIG. 2). Next, as shown in FIG. 3, the designer determines a temporary arrangement position of the block based on information on connection strength provided by the GUI by the floor plan design tool (S2). The processing so far is performed by the block arrangement processing unit 21 in FIG.

Next, as shown in FIG. 4, the wiring graph creating unit 22 shown in FIG. 4 only places the tentatively arranged blocks so that the surroundings are surrounded by four sides so that other blocks are not included. Is created (S3). Wiring graphs include intersections, points equally spaced between intersections, and
It consists of points and branches between the points. The interval between points is arbitrary. After the wiring graph is created, if the temporarily arranged block is the first block (S4), the designer gives an instruction from the input device 1 and the GUI of the floor plan design tool.
As shown in FIG. 5, an arrangement position of a block to be arranged is determined (S5), and the process returns to S1 to return to FIG.
As shown in FIG. 7, the process proceeds from the temporary arrangement of the second block. If the tentatively arranged block is the second or subsequent block (S4), the shortest path calculation unit 23 calculates the shortest paths for all the wirings connected to the block arranged at that time, as shown in FIG. (S6). Although the algorithm for searching for the shortest path is not specified, a simple algorithm close to the algorithm used for the wiring program in the layout design is used. The reason is that there is no large difference between the estimation of the wiring area in the floor plan and the wiring result in the layout design.

Next, as shown in FIG. 9, the wiring path calculated in S6 of FIG. 2 is assigned to intersections, points, and branches of the wiring graph by the mapping unit 24 (S6).
7). At this time, the mapping unit 24 searches for the nearest branch of the wiring graph from the wiring path, and performs mapping by storing the wiring path as data representing points, branches, and intersections of the wiring graph. I do. For example,
In the case of the wiring A in FIG. 9, the wiring path connecting the placement target block (a) and the existing placement target block (b) is assigned to a branch passing through the points a4, B, C, D, and d3 of the wiring graph. Can be At this time, in the data structure 1 storing the information of the wiring graph shown in FIG. 10A, the number of wirings is added to each branch assigned as a wiring path. At the same time as the assignment, the wiring path is also stored in the data structure 2 of FIG. 10B that stores the wiring path. In the case of FIG. 9, the path information of the terminal X of the wiring target block (a), the intersections B, C, and D of the wiring graph and the terminal Z of the already arranged block (b) are stored.

Next, the wiring area calculating unit 25 calculates a wiring width proportional to the number of wiring graphs assigned to the wiring graph, and outputs the wiring area to the output device 3 via the GUI of the floor plan design tool. It is displayed (S8). In the calculation of the wiring width, the value of the wiring width per one wiring is arbitrary. As shown in FIG. 11, the wiring area is displayed on the output device 3 as a wiring width required in the wiring area estimation from the side of the already arranged block adjacent to the arrangement target block. The designer can use the floor plan tool GUI
The placement position is determined (S9). At this time, the designer can determine the placement position while looking at the estimation result of the wiring area.
The above-described steps S1 to S9 are repeated until the designer finishes placing all the blocks (S10).

Here, a practical example will be described in more detail. FIG. 12 has already been processed through S1 to S8 in FIG.
It is a figure of a state where two blocks are arranged. In this case, as shown in FIG. 13, the data structure 1 stores the wiring graph calculated by the mapping unit 24 and the number of wirings allocated to each technique as data. FIG. 13 is a schematic diagram of the data structure 1 and the data structure 2. The data structure 2 includes wiring paths X, F, I, H, Z
I remember. Here, as shown in FIG. 14 by S1 and S2 in FIG. 2, it is assumed that macroblocks are temporarily arranged so as to straddle between the wiring graphs EF. In this case, S
As shown in FIG. 15 in FIG. 3, a new wiring graph between JK is newly created as a wiring graph of the third block. The wiring graph between the EFs disappears, and the intersection F disappears. At this time, the information of the intersection F stored in the data structure 1 is lost, and the information is also stored in the data structure 2 as passing through the intersection F.
Once part F is removed from the path. Then, for the smallest rectangle including the newly created wiring graph JK, in this example, the wiring included in the rectangle surrounded by the intersections B, H, I, and C, the search for the shortest wiring route is performed again. Okay, we will map a new wiring graph.
In the case of this example, a search is made for the shortest route from X to H as shown in FIG. As a result, mapping of the shortest route as shown in FIG. 17 is performed.
At this time, as shown in FIG. 17, both data structures 1 and 2 are rewritten to reflect this result. After this, 3
With respect to the second macroblock, the processing from S6 to S9 in FIG. 2 is performed by the method described above.

Next, a second embodiment of the present invention will be described. FIG. 18 shows the configuration of the second embodiment, in which an input device 1, a data processing device 20 and an output device 3
It consists of. Further, the data processing device 20 includes a wiring route designation processing unit 26, a mapping unit 27, and a wiring area calculation unit 28. The wiring path designation processing unit 26 performs power supply wiring and the like in accordance with the instruction of the designer designated from the input device 1,
The designation of the wiring path of the critical path is realized on the GUI. The mapping unit 27 maps the wiring route specified by the wiring route specification processing unit 26 to the wiring graph in the same manner as in the first embodiment described above. Next, the wiring area calculation unit 28, as in the first embodiment,
The wiring area is calculated, and the result is displayed on the GUI of the output device 3.

FIG. 19 shows a specific example of this, and shows a state in which a wiring path (i) is specified by a designer in the wiring path specifying processing section 26. Next, the wiring path mapping unit 27
Maps the wiring route to the wiring graph as shown in FIG. In this case, with respect to a wiring area such as a power supply wiring which takes a large wiring area, the value of the weight for the branch is made larger than that of the normal wiring. As described above, the first aspect of the present invention
According to the present embodiment, when arranging blocks in a floor plan, and according to the second embodiment of the present invention, an estimation of a wiring area can be realized based on designation of a wiring path by a designer.

[0022]

A first effect of the present invention is that a designer can perform a floor plan in consideration of wiring by displaying the estimation result of the wiring area successively at the time of block arrangement. The reason is that at the time of block arrangement, a wiring graph is created, a wiring path is searched, and the result is mapped to a wiring graph, thereby providing a function of estimating a wiring area and displaying the estimated area on a GUI. The second effect is that the wiring area is taken into account during floor planning,
An object of the present invention is to prevent occurrence of unwiring or dead space in a wiring process in a layout, which is a subsequent process.
The reason for this is that, by performing block layout in consideration of a wiring area expected to be required for actual wiring during floor planning, it is possible to prevent an extremely shortage or excessive wiring area of the wiring area.

A program for causing the data processing device 2 or the data processing device 20 to execute the integrated circuit layout design support method described above is stored on a magnetic disk.
The data may be recorded on a computer-readable recording medium such as a semiconductor memory, read by the data processing device 2 or the like, and executed. Such a layout design support method for an integrated circuit is a layout design support method for an integrated circuit in a floor plan which is an initial step of an integrated circuit design, and a procedure for arranging a selected placement target block,
A request for creating a rectangular wiring graph surrounding the periphery so as to include only the arranged block, and when the arranged block is a second or subsequent one, all of the connected blocks are connected. Calculating the shortest path of the wiring , mapping the calculated wiring of the shortest path to the created wiring graph, counting the number of mapped wirings , and processing results based on the mapping unit. The method includes a procedure for estimating a wiring area required for wiring of the arranged block, and a procedure for displaying the estimated wiring area.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of an integrated circuit layout design support apparatus according to the present invention;

FIG. 2 is a flowchart of the first embodiment shown in FIG.

3 is a state diagram of a layout design in a floor plan of the integrated circuit according to the flowchart of FIG. 2;

FIG. 4 is a state diagram of a layout design in a floor plan of the integrated circuit according to the flowchart of FIG. 2;

FIG. 5 is a state diagram of a layout design in a floor plan of the integrated circuit according to the flowchart of FIG. 2;

FIG. 6 is a state diagram of a layout design in a floor plan of the integrated circuit according to the flowchart of FIG. 2;

FIG. 7 is a state diagram of a layout design in a floor plan of the integrated circuit according to the flowchart of FIG. 2;

8 is a state diagram of a layout design in a floor plan of the integrated circuit according to the flowchart of FIG. 2;

9 is a state diagram of a layout design in a floor plan of the integrated circuit according to the flowchart of FIG. 2;

FIG. 10 is a state diagram of a layout design in a floor plan of the integrated circuit according to the flowchart of FIG. 2;

11 is a state diagram of a layout design in a floor plan of the integrated circuit according to the flowchart of FIG. 2;

FIG. 12 is a state diagram of a layout design in a floor plan of the integrated circuit according to the flowchart of FIG. 2;

FIG. 13 is a state diagram of a layout design in a floor plan of the integrated circuit according to the flowchart of FIG. 2;

14 is a state diagram of a layout design in a floor plan of the integrated circuit according to the flowchart of FIG. 2;

FIG. 15 is a state diagram of a layout design in a floor plan of the integrated circuit according to the flowchart of FIG. 2;

FIG. 16 is a state diagram of a layout design in a floor plan of the integrated circuit according to the flowchart of FIG. 2;

17 is a state diagram of a layout design in a floor plan of the integrated circuit according to the flowchart of FIG. 2;

FIG. 18 is a flowchart showing a second embodiment of an integrated circuit layout design support apparatus according to the present invention;

19 according to the second embodiment shown in FIG.
State diagram of layout design in floor plan of integrated circuit

20 according to the second embodiment shown in FIG.
State diagram of layout design in floor plan of integrated circuit

FIG. 21 is a block diagram showing an example of a conventional technique.

FIG. 22 is a flowchart of the conventional example shown in FIG. 21;

23 is a state diagram of a layout design in a floor plan of an integrated circuit according to the conventional example shown in FIG. 21;

24 is a state diagram of a layout design in a floor plan of an integrated circuit according to the conventional example shown in FIG. 21;

25 is a state diagram of a layout design in a floor plan of an integrated circuit according to the conventional example shown in FIG. 21;

26 is a state diagram of a layout design in a floor plan of an integrated circuit according to the conventional example shown in FIG. 21;

FIG. 27 is a state diagram of a layout design in a floor plan of an integrated circuit according to the conventional example shown in FIG. 21;

FIG. 28 is a state diagram of a layout design in a floor plan of an integrated circuit according to the conventional example shown in FIG. 21;

[Explanation of symbols]

 1, 101 Input device 2, 20, 102 Data processing device 3, 103 Output device 21 Block arrangement processing unit 22 Wiring graph creation unit 23 Wiring shortest route calculation unit 24, 27 Mapping unit 25, 28 Wiring region calculation unit 26 Wiring route designation Processing unit 121 Block provisional placement processing unit 122 Intra-block congestion degree display unit 123 Inter-block connectivity display unit 124 Block replacement processing unit 125 Wiring path change processing unit

Continuation of the front page (56) References JP-A-3-80555 (JP, A) JP-A-9-120993 (JP, A) JP-A 1-238035 (JP, A) JP-A-5-35822 (JP) JP-A-6-283603 (JP, A) JP-A-10-91673 (JP, A) JP-A-10-269258 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB Name) G06F 17/50 H01L 21/82

Claims (7)

(57) [Claims] 1. An integrated circuit layout design support apparatus for a floor plan, which is an initial step of integrated circuit design, comprising: input means having various instruction functions; and block arrangement processing means for arranging blocks in accordance with instructions from the input means. And a wiring graph creating means for creating a rectangular wiring graph enclosing the periphery so as to include only the arranged block, and when the arranged block is a second or subsequent one, is connected to the block. Wiring shortest path calculating means for calculating the shortest path of all the wirings, mapping means for mapping the calculated shortest path wiring to the created wiring graph, and counting the number of mapped wirings , Estimating a wiring area required for wiring of the arranged block based on a processing result by the mapping means. A wiring area calculation means, and displaying said estimated the wiring area, the layout design supporting apparatus for an integrated circuit that wherein there that an output means for forming a graphic user interface with the input means. Search algorithm as claimed in claim 2, wherein the shortest path, the layout design support of an integrated circuit according to claim 1, characterized in that close to those used in the routing program at the time of wiring design through the detailed layout design after floorplan apparatus. 3. A wiring route designating means for realizing designation of a specific wiring route designated by said input means on said graphic user interface, wherein said mapping means maps said specific wiring route to said wiring graph. 3. The integrated circuit layout design support device according to claim 1, wherein 4. A time the mapping, for a specific wiring path have a large wiring area, the layout design supporting apparatus for an integrated circuit according to claim 3, characterized in that the weighting large count of the number of the wiring. 5. The mapping means searches for the nearest branch of the wiring graph from the calculated wiring path, and stores the wiring path as data represented by points, branches, and intersections of the wiring graph. the layout design support apparatus for an integrated circuit according to any one of claims 1 to 4, characterized in that performing the mapping by. 6. A method for supporting layout of an integrated circuit in a floor plan, which is an initial step of designing an integrated circuit, includes a step of selecting a block to be arranged, a step of arranging the selected block, and a step of arranging the arranged block. A step of creating a rectangular wiring graph enclosing the periphery of the block, and calculating the shortest path of all wirings connected to the block when the arranged block is the second or subsequent one a step of, mapping the wiring of the calculated shortest path to the created wiring graph, map
To display the procedure for counting the number of pings and the wiring, a means for estimating a wiring space required for wiring blocks the arrangement based on the processing result by said mapping means, the estimated the wiring area And a layout design support method for an integrated circuit. 7. A layout design support method for an integrated circuit in a floor plan, which is an initial step of integrated circuit design, comprising: a step of arranging a selected placement target block; Creating a rectangular wiring graph enclosing the above, and, when the arranged block is the second or subsequent one, calculating the shortest paths of all the wirings connected to the block; distribution of the calculated shortest path is a wiring chart
A step of mapping lines and counting the number of mapped wirings ; a step of estimating a wiring area required for wiring of the arranged block based on a processing result by the mapping means; A computer-readable recording medium on which a program for causing a data processing apparatus to execute a method having a procedure of displaying an area is recorded.