JP2994307B2 - Variable period signal generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable period signal generating circuit, and more particularly to a variable period signal generating circuit for easily generating a synchronization signal required for an image display unit.

[0002]

2. Description of the Related Art In the prior art, various necessity of conversion of a synchronizing signal required in a multi-sync display monitor is described, but it does not extend to the internal configuration method. Usually, the conversion of the synchronization signal includes P
An LL circuit is used. The value of the counter is monitored by the frequency dividing circuit, and a signal of a required cycle is obtained from the timing. In this case, the necessary function is obtained by decoding the count value. Generally, when this decoder is realized on hardware, the gate I
C and a comparator IC are used.

When it is necessary to change not only the period of a signal to be output but also the duty of an input signal, a decoder for this is also required. Normally, in order to obtain a certain timing from the count value, decoders are required as many as the required timing.

[0004]

However, if all the count values are obtained by the decoder as described above, the hardware becomes heavier, especially as the specifications required for the decoder become closer to full decoding. For example, FIG.
When such a signal is required, the circuit block configuration usually includes a basic clock generator 5 as shown in FIG.
1, a counter 52, a decoder A, a decoder B, a decoder C, and a timing adjustment unit 53, and three decoders are required. As described above, in order to be able to generate signals of various periods, a number of decoders corresponding to those periods are required, and the same applies when the duty is changed.

An object of the present invention is to simply configure a decoding circuit block for generating a variable period signal. As a result, the circuit scale can be reduced, and the duty can be changed in addition to the period. An object of the present invention is to provide a variable period signal generator configured as described above.

[0006]

A variable period signal generating circuit according to the present invention comprises a basic clock generating section, a counter for counting clocks input from the basic clock generating section, and a load input setting section for setting a full count of the counter. Wherein the cycle of the output signal of the counter required by the load input setting section is determined.

With the above configuration, the full count output (carry) of the counter can be changed only by setting the load input value to the counter by the load input setting section, and signals of various cycles can be output. Can be done. That is, the period of the signal to be generated is
From the load input of the counter to the full count output of the counter.

A preferred variable period signal generating circuit according to the present invention further comprises: a comparison value setting section for setting a decode value; and inputting the counter output and comparing the value with the decode value set by the comparison value setting section. Or a comparison detection unit that outputs H, and the duty of the output signal required by the comparison value setting unit is determined.

With the above configuration, the duty of the signal to be generated is determined by comparing the load input of the counter with the decode value determined by the external setting by the comparison value setting unit. Therefore, it is possible to generate signals of various duties by operating the set value of the comparison value setting unit.

[0010]

Next, an embodiment of the present invention will be described with reference to FIG. The variable period signal generating circuit according to the present embodiment includes a basic clock generating unit 6 for generating a basic clock, a load input setting unit 1 for setting a load value forming a first decode value, and a load input setting unit for counting the basic clocks. A counter 2 for counting up to the value set in 1, a comparison value setting unit 3 for setting a second decode value for determining the duty, a comparison detection unit 4 for comparing the output of the counter 2 with the second decode value, It comprises a timing adjustment unit 5 controlled by the output of the comparison detection unit and the carry generated when the counter 2 is fully counted. The basic clock generator 6 may be provided externally.

As shown in FIG. 1B, the first decoded values A to B are the periods of the output signal of the variable period generating circuit of the present embodiment, and the second decoded values A to C are duty cycles. Is determined. In this case, the duty ranges from C to B. The comparison detection unit 4 compares the value set by the comparison value setting unit 3 with the count value output from the counter 2 and outputs L / H. This defines point C. Then, the cycle and timing of the output signal are determined by the timing adjustment unit 5 that receives the carry output of the counter 2 and the output of the comparison detection unit 4. As described above, the cycle and duty of the output signal can be freely changed based on the values set by the load input setting unit 1 and the comparison value setting unit 3, respectively.

Next, an actual circuit is shown in FIG. In the figure, reference numeral 21 denotes a load input setting unit (SW), which is composed of two 4-bit switches on the LSB (lower bit) side and the MSB (higher bit) side. 22 and 23 are L respectively
The counters on the SB and MSB sides count the basic clock output from the oscillator 27 forming the basic clock generating unit, and count up to the count value set by the load input setting unit 2. Reference numeral 24 denotes a comparison value setting unit (SW) for setting a count value, and a comparison detection unit (comparator) 25
The set value set by the comparison value setting unit 24 and the count value output from the counter 22 are compared.

An output timing adjustment unit 26 is an inverter 261 for receiving the output of the comparator, and an OR gate 26 having one input connected to the output of the inverter 261.
2. The output of the OR gate is input to the D input, the basic clock is input to the clock input (C input), the first D flip-flop 263, the carry output of the counter 23 on the MSB side is input to the D input via the inverter 231. And a second D flip-flop 264 in which the basic clock is input to the C input. The set input (XS input) and reset input (XR input) of the second D flip-flop
) Are invalid, the XS input of the first flip-flop 263 is invalid, and the XR input is connected to the Q output of the second flip-flop 264. The Q output of the first flip-flop 263 constitutes the output of the variable period generating circuit, and this output is input to the other of the OR gate 262.

The load input setting section 21 sets a load value constituting the first decode value. The 8-bit terminal is normally pulled up to 1 and becomes 0 when the switch is turned on. For example, when all are set to 0, the full count of the counter becomes 256. That is, a signal of one cycle is generated with a basic clock of 256. The set load value is loaded at the carry output timing of the MSB side counter by counting up the required division level (output signal cycle). As described above, the biggest feature of this circuit is that the decoding of the counter value necessary for controlling the cycle and duty of the output signal is performed by the counter IC 2.
This is realized by using 2, 23 load inputs and full count outputs.

Next, the 8-bit SW 24 and the comparator 25 on the right side of the drawing compare the count-up values of the counters 22 and 23. When the set value of the 8-bit SW 24 and the condition of the counter value match, the required pulse "
L ”width is determined, and then the MSB side of the counter 23
The width of the "H" portion is continued until the carry output timing.

That is, from time A to time C in FIG. 1B, the count value of the counter 2 is lower than the value set in the comparison setting unit 24, the output of the comparator 25 is 1, and the first D The output of the flip-flop 263 is 0. At time C, when the output of comparator 25 goes to zero, the first D flip-flop goes to one,
First D flip-flop 263 and OR gate 262
Is self-holding. The time point B in FIG.
When the carry output CA of the counter 23 on the side becomes 1, the second
Output of the flip-flop 264 becomes 0, and the first flip-flop 263 is reset. by this,
The output of the variable period signal generation circuit returns to 0. The carry output CA of the MSB side counter 23 is returned to the L input of the LSB side counter, and the counter returns to 0 again and starts counting again. The above operation is repeated, and FIG.
Is obtained.

Referring to FIG. 3, an application example of the variable period generating circuit of the present invention will be described. Now, as shown in FIG.
It is assumed that a controller for an image to be displayed on a 5.5-inch (320 × 240 dots) LCD is being developed. In this case, the standard of the synchronization signal is both NTSC, but as shown in FIG. Inches (640 x 480 dots)
In order to display an equivalent image on an LCD, the pixels of the front porch, the back porch and the like must be adjusted to the standard. That is, the controller cannot be manufactured unless the duty of the synchronization signal is made variable. The function of the variable period generating circuit of the present invention can be realized by the simple circuit configuration as described above. In this case, even when both synchronization signals are different, it is possible to cope with the same circuit.

In the above example, 5.5 inch LC
The horizontal signal standard for D and the horizontal signal standard for 9.4-inch LCD are shown in FIG.
The result is as shown in FIG. As shown in this figure, since both have the same cycle in this example, it is necessary to prepare synchronization signals having different duties. In order to generate this synchronization signal according to the present invention, it is possible to set a counter load value and a comparator set value.

FIG. 4 is a block diagram of a PLL circuit in which the variable period generating circuit of the present invention is suitably employed. In the figure, a phase comparison unit 31, a filter 32, a voltage controlled oscillator (VCO) 33, and a frequency dividing circuit 34 are connected in a loop. The frequency dividing circuit employs the variable period generating circuit of the present invention. Here, when a synchronization signal of a certain horizontal cycle is input and such a PLL circuit is used, a synchronization signal of a different cycle can be obtained, and the frequency dividing circuit 34 can add a variable duty. In this case, not only the cycle but also the duty can be changed in the conversion of the synchronization signal, and the application range of the PLL circuit is expanded.

[0020]

As described above, according to the variable period signal generating circuit of the present invention, the signal period and the signal period can be further reduced by merely inputting the full count value of the counter and the comparison value with the count value as the set value. Can set the duty,
A remarkable effect is obtained in that the configuration of the decoder for decoding the output of the counter, which has been conventionally required, is simplified.

[Brief description of the drawings]

FIG. 1A is a block diagram showing an embodiment of a variable period signal generator according to the present invention, and FIG. 1B is a waveform diagram of an output signal shown together with a decode point.

FIG. 2 is a circuit diagram further embodying the block diagram shown in FIG.

3A and 3B are configuration block diagrams of a liquid crystal display device, and FIG. 3C is a waveform diagram illustrating a difference in duty.

FIG. 4 is a block diagram showing an application example of the present invention.

FIG. 5 is an explanatory diagram of a conventional technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Load input setting part 2 Counter 3 Comparison value setting part 4 Comparison detection part 5 Timing adjustment part 6 Basic clock generation part

Claims (1)

(57) [Claims] A counter for counting a basic clock; a load input setting unit for setting a full count of the counter; a comparison value setting unit for setting a decode value smaller than a previous full count; A comparison detection unit that compares the decoded value set by the value setting unit and outputs L or H; a timing adjustment unit whose output is controlled by a full count output of the counter and an output of the comparison value setting unit; A variable period signal generation circuit, wherein the output of the timing adjustment unit is a period signal whose period and duty ratio are determined based on the setting of the full count and the decode value.