JP2993028B2 - High voltage MIS transistor - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high breakdown voltage MIS transistor suitable for use in, for example, a semiconductor integrated circuit.

[Summary of the Invention]

The high-breakdown-voltage MIS transistor of the present invention has a plurality of wiring contact portions in a drain region surrounded by an inter-element isolation insulating film, and the plurality of wiring contact portions are each surrounded by an in-element isolation insulating film. In the region, a portion below the element isolation insulating film and the element isolation insulating film and around the wiring contact portion has a low impurity concentration. The lower portion of the drain region as well as the portion around the wiring contact portion of the drain region may have a low impurity concentration. According to the present invention, the withstand voltage of a high-breakdown-voltage MIS transistor can be improved.

[Conventional technology]

Conventionally, a LOCOS offset drain type high voltage MOS transistor (hereinafter, referred to as an LOD type high voltage MOS transistor) is known as a high voltage MIS transistor. FIG. 7,
8 and 9 show a conventional LOD type high voltage MOS transistor. Here, FIG. 8 and FIG. 9 respectively correspond to FIG.
It is sectional drawing along the VIII-VIII line and IX-IX line. As shown in FIGS. 7, 8 and 9, in a conventional LOD type high breakdown voltage MOS transistor, for example, a field insulating film 102 is selectively formed on the surface of an n ⁻ type silicon (Si) substrate 101. Thus, isolation between elements and isolation within an element are performed. Reference numeral 103 indicates, for example, an n ⁺ type channel stop region. A gate insulating film 104 is formed on the surface of the active region surrounded by the field insulating film 102. Symbol G 'indicates a gate electrode. In the n ⁻ -type Si substrate 101, a p ⁺ -type source region 105 is formed in self-alignment with the gate electrode G ′. On the other hand, the gate electrode G '
The part opposite to the source region 105 with p ⁺
A mold drain region 106 is formed. In this case, the field insulating film 102 around the p ⁺ type drain region 106
In the lower portion, ap ⁻ -type low impurity concentration portion 106a constituting a part of the drain region 106 is formed. The gate electrode G ', the source region 105, and the drain region 106 having the low impurity concentration portion 106a form a p-channel LOD type high breakdown voltage MOS transistor. In this case, the drain electric field is alleviated by the low impurity concentration portion 106a of the drain region 106. Symbol 107
Indicates an interlayer insulating film, and 108 and 109 indicate aluminum (Al) wirings. Here, the Al wiring 108 contacts the source region 105 through the contact holes C ₁ ′ to C ₅ ′ formed in the interlayer insulating film 107 and the gate insulating film 104, and the Al wiring 109 connects to the interlayer insulating film 107 and the gate insulating film 104. The contact is made with the drain region 106 through the contact holes C ₆ ′ to C ₁₀ ′.

[Problems to be solved by the invention]

7 view of the above, in the conventional LOD-type high voltage MOS transistor shown in FIG. 8 and FIG. 9, when grounding the source region 105, applying a negative drain voltage V _D to the drain region 106, the As shown in FIGS. 8 and 9, a depletion layer 110 is formed. In this case, the junction between the low impurity concentration portion 106a of the drain region 106 and the n ⁻ type Si substrate 101 is a p ⁻ −n ⁻ junction, but the junction between the p ⁺ type drain region 106 and the n ⁻ type Si substrate 101 is p ⁺
−n ^- junction. Therefore, the depletion layer 110 at the junction between the low impurity concentration portion 106a, which is a p ⁻ −n ⁻ junction, and the n ⁻ type Si substrate 101.
Is increased, but the width of the depletion layer 110 at the junction between the p ⁺ -type drain region 106, which is a p ⁺ -n ^- junction, and the n ^-- type Si substrate 101 is reduced. Therefore, the drain electric field is reduced at the junction between the low impurity concentration portion 106a and the n ⁻ -type Si substrate 101, but not at the junction between the p ⁺ -type drain region 106 and the n ⁻ -type Si substrate 101. . This has caused the breakdown voltage of the conventional LOD type high breakdown voltage MOS transistor to deteriorate.

Therefore, an object of the present invention is to provide a high-breakdown-voltage MIS transistor capable of improving the withstand voltage.

[Means for solving the problem]

In order to achieve the above object, a high-breakdown-voltage MIS transistor according to the present invention has a plurality of wiring contact portions in a drain region (6) surrounded by an inter-element isolation insulating film, and The part of the drain region (6), which is below the inter-element isolation insulating film and the inter-element isolation insulating film and around the wiring contact portion, has a low impurity concentration.

Preferably, not only the portion around the wiring contact portion of the drain region (6) but also the lower portion of the drain region (6) may have a low impurity concentration.

[Action]

According to the high-breakdown-voltage MIS transistor of the present invention configured as described above, the portion around the wiring contact portion of the drain region (6) has a low impurity concentration. Part around (6a)
A wide depletion layer (10) is formed at the junction between the semiconductor substrate and the semiconductor substrate. As a result, the depletion layer region formed at the junction between the drain region (6) and the semiconductor substrate (1) is smaller than in the case where only the portion around the drain region (6) has a low impurity concentration. The drain electric field is reduced by that amount. And
This results in a more uniform drain electric field.

As described above, the withstand voltage of the high-breakdown-voltage MIS transistor can be improved.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings of the embodiments, the same portions are denoted by the same reference numerals.

FIG. 1 is a plan view showing an LOD type high breakdown voltage MOS transistor according to one embodiment of the present invention, and FIGS. 2 and 3 are cross-sectional views taken along lines II-II and III-III of FIG. 1, respectively. It is.

As shown in FIGS. 1, 2 and 3, in the LOD type high breakdown voltage MOS transistor according to this embodiment, for example,
A field insulating film 2 such as an SiO ₂ film is selectively formed on a surface of a semiconductor substrate 1 such as an n ^- type Si substrate, thereby performing element isolation and element isolation. Reference numeral 3 indicates, for example, an n ⁺ type channel stop region. Here, the channel stop region 3 is formed so as to surround the entire transistor. On the surface of the active region surrounded by the field insulating film 2, a gate insulating film 4 such as a SiO ₂ film is formed. G indicates a gate electrode.
The gate electrode G is formed of, for example, a polycrystalline Si film doped with an impurity such as phosphorus (P) or a tungsten silicide (WS)
i ₂ ) It can be formed by a polycide film in which a high melting point metal silicide film such as a film is laminated. The gate electrode G is formed over both the gate insulating film 4 and the field insulating film 2 when viewed in the channel length direction of the transistor.

On the other hand, reference numeral 5 indicates, for example, a p ⁺ type source region. The source region 5 is formed in the semiconductor substrate 1 in a self-aligned manner with respect to the gate electrode G. Reference numeral 6 indicates a drain region. Reference numeral 7 denotes an interlayer insulating film such as a phosphor silicate glass (PSG) film, and reference numerals 8 and 9 denote wirings such as aluminum (Al) wiring. Here, the wiring 8 contacts the source region 5 through the contact holes C _{1 to} C ₄ formed in the interlayer insulating film 7 and the gate insulating film 4, and the wiring 9 is formed in the interlayer insulating film 7 and the gate insulating film 4. It is put in contact with the drain region 6 through the contact hole C ₅ -C _8.

In this embodiment, contact holes C _{5 to} C ₈ for contacting the wiring 9 with the drain region 6 are formed on the active region surrounded by the field insulating film 2. The drain region 6 of the contact portion of the wiring 9 is, for example, p ⁺ type. On the other hand, in the drain region 6, a portion around the contact portion of the wiring 9 and a portion below the field insulating film 2 are, for example, p ^- type low impurity concentration portions 6a.

Next, the LOD according to this embodiment configured as described above is used.
A method of manufacturing a high-voltage MOS transistor with high breakdown voltage will be described.

As shown in FIG. 1, FIG. 2, and FIG. 3, first, for example, the surface of the semiconductor substrate 1 is selectively thermally oxidized to form a field insulating film 2 to perform element isolation and element isolation. At the same time, in advance by ion implantation has been each other n-type impurity and p-type impurities diffuse into the semiconductor substrate 1, the channel stop region 3 and p of the lower side of the field insulating film 2, for example n ⁺ -type ^- A low impurity concentration portion 6a of a mold is formed. Next, a gate insulating film 4 is formed on the surface of the active region surrounded by the field insulating film 2 by, for example, a thermal oxidation method. Next, for example, a polycrystalline Si film is formed on the entire surface by the CVD method, and the polycrystalline Si film is doped with an impurity such as P to reduce the resistance, and then the polycrystalline Si film is etched into a predetermined shape. The gate electrode G is formed by patterning. When the gate electrode G is formed of a polycide film, a refractory metal silicide film is formed on a polycrystalline Si film doped with the above-described impurities, and then the refractory metal silicide film and the polycrystalline Si film are formed. Perform patterning. Next, a p-type impurity such as boron (B) is ion-implanted at a high concentration over the entire surface. in this case,
The gate electrode G and the field insulating film 2 function as a mask at the time of the ion implantation, and the source region 5 is formed in self-alignment with the gate electrode G. P ^{+ in} the part opposite to region 5
A mold drain region 6 is formed. Next, after an interlayer insulating film 7 is formed on the entire surface by the CVD method, predetermined portions of the interlayer insulating film 7 and the gate insulating film 4 are removed by etching to form contact holes C _{1 to} C ₈ . Next, after forming an AL film on the entire surface by, for example, a sputtering method, the Al film is patterned into a predetermined shape by etching to form wirings 8 and 9. As a result, the intended LOD type high withstand voltage MOS transistor as shown in FIGS. 1, 2 and 3 is completed.

In the case of a semiconductor integrated circuit in which an n-channel MOS transistor and a p-channel MOS transistor are formed on the semiconductor substrate 1. Low impurity concentration portion 6a of drain region 6 described above
Can be also used as ion implantation of a p-type impurity for forming a channel stop region for an n-channel MOS transistor.

In LOD-type high voltage MOS transistor according to this embodiment, grounding the source region 5, in the case of applying a negative drain voltage V _D to the drain region 6, a depletion layer as illustrated in FIGS. 2 and 3 10 is formed. In this case, the junction between the p ⁺ -type drain region 6 and the n ^-- type semiconductor substrate 1 is a p ⁺ -n ^- junction, and the width of the depletion layer 10 formed at the p ⁺ -n ^- junction is small. . On the other hand, the junction between the p ⁻ type low impurity concentration 6a of the drain region 6 and the n ⁻ type semiconductor substrate 1 is a p ⁻ −n ⁻ junction, and a depletion layer formed at the p ⁻ −n ⁻ junction. The width of 10 is large. In this embodiment, not only the portion around the drain region 6 but also the portion around the p ⁺ -type drain region 6 contacted by the wiring 9 is a p ⁻ -type low impurity concentration portion 6a. of junction between region 6 and the semiconductor substrate 1 p ^- -n ^- the proportion of parts are joined increases.
Accordingly, the depletion layer region at the junction between the drain region 6 and the semiconductor substrate 1 is enlarged as compared with the conventional case. When viewed over the entire drain region 6, the drain electric field is more uniform than in the conventional case. With this, LOD type high voltage MOS
The withstand voltage of the transistor can be improved.

Further, the LOD type high breakdown voltage MOS transistor according to this embodiment can be easily realized only by changing the pattern of the field insulating film of the conventional LOD type high breakdown voltage MOS transistor.

The structure of the LOD type high breakdown voltage MOS transistor according to this embodiment is particularly effective when the channel width is large and the number of contact holes for contacting the wiring 9 with the drain region 6 is large. Further, the LOD type high withstand voltage MOS transistor according to this embodiment is suitable for application to, for example, a semiconductor memory.

 Next, another embodiment of the present invention will be described.

FIGS. 4 and 5 are cross-sectional views showing an LOD type high voltage MOS transistor according to another embodiment of the present invention. The plan view of this LOD type high voltage MOS transistor is the same as that of FIG. Here, FIG. 4 and FIG. 5 are II-
It corresponds to a cross-sectional view along the line II and the line III-III.

As shown in FIGS. 1, 4 and 5, in the LOD type high breakdown voltage MOS transistor according to this embodiment, the wiring 9
It has become a type of low impurity concentration portion 6a ^- of well portion of the periphery of the p ⁺ -type drain region 6 of the contact portion, the p ⁺ -type lower well e.g. p drain region 6. That is, in this embodiment, the p ⁻ -type low impurity concentration portion 6a is also formed below the p ⁺ -type drain region 6.

After this to produce a LOD-type high voltage MOS transistor according to the embodiment, the first formed up to the sixth gate electrode G as shown in Figure A in the same manner as described in the foregoing examples, p ⁺
A resist pattern 11 having a predetermined shape with an opening at a portion corresponding to the portion where the mold drain region 6 is formed is formed by lithography. Thereafter, using the resist pattern 11 as a mask, a low concentration p-type impurity such as B is ion-implanted into the semiconductor substrate 1 (impurities implanted into the semiconductor substrate 1 are indicated by dots). The dose of this p-type impurity ion implantation is, for example, that the concentration of the low impurity concentration portion 6a formed by diffusion of the p-type impurity is lower than that of the low impurity concentration 6a formed below the field insulating film 2. It is chosen to be approximately the same as the concentration.

Next, after removing the resist pattern 11, as shown in FIG. 6B, using the gate electrode G and the field insulating film 2 as a mask, a p-type impurity such as, for example, B is highly concentrated in the semiconductor substrate 1 at high energy. Ion implantation. After this,
Annealing for electrical activation of the implanted impurities is performed. Thereby, as shown in FIG. 1, FIG. 4 and FIG.
A p ⁺ -type drain region 6 having a p ⁺ -type source region 5 and a p ⁻ -type low impurity concentration portion 6a is formed. Thereafter, the process proceeds in the same manner as described in the above-described embodiment, and the desired LOD
-Type high voltage MOS transistor is completed.

As described above, according to this embodiment, the drain region 6
Not only the part around the contact part of the wiring 9 but also the part around the contact part of the wiring 9 and the lower part thereof are p ⁻ -type low impurity concentration parts 6a, so that the part at the junction between the drain region 6 and the semiconductor substrate 1 is formed. A wide depletion layer 10 is formed everywhere.
Then, the drain electric field becomes more uniform. This can further improve the breakdown voltage of the LOD type high breakdown voltage MOS transistor.

Although the embodiments of the present invention have been specifically described above, the present invention is not limited to the above-described embodiments, and various modifications based on the technical idea of the present invention are possible.

For example, in the above-described two embodiments, four contact holes C _{1 to} C ₄ are used to contact the wiring 9 with the drain region 6. However, for example, five or more contact holes can be used. Needless to say,

Also, in the above two embodiments, the p-channel
Although the case where the present invention is applied to the LOD type high withstand voltage MOS transistor has been described, the present invention can also be applied to an n-channel LOD type high withstand voltage MOS transistor. Further, the present invention is not necessarily limited to the LOD type high voltage MOS transistor, but can be applied to various high voltage MIS transistors other than the LOD type high voltage MOS transistor.

〔The invention's effect〕

As described above, according to the present invention, a plurality of wiring contact portions are provided in a drain region surrounded by an inter-element isolation insulating film, and the plurality of wiring contact portions are each surrounded by an in-element isolation insulating film. Since the drain region has a low impurity concentration in a portion below the inter-element isolation insulating film and the in-element isolation insulating film and around the wiring contact portion,
The withstand voltage can be improved.

Further, since the lower portion of the drain region has a low impurity concentration, the withstand voltage can be further improved.

[Brief description of the drawings]

FIG. 1 is a plan view showing an LOD type high breakdown voltage MOS transistor according to an embodiment of the present invention, FIG. 2 is a sectional view taken along the line II-II of FIG. 1, and FIG. 4 and 5 are cross-sectional views taken along the line III.
6A and 6B are cross-sectional views showing a D-type high-voltage MOS transistor, and FIGS. 6A and 6B are cross-sectional views for explaining a method of manufacturing the LOD-type high-voltage MOS transistor shown in FIGS. 4 and 5; Is a plan view showing a conventional LOD type high voltage MOS transistor, and FIG.
The figure is a cross-sectional view along the line VIII-VIII in FIG. 7, and FIG. 9 is a cross-sectional view along the line IX-IX in FIG. Description of main reference numerals in the drawings 1: semiconductor substrate, 2: field insulating film, 5: source region, 6:
Drain region, 6a: lower impurity concentration portion, 8,9: wiring, 10: depletion, G: gate electrode, C ₁ -C _8: contact hole.

Claims (2)

(57) [Claims] A plurality of wiring contact portions in a drain region surrounded by an inter-element isolation insulating film, each of the plurality of wiring contact portions being surrounded by an in-device isolation insulating film; A high withstand voltage MIS transistor, wherein a portion below the inter-element isolation insulating film and the inter-element isolation insulating film and around the wiring contact portion has a low impurity concentration. 2. The high breakdown voltage MIS transistor according to claim 1, wherein a lower portion of said drain region of said wiring contact portion also has a low impurity concentration.