JP2992992B2 - Image coding device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image coding apparatus for performing block coding on image data. [Prior Art] When digital image data, for example, a signal obtained by digitizing a television signal is transmitted to another device via a transmission line, the image information data has a very large amount of information. It is necessary to compress the amount of information by some method. As one of such compression methods, a block code or a transmission method in which image information for one screen is divided into a predetermined number of samples and compression encoding is performed on samples constituting the block for each block is known. Have been. Specifically, the maximum value and the minimum value of the sample belonging to the block of interest are detected, and between the minimum value and the maximum value, that is,
Linearly quantize the dynamic range and calculate the index of which quantization level belongs to each sample,
The maximum value, the minimum value and the corresponding index are transmitted. Since the number of bits of the index can be significantly smaller than the number of bits of the original sample, the amount of transmission can be compressed. [Problems to be Solved by the Invention] In this conventional block coding method, linear quantization is performed based on the dynamic range of sample values in a block. Therefore, when the dynamic range is narrow, encoding is performed with high accuracy. However, if the dynamic range is very wide, for example, if there is extreme brightness in the block or if the block contains a boundary, the encoded data will be very inaccurate, Large distortion occurs in the restored image. To solve this problem, if the dynamic range is wide, the average value of the sample values is detected, and the average value and the maximum value, and the average value and the minimum value are equally divided into linear quantum values. A method of adaptively switching between linear quantization between the above-described maximum value and minimum value and linear quantization considering the average value in accordance with a dynamic range is conceivable. However, in this method, there are cases where the average value data exists in the transmission data sequence and cases where it does not exist, resulting in a variable-length data sequence. For example, if a television signal is to be digitized and recorded on a video tape recorder, a variable-length data stream is used to process the data in real time, especially in a large-capacity memory where reproduction processing is difficult. Not only is the configuration required,
Since signal processing in special reproduction (for example, search reproduction and slow reproduction) is difficult, it is not suitable for a transmission system such as a recording / reproduction system. Accordingly, an object of the present invention is to provide an image encoding device that takes into account the distribution of sample values in a block and forms a fixed-length data sequence. [Means for Solving the Problems] An image encoding apparatus according to the present invention includes a block dividing unit that divides digital image data into blocks each including a predetermined number of samples, and detects a dynamic range of the intra-block image data. Detecting means, coding means for quantizing and coding the block data, and transmission means for forming the block data coded by the coding means into a transmission data sequence in a predetermined transmission unit and transmitting the data. Wherein the encoding means includes a first encoding mode for performing an encoding process by linear quantization and a second encoding mode for performing an encoding process by nonlinear quantization according to a data distribution state of the block data. Encoding mode, wherein the second encoding mode is selected when the dynamic range detected by the detection means is equal to or larger than a predetermined value. Is characterized by selecting the first encoding mode and encoding the block data. Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a television signal encoding apparatus according to one embodiment of the present invention. In FIG.
Reference numeral 10 denotes a digital image signal input terminal. The television signal used in the present embodiment is based on the NTSC system, and the input terminal 10 receives the NTSC television signal. Reference numeral 11 denotes an A / D converter which samples the television signal input to the input terminal 10 at a sampling frequency four times the carrier frequency f _SC and converts the digital signal into a digital television signal having 8 bits per sample. 12 is to temporarily store digital television signals sequentially input in units of horizontal scanning lines in a memory or the like, change the reading order, and read them out, thereby editing and outputting the scanning order in units of horizontal scanning lines in a block. Block circuit. In the illustrated embodiment, four blocks in the horizontal direction and four lines in the vertical direction constitute one block. The sample sequence rearranged by the blocking circuit 12 is applied to a minimum value detector 14, a maximum value detector 16, an intra-block average value calculator 18, and a delay circuit 20. The average value calculating circuit 18 integrates a sample value for one block, a dividing circuit that divides the integrated value of the integrating circuit by the number of sample points, that is, 16, and a hold that holds the division result of the dividing circuit. It consists of a circuit, and outputs the average value m ₀ sample values for one block. The subtractor 22 calculates a difference between the maximum value MAX detected by the maximum value detector 16 and the minimum value MIN detected by the minimum value detector 14. The output MIN of the minimum value detector 14,
The output DR (= MAX−MIN) of the subtractor 22, the output MAX of the maximum value detector 16, and the output m ₀ of the average value detector 18 are sent to the conversion circuit 32 via delay circuits 24, 26, 28, and 30, respectively. Applied. The conversion circuit 32 is also inputted sample value DT which is formed by the A / D converter 11 from the delay circuit 20, MAX, MIN, DR, and quantizes the DR based on m _0, in which the quantization step DT is Outputs the index ID indicating whether it belongs. The details will be described later. Note that the delay circuits 24, 26, 28, and 30 are for adjusting the timing with the sample value DT applied from the delay circuit 20 to the conversion circuit 32. In the present embodiment, as a method of encoding a digital television signal, the dynamic range DR in one block of sample values DT is divided into eight equal parts as shown in FIG. 3-bit index indicating to which divided area of the dynamic range it belongs
ID ₁ and a first operation mode in which each of the above-mentioned MAX and MIN data is formed by 8 bits as information representing the dynamic range of each block, and MAX, MIN and ID ₁ are output instead of the sample value DT; the dynamic range DR FIG. 6 (b) to 4 equal parts between the MIN and m _0, as shown, between the m ₀ and MAX 4 equal parts, which divided area of each sample value DT dynamic range And the 3-bit index ID ₂ and the MIN and m ₀ data are formed by 8 bits and MIN and m ₀ data respectively as information indicating the dynamic range of each block. Then, the second operation mode for outputting MAX, MIN, m ₀ and ID ₂ is adaptively switched according to the dynamic range DR. 34 receives the dynamic range DR from the delay circuit 26,
An identifier generating circuit that outputs an identifier for identifying an operation mode. Specifically, by comparing the threshold value and the DR for the operating mode selected, if DR is less than the threshold value, outputs an identifier MD ₁ that specifies the first operation mode, the second operation in the case of other and it outputs the identifier MD ₂ to specify the mode. The conversion circuits 36 and 38 and the parallel / serial conversion circuit 40 are circuits that function when the second operation mode is selected. Specifically, the conversion circuit 36 converts an 8-bit MIN into a 4-bit MI.
The conversion circuit 38 converts the 8-bit m ₀ into the 4-bit m
Convert to ₀ '. Such a conversion is implemented, for example, by a memory table system that outputs 4-bit data corresponding to 8-bit input data. parallel·
The serial conversion circuit 40 converts the 4-bit signals from the conversion circuits 36 and 38 into serial, ie, 8-bit signals. When the first operation mode is selected, the selection circuit 42 selects MIN (8 bits) from the delay circuit 24, and selects the second operation mode.
When the operation mode is selected, the parallel / serial conversion circuit 40
Select the 8-bit signal from. MAX from delay circuit 28, identifier M from identifier generation circuit
D, the selection output of the selection circuit 42 and the index ID from the conversion circuit 32 are applied to the data string formation circuit 44. The data string forming circuit 44 converts these input signals into a serial data string and outputs it. FIG. 5A shows an output data string when the first operation mode is selected, and FIG. 5B shows an output data string when the second operation mode is selected. As described above, in both operation modes, the length of the data string output from the data string forming circuit 44 is the same and has a fixed length, so that even when the output data string is transmitted or recorded / reproduced. The signal processing can be performed with a simple configuration. In particular, in the case of recording and reproduction, special reproduction and the like can be easily performed. FIG. 2 shows a specific configuration example of the conversion circuit 32. input signal
MIN, MAX, DT are applied to the conversion circuits 50, 52. Average value m ₀
Is applied to the conversion circuit 52. The outputs of the conversion circuits 50 and 52 and the dynamic range DR are applied to the output selection circuit 54. The conversion circuit 50 performs encoding in the above-described first operation mode, and the conversion circuit 52 performs encoding in the second operation mode. Outputs 3-bit index ID ₁ and ID ₂ respectively. The output selection circuit 54, under the same conditions as the identifier generation in the identifier generation circuit 34, according to the dynamic range DR,
The output of the conversion circuit 50 or 52 is selected and output. FIG. 3 shows a specific column of the conversion circuit 50. Subtractor 72 is MAX
Is subtracted from MIN to output the dynamic range DR. This dynamic range is reduced to 1/8 by the divider 74 and then supplied to the comparator 81 directly and to the comparators 82 to 87 via the multipliers 75 to 80. Each of the multipliers 75 to 80 multiplies the input signal by a factor of 2, 3,. The subtractor 88 subtracts MIN from the sample value DT in the block, and the subtraction result DT '
(= DT−MIN) is applied to the other inputs of the comparators 81 to 87. Each of the comparators 81 to 87 supplies the comparison results C1 to C7 to the priority encoder 90. C1 to C7 are as follows according to the output DT 'of the subtractor 88. (1) 0≤DT '<(1/8) DR C1 = C2 = C3 = C4 = C5 = C6 = C7 = 0 (2) (1/8) DR≤DT'<(2/8) DR C1 = 1, C2 = C3 = C4 = C5 = C6 = C7 = 0 (3) (2/8) DR ≤ DT '<(3/8) DR C1 = C2 = 1, C3 = C4 = C5 = C6 = C7 = 0 (4) (3/8) DR ≤ DT '<(4/8) DR C1 = C2 = C3 = 1, C4 = C5 = C6 = C7 = 0 (5) (4/8) DR ≤ DT'< (5/8) DR C1 = C2 = C3 = C4 = 1, C5 = C6 = C7 = 0 (6) (5/8) DR ≤ DT '<(6/8) DR C1 = C2 = C3 = C4 = C5 = 1, C6 = C7 = 0 (7) (6/8) DR ≦ DT ′ <(7/8) DR C1 = C2 = C3 = C4 = C5 = C6 = 1, C7 = 0 (8) (7) / 8) DR≤DT '<DR C1 = C2 = C3 = C4 = C5 = C6 = C7 = 1 Conditions (1), (2), (3), (4), (5),
(6), (7), (8) it it shows a first area A ₁ of FIG. 6 _{(a), A 2, A} 3, A 4, A 5, A 6, A 7, A 8. The priority encoder 90 is (000) for (1), (001) for (2), (010) for (3), and (01) for (4) above.
1), (5) (100), (6) (101),
In the case of (7), the 3-bit index ID ₁ of (110) and in the case of (8) (111) are output. FIG. 4 shows the details of the conversion circuit 52. Subtractor 100 subtracts MIN from the sample value DT, the subtracter 102 subtracts the MIN from m _0, subtractor 104 subtracts the m ₀ from MAX. The output (m ₀ −MIN) of the subtractor 102 is reduced to / 4 by the divider 106 and then applied to the multipliers 107 and 108 and the comparator 110. Multipliers 107, 10
8 multiplies the input signal by two and three times, respectively.
Is applied. The output (MAX−m ₀ ) of the subtractor 104 is divided by the divider 114
After that, it is applied to the multipliers 115 and 116 and the adder 117. Multipliers 115 and 116 respectively double the input signal,
It multiplies and supplies to adders 118 and 119. The outputs of the subtractor 102 are applied to the adders 117, 118, and 119, and the addition result is applied to one input of the comparators 120, 121, 122, and 123. Outputs DT '(= DT-MIN) of the subtractor 100 are supplied to the other inputs of the comparators 110 to 112 and 120 to 123. When the outputs of the comparators 110 to 112 and 120 to 123 are D1 to D7,
The following D1 to D7 are input to the priority encoder 124 in each case. (1) 0 ≦ DT ′ <(1/4) (m ₀ −MIN) D1 = D2 = D3 = D4 = D5 = D6 = D7 = 0 (2) (1/4) (m ₀ −MIN) ≦ DT ′ <(2/4) (m ₀ −MIN) D1 = 1, D2 = D3 = D4 = D5 = D6 = D7 = 0 (3) (2/4) (m ₀ −MIN) ≦ DT ′ < _{(3/4) (m 0 -MIN)} D1 = D2 = 1, D3 = D4 = D5 = D6 = D7 = 0 (4) (3/4) (m 0 -MIN) ≦ DT '<m 0 -MIN D1 = D2 = D3 = 1, D4 = D5 = D6 = D7 = 0 (5) m 0 -MIN ≦ DT '<(1/4) (MAX-m 0) + (m 0 -MIN) D1 = D2 = D3 = D4 = 1, D5 = D6 = D7 = 0 (6) (1/4) (MAX−m ₀ ) + (m ₀ −MIN) ≦ DT ′ <(2/4) (MAX−m ₀ ) + (M ₀
−MIN) D1 = D2 = D3 = D4 = D5 = 1, D6 = D7 = 0 (7) (2/4) (MAX−m ₀ ) + (m ₀ −MIN) ≦ DT ′ <(3/4) (MAX−m ₀ ) + (m ₀
−MIN) D1 = D2 = D3 = D4 = D5 = D6 = 1, D7 = 0 (8) (3/4) (MAX−m ₀ ) + (m ₀ −MIN) ≦ DT ′ <MAX−MIN D1 = D2 = D3 = D4 = D5 = D6 = D7 = 1 Conditions (1), (2), (3), (4), (5),
(6), (7), (8) shows the area _{B 1, B 2, B 3} , B 4, B 5, B 6, B 7, B 8 of FIG. 6, respectively (b). priority·
The encoder 124 assigns the same three bits in the case of the conversion circuit 50 for each case, and outputs the index ID _2. FIG. 7 shows a digital signal corresponding to the encoding device of FIG.
1 shows a schematic configuration of a television signal decoding device. A digital television signal input from a transmission path (not shown) is supplied from an input terminal 200 to a mode identification circuit 202, a maximum / minimum value separation circuit 204, a maximum / minimum / average value separation circuit 206, and an index separation circuit 208. Applied. Mode identification circuit 2
02 separates the mode identifier MD and separates the maximum and minimum values.
204 indicates that the identifier MD from the mode identification circuit 202 is MD ₁ (first
Operation mode), the maximum value MAX and the minimum value MIN are separated and output, and the maximum value / minimum value / average value separation circuit 206
When the identifier MD from the mode identification circuit 202 is MD ₂ (second operation mode), the maximum value MAX and the minimum value MIN ′ of 4 bits are set.
And the average value m ₀ ′ is separated and output, and the index separation circuit 208 separates and outputs the index portion. Since the data string supplied to each separation circuit has a fixed-length code for each block, these separations are extremely easy.
For separation, a clock generation circuit (not shown) is provided. The decoding circuit 210 decodes each sample value DT from each data separated by the separation circuits 202, 204, 206, and 208 and supplies the data to the D / A converter 212. The D / A converter 212 uses the sampling frequency 4f _SC as a synchronization signal, and
Is converted into an analog signal to restore and output the NTSC television signal. The details of the decoding circuit 210 are shown in FIG. 220 is a restoration circuit for restoring each sample value from the index ID ₁ in the first operation mode, 222 is a restoration circuit for restoring an encoded signal for restoring each sample value from the index ID ₂ in the second operation mode, 224, in accordance with the mode identifier MD, a selection circuit for selecting one of the output DT ₂ outputs DT ₁ and restore circuit 222 restore circuit 220. FIG. 9 shows a configuration example of the restoration circuit 220. Subtractor 226 is DR
(= MAX−MIN) is calculated and supplied to the divider 228. The divider 228 makes the input 1/8, and the multipliers 230 to 235 and the selection circuit
238. Multipliers 230 to 235 multiply the input signal by two, three, four, five, six and seven times to select circuit 238
Is applied. Thus, the boundary values when the dynamic range DR is equally divided into eight are input to the selection circuit 238. “0” is also input from the terminal 237 to the selection circuit 238. The selection circuit 238 sets the index ID _{1 for} each sample.
, One of the eight inputs is selected and output. Table 1 shows the relationship. Divider 240 halves the output of divider 228 to form DR / 16, and adder 242 adds divider 240 to the selected output of selector 238.
Are added to obtain a representative value. The adder 242 further adds MIN from the delay circuit 241. The delay circuit 241 is for timing adjustment. The output of the adder 242 is supplied to the selection circuit 224 as a sample value DT ₁ restored (Figure 8). FIG. 10 shows details of the restoration circuit 222. The conversion circuit 243 is composed of a memory table or the like, and has a 4-bit MIN ′
Is converted to an 8-bit MIN, and the conversion circuit 245 is also formed of a memory table or the like, and converts 4-bit m ₀ ′ to 8-bit m ₀ . Subtractor 244 calculates the difference between m ₀ and MIN,
Subtractor 246 calculates the difference between the MAX and m _0. The divider 248 sets the output (m ₀ −MIN) of the subtractor 244 to / 8, and sets the multipliers 249, 250, 2
51 and the selection circuit 252. The multipliers 249, 250, and 251 multiply the input signal by three times, five times, and seven times and supply it to the selection circuit 252. The divider 254 sets the output (MAX−m ₀ ) of the subtractor 246 to 1
/ 8 is applied to the multipliers 255, 256, 257 and the adder 258. Multipliers 255, 256, 257 respectively triple the input signal,
5 times and 7 times are applied to the adders 259, 260 and 261. Each of the adders 258 to 261 adds the output (m ₀ −MIN) of the subtractor 244 and supplies the result to the selection circuit 252. The selection circuit 252 selects and outputs any one of the eight inputs according to the index ID _{2 of} each sample. Table 2 shows the relationship. The output of the selection circuit 252 is applied to the adder 262. Adder
It is applied MIN through the delay circuit 264 to 262, 8 as a sample value DT ₂ the addition result of the two signals is restored
It is applied to the selection circuit 224 in the figure. As described above, in the present embodiment, by encoding a television signal, which is one type of image information, in the two types of operation modes as described above, even if the amount of information is small, the image quality can be improved. In addition to being capable of being encoded and transmitted in a state where deterioration is small, when encoding is performed based on the above-described two types of operation modes, the unit code length of a data string obtained by the encoding changes according to the type of operation mode. In addition, even when data strings based on the two types of operation modes are mixed in the data string, it is possible to reliably determine in which operation mode the transmitted data string is encoded data. It can be determined and restored to the original signal. Although the description has been made with reference to the encoding transmission of the NTSC television signal as an example, the present invention is not limited to this.
The same effects can be obtained by applying the present invention to a transmission apparatus for encoding a television signal of the SECAM system or a transmission apparatus for transmitting an image signal other than the television signal, for example, a facsimile signal. [Effects of the Invention] As can be easily understood from the above description, according to the present invention, based on the dynamic range of image data in a block, the coding mode by linear quantization or the distribution state of image data in a block are Since the block data is encoded by selecting an encoding mode based on the corresponding non-linear quantization, the distortion of the restored image can be reduced as compared with the related art.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing the configuration of an encoding apparatus according to an embodiment of the present invention; FIG. 2 is a detailed view of a conversion circuit 32 shown in FIG. 1;
4 and 5 are detailed diagrams of the conversion circuits 50 and 52 of FIG. 2, respectively. FIG. 5 is an example of an output code string of the data string formation circuit 44 of FIG. 1, and FIG. FIG. 7 is an example of the configuration of a decoding device, FIG. 8 is a detailed example of the decoding circuit 210 of FIG. 7, and FIGS. 9 and 10 are each a diagram of FIG. 4 is a detailed example of the restoration circuits 220 and 222. 14 ... Minimum value detector, 16 ... Maximum value detector, 18 ... Average value calculator in block, 32 ... Conversion circuit, 34 ... Identifier generation circuit, 42 ... Selection circuit, 44 ... Data string Forming circuit

   ────────────────────────────────────────────────── ─── Continuation of front page    (72) Inventor Shin Shimokoriyama               3-30-2 Shimomaruko, Ota-ku, Tokyo               Inside Canon Inc. (72) Inventor Tetsuya Shimizu               3-30-2 Shimomaruko, Ota-ku, Tokyo               Inside Canon Inc. (72) Inventor Akio Fujii               770 Shimonoge, Takatsu-ku, Kawasaki-shi, Kanagawa               Inside the Tamagawa Office of Canon Inc.                (56) References JP-A-60-106228 (JP, A)

Claims (1)

(57) [Claims] Blocking means for dividing the digital image data into blocks consisting of a predetermined number of samples; detecting means for detecting the dynamic range of the intra-block image data; coding means for quantizing and coding the block data; Transmitting means for forming the block data encoded by the encoding means and forming a transmission data sequence in a predetermined transmission unit and transmitting the data; and wherein the encoding means performs an encoding process by linear quantization. A first encoding mode, and a second encoding mode for performing an encoding process by nonlinear quantization according to a data distribution state of the block data, wherein a dynamic range detected by the detection unit is a predetermined value. In the above case, the second
An image encoding apparatus for selecting the first encoding mode, and otherwise selecting the first encoding mode, and encoding the block data.