JP2991938B2 - Chroma key synthesis circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for real-time chroma key synthesis of two video images.

[0002]

2. Description of the Related Art A multimedia computer which uses video moving images as a means of communication (mutual communication) is installed one at each of two separate locations, and video moving images taken by both video cameras are mutually communicated with each other. If you send it to Chroma Key, you can have intimate visual communication. In addition, in a presentation system, a desired portion of a reproduced video moving image is synthesized by chroma-keying a video moving image reproduced from a VTR or an optical disk device with an image of one's own hand shot by a video camera. A presentation can be made while pointing with a hand image.

FIG. 22 shows a configuration example of a conventional chroma key synthesizing circuit mounted on a system device having such a function. The circuit of FIG. 22 has a function of synthesizing and outputting Vout on the right side based on the images Va (background) and Vb (foreground) arranged on the left side, as shown in the image diagram of the screen image in FIG. In FIG. 22, 901, 902, 903, 90
Reference numeral 6 denotes a D flip-flop (DF / F / H) which holds and outputs input data at the rising edge of a clock signal (clock).
F). Numeral 1 is a condition determining means for inputting two input data A and B, and outputting a match signal if the input data A meets the condition indicated by the input data B. In the example of FIG. Realize. The comparator 21 receives two pieces of input data A and B, determines whether the value of the input data A is within the range indicated by the input data B, and outputs a match signal “1” to the output Y if the value is included. Output. Reference numeral 4 denotes a data selector, which receives the input signal B when the selection input S is "0", the input signal A when the selection input S is "1", and the output Y
Respectively. In FIG. 22, B (0) indicates that B is selected when S = 0, and A (1) indicates that A is selected when S = 1. Dcon is condition data to be input to the comparator 21. In this example, RGB (Red: red,
Green: Green, Blue: Blue) RG corresponding to each 8 bits
B upper limit (8 bits x 3) and lower limit (8 bits x
In order to specify the range of the moving image data value by giving 3), a total of 48 bits of condition data Dcon are employed.

[0004] The D flip-flop 901 is provided with image data (a video of a building photographed from the ground and reproduced by a VTR) as shown by Va in FIG.
Input in units (24 bits) in synchronization with the clock signal. The Va screen is composed of 640 pixels in width and 480 pixels in height, and each pixel has color data of 8 bits for RGB, that is, 24 bits. The moving image signal Va is horizontally scanned from the pixel at the upper left corner of Va in FIG.
Go to the left corner of the second line, scan the second line horizontally, repeat this, reach the lower right corner, and return to the upper left corner again. Similarly, the D flip-flop 902 synchronizes the image data shown in Vb of FIG. 23 (the image in which the user's hand is photographed with a video camera in front of the blue background (blue background)) in synchronization with the clock signal in pixel units. And enter. Of course, the input pixel data are all at the same scan position and are synchronized.

The condition data Dcon is set to the color range (key color) of “blue back” of Vb in FIG. 23, and the D flip-flops 901 and 902 hold the pixel data of Va and Vb in synchronization with the clock signal. When output, the condition determination means 1 outputs "1" only when it corresponds to the "blue back" portion of the Vb image data. As a result, from the D flip-flop 906 latching the output of the data selector 4, “hand and arm” and its “shadow” (which is always “blue back”) as shown in Vout of FIG. Is obtained by superimposing (chroma key composition) the image of the "building" on the image of the "building".

[0006]

Looking at Vout in FIG. 23, "hand and arm" and "shadow" are overlying the image of "building", and the image underneath is not visible at all. This has the drawback that quite a large amount of video information is lost, sometimes causing misunderstanding, and is often fatal.

An object of the present invention is to point (instruct) in real time a desired portion of a first video moving image with an image (second video moving image) such as a "hand" photographed by a user's own video camera. To provide a chroma-key compositing circuit that prevents the pointed first video movie from being hidden by the pointing "hand" or its "shadow" so that the first video movie that is pointed can be made difficult to see. is there.

[0008]

In order to achieve the above object, a first chroma key synthesizing circuit according to the present invention uses a video moving picture as a background as a first moving picture and a video moving picture as a foreground, for example, as a pointing means. When the second moving image is set as the second moving image, at least one mixing circuit for performing weighted addition (semi-transparent synthesis) of the pixel data of the first and second moving images, and the pixel data of the second moving image as conditional data (color range ), A plurality of condition determining means having a function of outputting a match signal when the condition is satisfied, and a first moving image (background) in accordance with a combination of the match signal output of each of the plurality of condition determining means; A second moving image (foreground), and a data selector for selectively outputting one of the outputs (semi-transparently synthesized) of at least one mixing circuit. .

The second chroma key synthesizing circuit according to the present invention includes a mixing circuit for weighted addition (semi-transparent synthesizing) of the pixel data of the first and second moving images according to the transparency data, and A plurality of condition determining means having a function of outputting a match signal when the pixel data of the moving image satisfies the condition indicated by the condition data (color range), and a combination of the respective match signal outputs of the plurality of condition determining means And a data selector for supplying at least one of variable transparency data, fixed complete transparency data, and fixed opacity data to the mixing circuit in accordance with the above.

The third chroma key synthesizing circuit according to the present invention converts the "colored shadow" generated in the second moving image (foreground) into the "colorless shadow" so as to convert the second moving image (foreground) into the "colorless shadow". The image processing apparatus further includes a black-and-white conversion circuit that receives pixel data (having a color), removes a color component, and outputs only a luminance (gray) component. According to the combination, the output data of the black and white conversion circuit and the pixel data of the first moving image (background) are weighted and added so as to be translucently combined, so that a more natural “shadow” falls on the first moving image. It is like that.

A fourth chroma key synthesizing circuit according to the present invention employs a two-stage pipeline configuration.
In order to reduce the power consumption, all inputs of the mixing circuit are fixed when translucent synthesis is not required.

[0012]

By adopting the configuration provided with the plurality of condition determining means, a partial area (for example, only "shadow" or "hand and arm" and "shadow") of the second moving image (foreground) is used. Both sides)
Is translucent and superimposed on the first video (background), so that the second video is not overlaid on the foreground.
The first moving image can be pointed by the moving image. Also,
If the "hand and arm" and the "shadow" are translucently synthesized and superimposed with different degrees of transparency, more effective pointing and presentation can be achieved. Moreover, if a "colored shadow", which always occurs when using a blue background or the like, is converted to a "shadow" without complete color and translucently synthesized with the first moving image (background), an extremely natural synthesized moving image can be obtained. can get.

[0013]

【Example】

(Embodiment 1) FIG. 1 is a block diagram showing a chroma key synthesizing circuit according to a first embodiment of the present invention. In FIG. 1, V
a, Vb, and Vout are TV-size image data composed of 640 pixels by 480 pixels, as shown in FIG. 6.
b and Vout each have one pixel of 8 bits each for RGB,
It has a total of 24 bits of color data. Video data Va, V
When b is input to the circuit of FIG. 1, a non-interlaced scan starting from the upper left corner of the screen image diagram of FIG. 6 (the uppermost line is scanned rightward from the upper left corner to the upper right corner, and the second line from the top) To the left corner, scan the second line to the right, go to the lower right corner, return to the upper left corner, and repeat this.) In this order, the data in units of one pixel are converted to the clock signal (clock). Input is synchronized. Of course, the phase of the non-interlace scan is also completely synchronized.

Reference numeral 3 denotes a mixing circuit for performing weighted addition of two input data A and B.
A + (1-t) B data is obtained.
t is transparency, and takes a value of 0 ≦ t ≦ 1. When t = 0 (completely opaque), M = B (foreground), and when t = 1 (completely transparent), M = A (background). When 0 <t <1, translucent composition is obtained. In the case of FIG. 1, the data is 8 for each of RGB.
Since the bits are formed, R is weighted by R, G is G, and B is weighted by B. Transparency t
Is supplied as 8-bit transparency data T. t = 0 is T
= “00000000” and t = 1 corresponds to T = “11111111”.

FIG. 3 shows a configuration example of the mixing circuit 3.
301, 302, 304, 305, 307, 308 are 8
It is a multiplication circuit of bit / 2 input, 303, 306, 3
Reference numeral 09 denotes an 8-bit output addition circuit. Reference numeral 310 denotes a complement conversion circuit that converts t into (1-t), that is, converts 8-bit T into ("11111111" -T) and outputs the result. Specifically, the sign of all bits of T is inverted. 301-303
At red (Red), 304-306 at green (Green), 307
In 309, blue (Blue) is weighted and added. Red (R
ed), the output M is expressed as: M = (T × Va +
(“11111111” −T) × Vb) / “11111111”.

Referring again to FIG. 1, reference numeral 1 denotes a first condition determining means for inputting two input data A and B, and outputting a match signal m1 if the input data A meets the condition indicated by the input data B. In this embodiment, this is realized by the first comparator 21. The first comparator 21 has two input data A, B
And determines whether the value of the input data A is within the range indicated by the input data B, and if so, outputs a match signal “1” to the output Y. 2 is a second condition determination means, m2 is a match signal, and specifically, the second comparator 2
2. These are the same as the first condition determination means 1, the match signal m1, and the first comparator 21, respectively. The first comparator 21 stores the pixel data Vb of the second moving image and the first condition data Dcon1, and the second comparator 22 stores the pixel data Vb of the second moving image and the second condition data Dcon2. Supplied.

FIG. 2 shows an example of the configuration of the first and second comparators 21 and 22. Reference numerals 200 to 205 denote known magnitude comparators, which compare the input data P with the value of Q. If P is equal to or greater than Q, P> Q = “1” and P <Q
= “0”, and if P is smaller than Q, then P> Q = “0” and P <Q = “1”. 206 to 209 are known ANDs
The gate. The pixel data Vb of the second moving image is input to the input A of the first comparator 21 in 24 bits, that is, 8 bits for each of RGB, and the first condition data Dcon1 is input to the input B in 48 bits, ie, each of 8 bits for RGB. Each corresponding upper limit value Rma
x, Gmax, Bmax (8 bits each) and lower limit values Rmin, G
When min and Bmin (each 8 bits) are input, the pixel data value of the moving image of the input A is Rmin ≦ Red ≦ Rmax and Gmin ≦
Only when the condition of Green ≦ Gmax and Bmin ≦ Blue ≦ Bmax is satisfied, the output Y becomes “1”, and otherwise (0), the output Y becomes “0”.

Referring again to FIG. 1, reference numeral 4 denotes a three-input data selector which outputs Y in response to selection control inputs S1 and S0.
Is determined. That is, the input signal A is output when S1 = 0 and S0 = 1, the input signal B is output when S1 = 0 and S0 = 0, and the input signal C is output Y otherwise.
Is selected as In FIG. 1, for example, S1 = 0 and S0
A (01) indicates that A is selected when = 1. The A input of the data selector 4 is the pixel data Va (background) of the first moving image, the B input is the pixel data Vb (foreground) of the second moving image, and the C input is the output of the mixing circuit 3. Supplied.

Reference numeral 40 denotes a programmable (variably settable) code converter, which includes first and second condition determining means 1, 2
Is converted and output from the code composed of the match signals m1 and m2 output from. FIG. 4 shows an example of the configuration. Reference numeral 401 denotes an 8-bit D flip-flop;
02 and 403 are data selectors, both of which are known. A conversion rule (conversion table) is obtained by writing a conversion code (data for code conversion) from the 8-bit data buses D7 to D0 to the D flip-flop 401.
Can be set freely. FIGS. 5A to 5C show three setting examples of conversion tables for converting A1 and A0 into Q1 and Q0.
It is shown in (c). For example, in the setting of FIG.
A0 passes directly to Q1 and Q0 (no conversion). At this time, “11001010” is written in the D flip-flop 401.

Referring again to FIG. 1, reference numerals 901 to 906 denote D flip-flops which hold and output input data at the rising edge of the clock signal. These D flip-flops 901 to 906 are provided with 24-bit first moving image data Va, 24-bit second moving image data Vb, 48-bit first condition data Dcon1, 48-bit second condition data Dcon2, It holds and outputs 8-bit transparency data Tp and 24-bit output data Vout.

Next, the operation of the embodiment of FIG. 1 will be described with reference to FIG. In the D flip-flop 901, image data as a background (a video which is obtained by moving a high-rise building while moving from the ground and reproduced by a VTR) as shown by Va in FIG. Enter The Va screen is composed of 640 pixels in width and 480 pixels in height, and each pixel has color data of 8 bits for RGB, that is, 24 bits. D flip-flop 9
In 02, image data as a foreground as shown by Vb in FIG. 6 (video in which one's own hand is photographed by a video camera in front of a blue background) is input in pixel units in synchronization with a clock signal. Of course, the input pixel data are all at the same scan position and are synchronized.

As the first condition data Dcon1, the upper limit value and the lower limit value of the color data in the range covering the color representing the "blue back" of Vb are supplied. That is, for example, the distribution range of the color data of “blue back” is red: Red = Rmin to Rma
x = “00000000” to “00000010”, green: Green = Gmin
Gmax = “00000000” to “00000010”, blue: Blue =
If Bmin-Bmax = “11111100”-“11111111”, Dcon1 = Rmin · Rmax · Gmin · Gmax · Bmin
Bmax = "00000000 00000010 00000000 00000010 11
111100 11111111 ". The second condition data Dcon2 is supplied with the upper limit value and the lower limit value of the color data in the range covering the color representing the" shadow "of Vb. That is, the color range of the “shadow” is red: Red = Rmin to Rmax = “00000000” to “0000”
0001 ", green: Green = Gmin to Gmax =" 00000000 "
“00000001”, blue: Blue = Bmin to Bmax = “100000”
00 ”to“ 11110000 ”, Dcon2 = Rmin · Rmax
・ Gmin ・ Gmax ・ Bmin ・ Bmax = “00000000 000000
01 00000000 00000001 1000000011110000 ".

Now, pixel data for one pixel of Va and Vb are respectively stored in D flip-flops 901 and 902.
The first and second condition data Dcon1, Dcon2 and the transparency data Tp are D flip-flops 903, 904, 9 respectively.
05, the mixing circuit 3 outputs Va and Vb
Is semi-transparently synthesized and output in a distribution corresponding to the transparency data Tp. As shown by m1 and m2 in FIG. 6, the first condition determination means 1 matches only when the pixel of the “blue back” portion of Vb is captured because Dcon1 is set as described above. The signal "1" is output. Also, the second
Since Dcon2 is set as described above, the condition determining means 2 outputs the match signal "1" only when the pixel of the "shadow" portion of Vb is captured. The match signals m2 and m1 of the second and first condition determination means 2 and 1 are 0 and 1 in the "blue back" region of Vb, and the "hand and arm"
In this case, it becomes 0, 0, and in the case of "shadow", it becomes 1, 0 (in this example, there is almost no area where 1, 1 is obtained). Code converter 4
If “0” is set to “pass without conversion” as shown in FIG. 5A, moving image data such as Vout in FIG. 6 is obtained at the output of the D flip-flop 906 at the next clock signal. Will be. That is, Vout of the conventional example of FIG.
Compared to, the situation of the building in the background can be clearly understood through the "shadow" part. Shadows are originally seen through the groundwork, look very natural, and are effective for presentations.

Next, when the code converter 40 is set as shown in FIG. 5 (b), the data is obtained even when the match signals m2 and m1 from the second and first condition judgment means 2 and 1 are both "0". Since the selector 4 selects and outputs the output of the mixing circuit 3,
As shown by Vout in FIG. 7, not only “shadow” but also “hand and arm” can be seen through. As a result, all the background appears, and important information is not lost, so that not only the presentation effect but also the pointing effect is extremely improved.

(Embodiment 2) FIG. 8 is a block diagram showing a chroma key synthesizing circuit according to a second embodiment of the present invention. This embodiment eliminates the large data selector 4 for selectively outputting the 24-bit pixel data in FIG. 1 and uses the small 8-bit data selector 5 for selectively outputting the transparency data. In this embodiment, the same function as that of the embodiment is realized by small hardware.

In FIG. 8, the data selector 5 is a three-input selector that determines the output Y according to the selection control inputs S1 and S0. That is, the input signal A is selected as the output Y when S1 = 0 and S0 = 0, the input signal B when S1 = 0 and S0 = 1, and the input signal C otherwise as the output Y. The minimum value of transparency data "00000000" (opaque data) is input to the A input of the data selector 5, the maximum value "11111111" (completely transparent data) of the transparency data is input to the B input, and the clock signal is synchronized to the C input. The externally supplied transparency data Tp is supplied. The output Y of the data selector 5 is provided to the mixing circuit 3.

Next, the operation of the embodiment shown in FIG. 8 will be described. The operation up to the output of the code converter 40 is exactly the same as in FIG. Since the data selector 5 supplies the output Y as described above to the mixing circuit 3 as a transparency signal, if the code converter 40 is set as shown in FIG. 5A, the moving image data Vout as shown in FIG. The code converter 40 is shown in FIG.
If the settings are made as shown in (b), moving image data Vout as shown in FIG. 7 is obtained.

(Embodiment 3) FIG. 9 is a block diagram showing a chroma key synthesizing circuit according to a third embodiment of the present invention. In the present embodiment, the configuration of the first embodiment is modified so that two pieces of transparency data are input. The difference from FIG. 1 is that the number of mixing circuits is increased by one, and the data selector is changed from three inputs to four inputs.

In FIG. 9, reference numerals 6 and 7 denote first and second mixing circuits, each having exactly the same function as the mixing circuit 3 of FIG. Reference numerals 907 and 908 denote D flip-flops for supplying the first and second transparency data Tp1 and Tp2 to the first and second mixing circuits 6 and 7, respectively, in synchronization with a clock signal. Reference numeral 8 denotes a 4-input data selector, which outputs Y according to the selection control inputs S1 and S0.
Is determined. That is, the input signal A when S1 = 0 and S0 = 1, the input signal B when S1 = 1 and S0 = 1, and the input signal C when S1 = 0 and S0 = 0.
However, when S1 = 1 and S0 = 0, the input signal D is selected as the output Y. The A input of the data selector 8 is the pixel data Va (background) of the first moving image, the B input is the pixel data Vb (foreground) of the second moving image, and the C input is the pixel data Va of the first mixing circuit 6. The output is supplied to the D input, and the output of the second mixing circuit 7 is supplied to the D input.

Next, the operation of the embodiment shown in FIG. 9 will be described. As in the first embodiment (FIG. 1), it is assumed that the video as shown in FIG. 7 is input as the pixel data Va and Vb of the first and second moving images. The first condition data Dcon1 includes Vb
The upper and lower limits of the color data in the range covering the color representing the “blue back” are supplied. Second condition data Dco
The upper limit and the lower limit of the color data in the range covering the color representing the “shadow” of Vb are supplied to n2. When the code converter 40 is set to “pass without conversion” as shown in FIG. 5A, the “hand and arm” portion corresponds to the first transparency data Tp1 by the first mixing circuit 6. In the "shadow" portion, the result of the semi-transparent composition according to the second transparency data Tp2 by the second mixing circuit 7 is reflected in the output Vout, as shown in Vout in FIG. Video is obtained. In addition, the "hand and arm" portion can be seen through with transparency corresponding to the first transparency data Tp1 (for example, 30%: not very transparent), and the "shadow" portion can be seen through the second transparency data Tp2 (for example, 80). %: Almost transparent). That is, "hand and arm" and "shadow"
By making the transparency different, it is possible to make the appearance more natural, which is very effective for presentations and the like.

It is to be noted that the area where S1 = 1 and S0 = 1 is the area of "blue back" and "shadow", and this portion should not originally occur. However, if the color range of the chroma key condition data Dcon1 and Dcon2 is too wide,
The overlapped area appears along the boundary of the "shadow", and in the above example, the unexpected Vb (foreground) appears remarkably. At this time, if the conversion table of the code converter 40 is set as shown in FIG. 5C, Va (background) is output to Vout even when S1 = 1 and S0 = 1, so that the background is covered. It is convenient without being hidden.

(Embodiment 4) FIG. 10 is a block diagram showing a chroma key synthesizing circuit according to a fourth embodiment of the present invention. In this embodiment, the two mixing circuits 6, 7 and 24 in FIG.
By removing the large data selector 8 for selectively outputting bit pixel data and using one mixing circuit 3 and the small 8-bit data selector 9 for selectively outputting transparency data, the third embodiment is realized. It implements the same functions as the example with small hardware.

In FIG. 10, the data selector 9 is a four-input selector that determines the output Y according to the selection control inputs S1 and S0. That is, the input signal A when S1 = 1 and S0 = 1, the input signal B when S1 = 0 and S0 = 1, the input signal C when S1 = 0 and S0 = 0,
When S1 = 1 and S0 = 0, the input signals D are output Y
Is selected as The A input of the data selector 9 has a minimum value of transparency data “00000000” (opaque data).
However, the maximum value of transparency data "11111111" (completely transparent data) is input to the B input, the first external transparency data Tp1 synchronized with the clock signal is input to the C input, and the D input is synchronized to the clock signal. External second transparency data Tp2
Are supplied respectively. The output Y of the data selector 9 is provided to the mixing circuit 3.

Next, the operation of the embodiment shown in FIG. 10 will be described. The operation up to the output of the code converter 40 is exactly the same as in FIG. Since the data selector 9 supplies the output Y as described above to the mixing circuit 3 as a transparency signal, when the code converter 40 is set to “pass through without conversion” as shown in FIG. Moving image data Vout as shown in FIG. 7 in which the transparency of the “hand and arm” and the “shadow” are different is obtained.

In the first to fourth embodiments, the input data A is used as a function of the first and second comparators 21 and 22.
Matches with the condition of the condition data B, the match signal "1"
However, the present invention is not limited to this, and conversely, “0” may be output as a match signal (“1” when no match occurs). The selection rules of the data selectors 4, 5, 8, and 9 can be freely designed without being limited to each embodiment. The code converter 40 is not always necessary if the selection rules are set to suit the application.

In each embodiment, there are two condition judging means for monitoring foreground pixel data and outputting a match signal (key signal) if the condition is met. In response to this, there are three data selector options. There are four or four. If there are three or more colors to be extracted as keys, the condition determination means may be provided according to the number. For example, if there are three key colors of light blue, dark blue, and light green, three condition determination means are provided, and those colors are set as first, second, and third condition data Dcon.
1, Dcon2 and Dcon3, and their outputs may be supplied to the selection control inputs S2, S1, and S0 of the data selector. At this time, each pixel can be changed in 2 × 2 × 2 = 8 ways, and the number of options can be increased. If you want to make the "hand and arm" opaque and the "shadow" translucent chromakey, the color of some area of "hand and arm" falls within the "blue back" setting color range due to lighting. If some of the "hands and arms" become transparent unintentionally, reduce the set color range of the "blue back" and use multiple conditions to determine the color range of the "hands and arms". By providing the determination means, the transparent part of the "hand and arm" may be revived.

(Embodiment 5) FIG. 11 is a block diagram showing a chroma key synthesizing circuit according to a fifth embodiment of the present invention. In the present embodiment, the code converter 40 is removed from FIG. 9 described in the third embodiment, and the color component of the pixel data Vb of the second moving image is removed so that only the luminance component is output. Circuit 30 and the output data of the black and white conversion circuit 30 and the original pixel data Vb by appropriately switching between the first and second data.
Are newly provided with data selectors 31, 32 for supplying to the B inputs of the mixing circuits 6, 7, respectively, and a 4-bit output code converter 41. As a result, the "shadow" falling on the "background" becomes completely black and white (gray), and an unnatural color (such as blue) is not added, thereby enabling a more natural translucent composition.

In FIG. 11, a black-and-white conversion circuit 30 receives the pixel data Vb of the second moving image, removes its color component, and outputs only the luminance (gray) component.
FIG. 12 shows an example of the configuration. In FIG.
A coefficient circuit 333 multiplies input data by coefficients of 0.30, 0.59, and 0.11, respectively. Reference numeral 334 denotes a 3-input addition circuit that adds the output data of the coefficient circuits 331 to 333 and outputs an 8-bit result. The black-and-white conversion circuit 30 has RGB
The 8-bit output data of the adding circuit 334 is overlapped three times in correspondence with the input pixel data Vb of each 8-bit configuration, and is output as an apparent 8-bit configuration of RGB. For example, as Vb, Vb = “11111111 (R) 111111
When the data of "11 (G) 00000000 (B)" (yellow) is input, the output of the adder circuit 334 is "11100011", and the 24-bit output of the monochrome circuit 30 is "11100011".
(R) 11100011 (G) 11100011 (B) ". The coefficients of the coefficient circuits 331 to 333 are obtained by calculating Y /
Conversion formula to C (luminance / color difference) signal: Ey = 0.30 Er + 0.
The value is based on 59Eg + 0.11Eb, but need not be limited to this, and the coefficient may be set to a desired value.

Referring again to FIG. 11, data selector 3
Both 1 and 32 are the same as the data selector 4 of FIG. 21, and output the input signal B when the selection input S is "0" and output the input signal A when the selection input S is "1". It is. FIG. 13 shows a configuration example of the code converter 41. This is an extension of the code converter 40 of FIG. 4, where 411 and 412 are 8-bit D flip-flops, and 413 to 416 are data selectors, all of which are known. 8-bit data bus D7 to
Conversion code (data for code conversion) from D0 to D
By writing the data into the flip-flops 411 and 412, the conversion rule (conversion table) can be set freely. A1, A0
FIG. 14 shows an example of setting a conversion table for converting Q3 to Q3 to Q0. At this time, the D flip-flop 411,
“01001010” and “10111111” are written in 412 respectively.

Next, the operation of the embodiment shown in FIG. 11 will be described. As in the third embodiment (FIG. 9), the video as shown in FIG. 7 is input as the pixel data Va and Vb of the first and second moving images.
Assuming that both Q3 outputs are fixed at "1",
The data selectors 31 and 32 connect the pixel data V of the second moving image to the B inputs of the first and second mixing circuits 6 and 7, respectively.
11B, the operation of FIG. 11 is exactly the same as the operation when the code converter 40 is set to FIG. 5C, and the synthesized moving image is completely the same as Vout of FIG. Is obtained. At this time, the “shadow” of Vb in FIG. 7 is the “shadow” of “dark blue” because it is the shadow of the “hand and arm” that has fallen on the blue background. Since the “shadow” of “dark blue” is semi-transparently synthesized with Va, the “shadow” falling on the “building” of Vout becomes an unnatural “shadow” of “dark blue”.

Therefore, in the embodiment of FIG. 11, the outputs of Q2 and Q3 of the code converter 41 change appropriately according to the conversion table of FIG. In this example, the Q2 output outputs "1" in any case, and the pixel data Vb of the second moving image is directly connected to the B input of the first mixing circuit 6. Therefore, the “hand and arm” are translucently synthesized with the transparency Tp1 while preserving the original color. The Q3 output normally outputs "1", but becomes "0" only when the pixel data Vb becomes a "shadow" pixel, that is, when the inputs A1 = 1 and A0 = 0. . As a result, the data selector 32 is switched from the A input to the B input, and the output data of the monochrome circuit 30 is supplied to the B input of the second mixing circuit 7.
The second mixing circuit 7 semi-transparently combines the "shadow" and the "building" (Va) which have been converted to black and white and have only luminance (gray) with a transparency Tp2. That is, the "shadow" that has fallen into the "building" of Vout is completely black and white (gray) without any unnatural color component, and an extremely natural "shadow" can be obtained in the composite moving image Vout.

In order to obtain only the synthesized moving image shown in FIG. 7, the 4-bit output code converter 41 is replaced with a 2-bit output code converter 40 (FIG. 9), and the data selectors 31 and 32 are removed. The pixel data Vb of the second moving image may be directly supplied to the B input of the first mixing circuit 6, and the output of the monochrome circuit 30 may be directly connected to the B input of the second mixing circuit 7.

(Embodiment 6) FIG. 15 is a block diagram showing a chroma key synthesizing circuit according to a sixth embodiment of the present invention. In the present embodiment, the code converter 40 is removed from FIG. 10 described in the fourth embodiment, and the color component of the pixel data Vb of the second moving image is removed, so that only the luminance component is output. Circuit 30 and a data selector 31 for appropriately switching between the output data of the monochrome circuit 30 and the original pixel data Vb and supplying the data to the B input of the mixing circuit 3.
And a code converter 42 for 3-bit output. As a result, the "shadow" falling on the "background" becomes completely black and white (gray), and an unnatural color (such as blue) is not added, thereby enabling a more natural translucent composition.

In FIG. 15, the monochrome circuit 30 and the data selector 31 are exactly the same as those having the same names and numbers in FIG. 11 (Embodiment 5). FIG. 16 shows a configuration example of the code converter 42. This is an extension of the code converter 40 of FIG. 4, and 421 and 422 are 8-bit and 4-bit D flip-flops, respectively.
25 is a data selector, all of which are known. A conversion code (data for code conversion) is transferred from an 8-bit data bus D7 to D0 to a D flip-flop 4.
The conversion rules (conversion tables) can be set freely by writing to 21 and 422. FIG. 17 shows a setting example of a conversion table for converting A1 and A0 into Q2 to Q0. At this time, “01001010” and “1011” are written in the D flip-flops 421 and 422, respectively.

Next, the operation of the embodiment shown in FIG. 15 will be described. Similar to the fourth embodiment (FIG. 10), the video as shown in FIG. 7 is input as the pixel data Va and Vb of the first and second moving images, and if the Q2 of the code converter 42 of FIG.
Assuming that the output is fixed at "1", the data selector 31 continues to supply the pixel data Vb of the second moving image to the B input of the mixing circuit 3, so that the embodiment of FIG. The operation is exactly the same as the operation when the code converter 40 is set as shown in FIG. 5C, and a synthesized moving image exactly the same as Vout in FIG. 7 is obtained. At this time, the “shadow” of Vb in FIG. 7 is the “shadow” of “dark blue” because it is the shadow of the “hand and arm” that has fallen on the blue background. Since the “shadow” of “dark blue” is semi-transparently synthesized with Va, the “shadow” falling on the “building” of Vout becomes an unnatural “shadow” of “dark blue”.

Therefore, in the embodiment of FIG. 15, the Q2 output of the code converter 42 changes appropriately according to the conversion table of FIG. The Q2 output normally outputs "1", but becomes "0" only when the pixel data Vb becomes a "shadow" pixel, that is, when the inputs A1 = 1 and A0 = 0. As a result, the data selector 31 is switched from the A input to the B input, and the output data of the monochrome circuit 30 is supplied to the B input of the mixing circuit 3. Mixing circuit 3
Synthesizes the “shadow” and the “building” (Va), which have been converted to black and white and have only luminance (gray), translucently with transparency Tp2. That is,
The “shadow” falling on the “building” of Vout becomes completely black and white (gray) without any unnatural color components, and an extremely natural “shadow” can be obtained in the composite moving image Vout.

(Embodiment 7) FIG. 18 is a block diagram showing a chroma key synthesizing circuit according to a seventh embodiment of the present invention. The first and second condition determination means 1 and 2, the mixing circuit 3, and the D flip-flops 901 to 906 in FIG. 18 have the same functions as those of the first embodiment (FIG. 1). This embodiment adopts a two-stage pipeline configuration by providing five more D flip-flops 909 to 913, and positively fixes all inputs of the mixing circuit 3 when translucent synthesis is not required. By
It is a device that reduces power consumption.

In FIG. 18, reference numeral 11 denotes a first data selector, which determines an output Y from two inputs A and B according to selection control inputs S1 and S0. That is, "S
When “1 = 0 and S0 = 0” or “S1 = 0 and S0 = 1”, the input signal A is selected as the output Y, otherwise, the input signal B is selected. A fixed transparency data (for example, “00”) is input to the A input of the first data selector 11.
000000 "), the transparency data Tp from the outside synchronized with the clock signal is supplied to the B input. The output Y of the data selector 5 is supplied to the mixing circuit 3 via the D flip-flop 912.

Reference numeral 10 denotes a second data selector for determining an output Y from three inputs A, B, and C according to the selection control inputs S1 and S0. That is, S1 = 0 and S0
= 1, the input signal B is selected as the output Y when S1 = 0 and S0 = 0, and the input signal C is selected as the output Y otherwise. This second data selector 1
The pixel data Va (background) of the first moving image is input to the A input of 0 via two D flip-flops 901 and 909, and the pixel data Va (background) of
The input receives pixel data Vb (foreground) of the second moving image via two D flip-flops 902 and 910, and the output of the mixing circuit 3 is directly supplied to the C input.

Reference numeral 12 denotes second and first condition determining means 2, 1
Is a logic circuit for decoding the match signals m2 and m1. The logic circuit 12 outputs a fixed signal γ of “0” when translucent synthesis of Va and Vb is not required, that is, when Va or Vb is to be output to Vout as it is. FIG.
In the example of No. 8, the fixed signal γ is set to “0” only when the matching signals m2 and m1 of the second and first condition determination means 2 and 1 are 0, 0 or 0 and 1, respectively.

The reference numerals 13 and 14 normally pass the input 24-bit pixel data as it is and output the same, and only when the fixed signal γ of “0” is asserted from the logic circuit 12 as a control input, a predetermined value is output. This is a gate circuit having a function of outputting a 24-bit fixed value. FIG. 19 shows an example of the configuration.
Shown in Reference numeral 130 denotes a well-known AND gate, in which 24 gates having the same function are arranged. When the fixed signal γ is “1”, the input signal is passed as it is and output. When the fixed signal γ is “0”, that is, when the logic circuit 12 asserts the fixed signal γ, all the bits are set to “0”. Is output.

Next, the operation of the embodiment shown in FIG. 18 will be described. The output data Vout is the same as in the first embodiment (FIG. 1) in which the code converter 40 is set to "pass without conversion" as shown in FIG. 5A. That is, an output Vout as shown in FIG. 6 is obtained.

First, for simplicity, the D flip-flops 909 to 913 are ignored. Focusing on the inputs A, B, and T of the mixing circuit 3, from the above description,
When the translucent combination of Va and Vb is not necessary, that is, when the pixel which should output Va or Vb as it is (the area other than the "shadow" of Vout in FIG. 6), the inputs A, B, and T have predetermined values, respectively. A fixed value is supplied. That is, if pixels that do not require translucent composition continue, the logic of the mixing circuit 3 freezes during this time, making it difficult to consume power. When the present chromakey synthesizing circuit is constituted by CMOS transistors, the effect is particularly large, and the power consumption of the mixing circuit 3 becomes almost zero. Further, since the output of the mixing circuit 3 is frozen, a great deal of logic associated with the input C of the second data selector 10 is effectively frozen. In the first embodiment, the effect of reducing power consumption according to the present embodiment is considered, considering that the mixing circuit 3 having a large amount of hardware is always operated (every clock) even when translucent synthesis pixels are not required. Is big.

Next, the pipeline operation will be described. The configuration in FIG. 18 is a two-stage pipeline.
In the first clock pulse, the D flip-flop 901
The data is fetched by .about.905 and the condition is determined. In the second clock pulse, the D flip-flops 909 to 913 transmit the result of the determination to the mixing circuit 3 and the second data selector 10 to perform an operation. D
The flip-flop 906 synchronously outputs Vout to the outside. In the condition determination stage, it is determined whether or not the mixing circuit 3 is to be moved, a fixed signal γ for freezing the operation is prepared, and the next clock pulse is awaited.
The fixed signal γ arrives at the mixing circuit 3 at the arrival of the clock pulse, but if the signal is “frozen” at the immediately preceding clock pulse, the logic of the mixing circuit 3 does not change and does not consume power.

FIG. 20 is a time chart of the circuit shown in FIG. The n-th to (n + 4) -th pixel data of Vb are pixels that do not require translucent composition. It can be seen that Vout is output two clocks after the input of Va and Vb. The A, B, and T inputs of the mixing circuit 3 are "0" for 5 clocks.
And the power consumption of the mixing circuit 3 is lost for four clocks. When N pixels that do not require translucent composition are arranged in a row, the power consumption of the mixing circuit 3 is eliminated during (N-1) clocks. In general, it is extremely rare that pixels requiring translucent composition occupy the entire screen, so that the effect of reducing power consumption is large and extremely valuable.

The rules for selecting the data selectors 10 and 11 and the rules for decoding the logic circuit 12 are not limited to the present embodiment, but can be set freely according to the application. If the transparency data Tp does not frequently fluctuate, the data selector 11 may be removed and the transparency data Tp may be directly connected to the D flip-flop 912.
Between the D flip-flop 910 and the gate circuit 14,
Following the fifth embodiment (FIG. 11), it is also possible to insert a monochrome circuit and a data selector.

(Eighth Embodiment) FIG. 21 is a block diagram showing a chroma key synthesizing circuit according to an eighth embodiment of the present invention. In the present embodiment, the configuration of the seventh embodiment is modified so that two pieces of transparency data are input. The difference from FIG. 18 is that the first data selector has changed from two inputs to three inputs.

In FIG. 21, reference numeral 16 denotes a first data selector, which determines an output Y from three inputs A, B and C according to selection control inputs S1 and S0. That is,
"S1 = 0 and S0 = 1" or "S1 = 1 and S0 =
When “1”, the input signal A is selected as the output Y when S1 = 0 and S0 = 0, and the input signal C is selected as the output Y when S1 = 1 and S0 = 0. An arbitrary fixed transparency data (for example, "00000000") is input to the A input of the first data selector 16, an external first transparency data Tp1 synchronized with the clock signal is input to the B input, and a clock is input to the C input. Second transparency data Tp2 is supplied from the outside in synchronization with the signal. The output Y of the first data selector 16 is provided to the mixing circuit 3 via the D flip-flop 912.

Reference numeral 17 denotes a second data selector which determines an output Y from three inputs A, B and C according to the selection control inputs S1 and S0. That is, S1 = 0 and S0
= 1, the input signal B is selected as the output Y when S1 = 1 and S0 = 1, and the input signal C is selected as the output Y otherwise. This second data selector 1
7, the pixel data Va (background) of the first moving image is input to the A input.
However, the pixel data Vb (foreground) of the second moving image is input to the B input.
However, the output of the mixing circuit 3 is supplied to the C input.

Reference numeral 15 denotes the second and first condition determining means 2, 1
Is a logic circuit for decoding the match signals m2 and m1. The logic circuit 15 outputs a fixed signal γ of “0” when the translucent combination of Va and Vb is not required, that is, when Va or Vb is to be output to Vout as it is. FIG.
In the example of 1, the fixed signal γ is set to “0” only when the matching signals m2, m1 of the second and first condition determining means 2, 1 are 0, 1, or 1, 1.

Next, the operation of the embodiment shown in FIG. 21 will be described. Similarly to the third embodiment (FIG. 9), pixel data Va and Vb of the first and second moving images, first and second condition data Dcon1 and Dcon2, and first and second transparency data Tp1. , T
supply p2. In the "hand and arm" portion, the result of the translucent composition by the mixing circuit 3 according to the first transparency data Tp1, and in the "shadow" portion, the translucent result according to the second transparency data Tp2 by the mixing circuit 3. Since the results of the combination are reflected in the output Vout, moving image data Vout as shown in FIG. 7 in which the transparency of the "hand and arm" and the "shadow" are different from each other is obtained.

Further, similarly to the seventh embodiment (FIG. 18),
A two-stage pipeline operation is executed. In addition, when translucent synthesis is not required, the input A of the mixing circuit 3
Since B and T are all fixed, the power consumption of the mixing circuit 3 becomes almost zero.

The rules for selecting the data selectors 16 and 17 and the rules for decoding the logic circuit 15 are not limited to the present embodiment, but can be freely set according to the application. It is also possible to insert a monochrome circuit and a data selector between the D flip-flop 910 and the gate circuit 14 according to the fifth embodiment (FIG. 11).

[0064]

As described above, according to the present invention, a plurality of condition judging means for judging a color range of pixel data are provided, and when a background moving image is pointed to a foreground moving image, Some areas of the foreground video (for example,
Since a configuration in which only the “shadow” or both “the hand and the arm” and the “shadow” are translucently combined with the moving image of the background is adopted, it is possible to realize the pointing without covering the background with the foreground. The foreground “hand and arm” and “shadow” can be translucently combined with the background moving image with different degrees of transparency. Further, by selectively converting a partial area of the foreground video to black and white (gray), the original black and white (gray) “shadow” that is not mixed with unrelated colors can be dropped into the background video, More natural pointing and effective presentations are possible. Therefore, the present invention exerts extremely excellent value for applications such as multimedia computers and presentation systems that use video moving images as communication means.

[Brief description of the drawings]

FIG. 1 is a block diagram of a chroma key synthesizing circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration example of two comparators in FIG.

FIG. 3 is a circuit diagram illustrating a configuration example of a mixing circuit in FIG. 1;

FIG. 4 is a circuit diagram illustrating a configuration example of a code converter in FIG. 1;

5A to 5C are diagrams showing three setting examples of a conversion table of the code converter of FIG.

FIG. 6 shows the chroma key synthesizing circuit shown in FIG.
FIG. 10 is a diagram showing an operation when the conversion table of FIG.

FIG. 7 shows the chroma key synthesizing circuit shown in FIG.
FIG. 10 is a diagram showing an operation when the conversion table of FIG.

FIG. 8 is a block diagram of a chroma key synthesizing circuit according to a second embodiment of the present invention.

FIG. 9 is a block diagram of a chroma key combining circuit according to a third embodiment of the present invention.

FIG. 10 is a block diagram of a chroma key combining circuit according to a fourth embodiment of the present invention.

FIG. 11 is a block diagram of a chroma key synthesizing circuit according to a fifth embodiment of the present invention.

12 is a circuit diagram illustrating a configuration example of a black and white conversion circuit in FIG. 11;

FIG. 13 is a circuit diagram showing a configuration example of a code converter in FIG. 11;

14 is a diagram illustrating a setting example of a conversion table of the code converter in FIG. 13;

FIG. 15 is a block diagram of a chroma key combining circuit according to a sixth embodiment of the present invention.

FIG. 16 is a circuit diagram showing a configuration example of a code converter in FIG.

17 is a diagram showing a setting example of a conversion table of the code converter of FIG.

FIG. 18 is a block diagram of a chroma key combining circuit according to a seventh embodiment of the present invention.

FIG. 19 is a circuit diagram showing a configuration example of two gate circuits in FIG. 18;

FIG. 20 is a time chart showing the operation of the chroma key synthesizing circuit of FIG. 18;

FIG. 21 is a block diagram of a chroma key synthesis circuit according to an eighth embodiment of the present invention.

FIG. 22 is a block diagram illustrating a configuration of a conventional chromakey synthesis circuit.

FIG. 23 is a diagram illustrating the operation of the chroma key synthesizing circuit of FIG. 22;

[Explanation of symbols]

1, 2 Condition determining means 3, 6, 7 Mixing circuit 4, 5, 8-11, 16, 17, 31, 32 Data selector 12, 15 Logic circuit 13, 14 Gate circuit 21, 22 Comparator 30 Monochrome circuit 40 , 41, 42 Code converters 130, 206-209 AND gates 200-205 Magnitude comparators 301, 302, 304, 305, 307, 308 Multiplication circuits 303, 306, 309, 334 Addition circuits 310 Complement conversion circuits 331-333 Coefficient circuits 401, 411, 412, 421, 422, 901-9
13D flip-flop 402, 403, 413-416, 423-425 Data selector

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H04N 9/75 H04N 5/275

Claims (13)

(57) [Claims] 1. A chroma key synthesizing circuit for generating a synthetic moving image of a first moving image and a second moving image in real time with a first moving image as a background, wherein a pixel data of the first moving image and First means for inputting pixel data of a second moving image in synchronization with a clock signal; and first means for indicating whether the input pixel data of the second moving image satisfies a first condition. And a second means for generating a second binary signal indicating whether or not the input pixel data of the second moving image satisfies a second condition. And pixel data of the input first moving image so as to achieve completely transparent composition, opaque composition and translucent composition in accordance with the code composed of the first and second binary signals. And the input pixel data of the second moving image, and the input Fourth means for selectively outputting one of pixel data obtained by weighted addition of pixel data of the first and second moving images, and pixel data output from the fourth means And synthesizing the moving image as pixel data of the synthesized moving image in synchronism with the clock signal. 2. The chroma key synthesizing circuit according to claim 1, wherein the data indicating the first and second conditions in the second and third means respectively designate a color range of pixel data. A chroma key synthesizing circuit, further comprising means for externally inputting the above condition data. 3. The chroma key synthesizing circuit according to claim 1, wherein said fourth means externally inputs transparency data specifying a weight distribution for weighted addition of pixel data of the first and second moving images. A chroma key synthesizing circuit, further comprising: 4. The chroma key synthesizing circuit according to claim 1, wherein said chroma key synthesizing circuit comprises said first and second binary signals interposed between said second and third means and said fourth means. A chroma key synthesizing circuit, further comprising means for converting the converted code according to a variable setting rule. 5. The chroma key synthesizing circuit according to claim 1, wherein said fourth means weights and adds the input pixel data of the first and second moving images with a weight distribution according to given transparency data. A mixing means for outputting the pixel data obtained by the weighted addition, and achieving a completely transparent composition, an opaque composition and a semi-transparent composition according to a code composed of the first and second binary signals. To selectively select one of the input pixel data of the first moving image, the input pixel data of the second moving image, and the pixel data output from the mixing unit. A chroma key synthesizing circuit, comprising: selecting means for supplying to the fifth means. 6. The chroma key synthesizing circuit according to claim 5, wherein the mixing unit removes a color component from the input pixel data of the second moving image, and outputs black and white pixel data obtained by removing the color component. A black-and-white conversion circuit for outputting the pixel data of the input second moving image or the black-and-white pixel data according to a code composed of the first and second binary signals. A data selector for selectively outputting the pixel data of the first moving image and the pixel data output from the data selector by weighted addition in a weight distribution according to the given transparency data. And a mixing circuit for supplying the pixel data obtained by the weighted addition to the selecting means. 7. The chroma key synthesizing circuit according to claim 5, wherein said mixing means weights said input first and second moving image pixel data by weight distribution according to given first transparency data. A first mixing circuit for adding the pixel data obtained by the weighted addition to the selection means; removing a color component from the input second moving image pixel data; A black-and-white conversion circuit for outputting black-and-white pixel data obtained by the removal; and a weight distribution according to the second transparency data given the input first moving-image pixel data and the black-and-white pixel data. And a second mixing circuit for performing weighted addition and supplying the pixel data obtained by the weighted addition to the selection means. 8. The chroma key synthesizing circuit according to claim 5, wherein the selection unit selects one of the input pixel data of the first moving image and the input pixel data of the second moving image. And a means for stopping the weighted addition operation of the mixing means in the case where the mixing is performed. 9. The chroma key synthesizing circuit according to claim 1, wherein said fourth means is configured to perform a first transparent corresponding to a completely transparent synthesis according to a code constituted by said first and second binary signals. Fixed transparency data, second fixed transparency data corresponding to opaque composition,
Selection means for selectively outputting one of transparency data corresponding to translucent composition; and transparency data output from the selection means, based on the input pixel data of the first and second moving images. And a mixing means for supplying the pixel data obtained by the weighted addition to the fifth means. 10. The chroma key synthesizing circuit according to claim 9, wherein said mixing means removes a color component from the input pixel data of the second moving image, and outputs black and white pixel data obtained by removing the color component. A black-and-white conversion circuit for outputting the pixel data of the input second moving image or the black-and-white pixel data according to a code composed of the first and second binary signals. A data selector for selectively outputting the pixel data of the first moving image and the pixel data output from the data selector according to the transparency data output from the selection means. And a mixing circuit for supplying the pixel data obtained by the weighted addition to the fifth means. 11. A chromakey synthesis circuit having a pipeline configuration for generating a synthesized moving image of the first moving image and the second moving image in real time with a first moving image as a background, A first D flip-flop for holding and outputting pixel data in synchronization with a clock signal; and a second D flip-flop for holding and outputting pixel data of the second moving image in synchronization with the clock signal. 2 D flip-flops, and holds the pixel data of the first moving image output from the first D flip-flop in synchronization with the clock signal;
And a third D flip-flop for outputting, and holding the pixel data of the second moving image output from the second D flip-flop in synchronization with the clock signal,
And a fourth D flip-flop for outputting, and a first indicating whether or not the pixel data of the second moving image output from the second D flip-flop satisfies a condition indicated by the first condition data. For generating a binary signal of
And a second binary signal indicating whether pixel data of a second moving image output from the second D flip-flop satisfies a condition indicated by second condition data. Second
And a fixed signal that is asserted in the case of a pixel that does not require translucent synthesis according to the code composed of the first and second binary signals, A logic circuit for outputting a fixed signal that is not asserted in each case, a fifth D flip-flop for holding and outputting given transparency data in synchronization with the clock signal, A sixth D flip-flop for holding and outputting a fixed signal output from a logic circuit in synchronization with the clock signal, and a code composed of the first and second binary signals; A seventh D flip-flop for holding and outputting in synchronization with a clock signal; and a seventh D flip-flop for outputting a non-asserted fixed signal from the sixth D flip-flop. The pixel data of the first moving image output from the D flip-flop is output as it is, and when the fixed signal asserted from the sixth D flip-flop is output, the pixel data of the first moving image is output. A first gate circuit for outputting alternate fixed pixel data; and a fourth gate output from the fourth D flip-flop when a non-asserted fixed signal is output from the sixth D flip-flop. 2 for outputting the pixel data of the moving image as it is and outputting fixed pixel data in place of the pixel data of the second moving image when the asserted fixed signal is output from the sixth D flip-flop. A second gate circuit, and the pixel data output from the first gate circuit and the pixel data output from the second gate circuit are connected to the fifth D-free circuit. A mixing circuit for performing weighted addition by weight distribution according to the transparency data output from the flip-flop and outputting pixel data obtained by the weighted addition, and a mixing circuit for outputting pixel data obtained from the seventh D flip-flop. The first moving image pixel data output from the third D flip-flop and the second moving image pixel data output from the fourth D flip-flop are output so as to achieve completely transparent synthesis, opaque synthesis, and translucent synthesis. A data selector for selectively outputting one of pixel data of a moving image and pixel data output from the mixing circuit; and synchronizing the pixel data output from the data selector with the clock signal. An eighth D flip-flop for holding and outputting as pixel data of the composite moving image, wherein the data selector comprises: If the code output from the seventh D flip-flop is a code that outputs the fixed signal asserted from the logic circuit, the pixel of the first moving image output from the third D flip-flop Fixed between the data and the pixel data of the second moving image output from the fourth D flip-flop, wherein the code output from the seventh D flip-flop is not asserted from the logic circuit. A chroma key synthesizing circuit having a function of selecting each of the pixel data output from the mixing circuit when the code is a code for outputting a coded signal. 12. The chroma key synthesizing circuit according to claim 11, wherein the code composed of the first and second binary signals is a code that outputs a fixed signal that is not asserted from the logic circuit. Outputs at least one variable transparency data supplied in synchronization with the clock signal, and a fixed signal in which a code composed of the first and second binary signals is asserted from the logic circuit. A chroma key synthesizing circuit, further comprising a data selector for supplying fixed transparency data in place of the variable transparency data to the fifth D flip-flop when the code is a code. 13. The chroma key synthesizing circuit according to claim 11, wherein a color component is removed from the pixel data of the second moving image output from the fourth D flip-flop, and the black and white obtained by removing the color component. A black-and-white conversion circuit for outputting pixel data; and a second moving image pixel data output from the fourth D flip-flop and the black-and-white conversion in accordance with a code output from the seventh D flip-flop. A chroma selector for selectively supplying one of black-and-white pixel data outputted from the circuit to the second gate circuit.