JP2989879B2 - Line controller - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a line controller, and more particularly, to a priority control method for an interrupt from a line controller and a bus interface controller.

[Conventional technology]

In this type of conventional line controller, data transmitted from a higher-level device is stored in a buffer memory connected to an internal bus for transmission to a line, and received data stored in a buffer memory is received for reception from a line. The bus interface controller issues a bus request interrupt to the MPU in order to transfer the Further, the line control unit issues an interrupt to transmit the data in the buffer memory to the line and to store the data received from the line in the buffer memory. The MPU that has received the interrupt gives the right to use the bus to each control unit and causes the data to be transferred. In this case, the priority order is determined by the number of interrupt signal input pins provided in advance in the MPU. In a normal line controller, a line controller is connected to a high-priority input pin in order to prevent overrun / underrun of the line.

[Problems to be solved by the invention]

The priority control of the conventional line controller described above is determined by the input pin of the MPU to which the interrupt signal line is connected, and always gives priority to the line control unit, so when the number of interrupts from the line increases, the bus use right is controlled by the line. The bus interface controller is interrupted, the bus interface controller becomes inoperable, data is not taken over to the host device, and an overrun / underrun occurs.

[Means for solving the problem]

The present invention provides an MPU for controlling the whole, a bus interface control means for performing data transfer between an upper-level device and a buffer memory provided in advance via an internal bus, and A line control unit that performs data transfer via an internal bus, and an interrupt for the internal bus use request from the bus interface control unit or the line control unit, which is received at separate reception ports, and is usually a predetermined reception port. In a line control device comprising interrupt control means for performing an interrupt process to the MPU in priority order, the interrupt control means may receive the bus interface control means or the line control means received at the separate reception port from the MPU. If the number of interrupt requests waiting for interrupt processing reaches a predetermined number, Characterized in that it comprises means for the interrupt processing to preferentially the MPU for serial interrupt request.

〔Example〕

FIG. 1 is a block diagram of one embodiment of the present invention. 1 is an MPU running by a microprogram, 2 is a buffer memory, 3 is a bus interface control unit that performs data transfer with a higher-level device, 4 is a line control unit that controls transmission and reception to and from a line, and 5 is a priority control of interrupts internally. An interrupt control unit having a function, 6 is a common internal bus in the line controller, and 7 is a system bus having an interface with a higher-level device.

Next, the operation of this embodiment will be described. When transmitting data to the line, the bus interface control unit 3 receives the data from the system bus 7 and transfers the data to the buffer memory 2.
Generate an interrupt to MPU1. The interrupted MPU 1 returns the right to use the bus to the bus interface control unit 3, and the bus interface control unit 3 having secured the bus stores the transmission data in the buffer memory 2 by DMA transfer. And issue a termination interrupt. The MPU 1 that has received the end interrupt activates the line control unit 4. The activated line control unit 4 issues a bus request to the MPU 1 and, when the right to use the bus is obtained, transfers the transmission data from the buffer memory 2 to the DMA.
Received by transfer and output on line.

At the time of reception, the operation is reverse to that described above. In addition, the interrupt signal of the bus request on the line control unit side is applied to the L1 pin of the MPU1 and the interrupt signal of the bus request on the bus interface control unit side is output to the LPU pin of the MPU1.
Connected to L2 pin. In the MPU 1, priority control is performed in the order of L1> L2, and the line control unit 4 has priority. When there is a bus request interrupt from both the line controller 4 and the bus interface controller 3, the interrupt of the bus interface controller 3 is suspended. When the multiplicity of transmission / reception on the line increases, an interrupt signal of a bus request for reception from the line control unit 4 frequently occurs and the number of times of storing the received data in the buffer memory increases, while the MPU 1 controls the bus interface control unit 3 Is activated to transfer the received data stored in the buffer memory to the higher-level device, but the interrupt from the bus interface control unit 3 has a lower priority than the interrupt from the line control unit 4 and is often suspended. Become.
The interrupt control unit 5 changes the priority control in the interrupt control circuit unit 5 when the number of interrupt signals from the bus interface control unit 3 for the activation to the bus interface control unit 3 reaches a predetermined number. In this way, the bus interface controller is given priority to use the bus by allowing the interrupt of the bus interface controller 3 to be accepted by the microprogram of the MPU 1 so that the received data in the buffer memory can be transferred to the host device. When the DMA transfer from the bus interface control unit 3 is completed, the MPU 1 returns the priority order and accepts an interrupt from the line control unit 4 again. When the number of interrupts held by the line controller 4 reaches a certain value, the priority is temporarily changed to accept the interrupt and perform data transmission and reception.

〔The invention's effect〕

As described above, according to the present invention, when the number of pending interrupts in the interrupt control unit 5 reaches a predetermined value, the priority is temporarily changed and the interrupt is accepted, so that the data in the buffer memory 2 at the time of reception is changed. Is not obtained, and there is an effect of preventing an overrun / underrun that transmission data does not exist in the buffer memory 2 at the time of transmission.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. 1 ... MPU, 2 ... Buffer memory, 3 ... Bus interface controller, 4 ... Line controller, 5 ... Interrupt controller, 6 ... Internal bus, 7 ... System bus

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G06F 13/00

Claims (1)

(57) [Claims] An MPU for controlling the whole; a bus interface control means for performing data transfer between an upper-level device and a buffer memory provided in advance via an internal bus; A line control unit for performing data transfer via the internal bus, and an interrupt for the internal bus use request from the bus interface control unit or the line control unit which is received at a separate reception port, and the reception port usually determined in advance. A line control device comprising interrupt control means for performing an interrupt process to the MPU in the priority order, wherein the interrupt control means receives the MPU from the bus interface control means or the line control means received at the separate reception port. If the number of interrupt requests waiting for interrupt processing reaches the predetermined number, Line control apparatus characterized by comprising means for the interrupt processing to preferentially the MPU for the interrupt request.