JP2989696B2 - Semiconductor device and mounting method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of mounting the same, and more particularly, to a flip-chip type semiconductor device and a method of mounting the same.

[0002]

2. Description of the Related Art The structure and manufacturing method of a semiconductor device used in a conventional flip-chip type assembly are described in, for example, Japanese Patent Application Laid-Open No. 1-187948.
Hereinafter, a method for manufacturing the conventional flip-chip type semiconductor device will be described with reference to FIG.

In the figure, 1 is a semiconductor chip, 2 is an insulating film, 3
Is a metallized layer, 4 is a barrier metal layer, 5 is a polyimide layer,
Reference numeral 6 denotes an opening, 7 denotes a columnar electrode layer, and 8 denotes a solder bump.

In FIG. 8A, a metallized layer 3 is formed on a surface of a semiconductor chip 1 on which an active area is formed. Next, after the insulating film 2 is formed on the entire surface, the insulating film 2 on the metallized layer 3 is selectively removed.

[0005] Next, a metal having good adhesion to the metallized layer 3 and not causing deterioration due to diffusion between the metals is deposited on the entire surface of the semiconductor chip 1 including the metallized layer 3 by a sputtering method or metal vapor deposition. The barrier metal layer 4 is formed by a method. The barrier metal layer 4 has a two-layer structure by first depositing titanium or chromium on the metallized layer 3 and depositing copper or nickel thereon. The titanium or chromium thin film layer is usually formed with a thickness of about 0.05 to 0.1 μm in consideration of a subsequent etching step of the barrier metal layer 4.

In FIG. 8B, a polyimide layer 5 is applied on the entire surface of the barrier metal layer 4 to a thickness of 30 to 50 μm and cured. In FIG. 8C, the region of the polyimide layer 5 on the metallized layer 3 is selectively removed by a reactive ion etching method using oxygen or a mixed gas of carbon tetrafluoride and oxygen to form an opening 6. .

In FIG. 8D, a columnar electrode layer 7 is formed by filling the opening 6 with a metal having good wettability with solder, such as nickel or copper, by an electrolytic plating method. Next, a solder bump 8 is formed on the columnar electrode layer 7 in an umbrella shape by an electrolytic plating method or a dipping method. As the solder, for example, a solder having 95% lead and 5% tin is used.

In FIG. 8E, dry etching is performed by using the umbrella-shaped solder bumps 8 as a mask.
The polyimide layer 5 in a region other than the solder bumps 8 is removed to leave the polyimide layer 5 on the side surface of the columnar electrode layer 7.

In FIG. 8F, the portion of the barrier metal layer 4 other than the region located under the solder bump 8 is removed by wet etching. As described above, when the columnar electrode layer 7 is formed by the electrolytic plating method, since the polyimide layer 5 is provided, the plating layer can be formed high while suppressing the lateral spread. Height can be increased. In addition, since the solder bumps 8 are formed on the columnar electrode layers 7 covered with the polyimide layer 5, the solder bumps 8 with less variation can be obtained without the solder wrapping around the side surfaces of the columnar electrode layers 7. .

Next, the flip chip method for assembling the semiconductor chip 1 on the circuit board 9 will be described. FIG.
FIG. 3 is a side view showing a state where the semiconductor chip 1 is connected to a circuit board 9.

Conventionally, a device such as a flip chip bonder is used for positioning and assembling a semiconductor chip and a substrate. First, the solder bumps 8 of the semiconductor chip 1 are attached to the electrode pads of the circuit board 9 on a circuit board 9 having electrode pads (not shown) provided at positions corresponding to the solder bumps 8 of the semiconductor chip 1 by a bonder. The semiconductor chip 1 is mounted on the circuit board 9 by abutting and positioning. At this time, the solder bumps 8 are re-melted by applying appropriate pressure and heating, and the semiconductor chip 1 and the circuit board 9 are connected by forming the connection body 10.

Thus, a flip-chip type semiconductor device is formed.

[0013]

However, the bumps in the conventional flip-chip type semiconductor device as described above are formed by re-melting the solder bumps 8 to form the connection body 10 so that the semiconductor chip 1 becomes a circuit. Connected to substrate 9. That is, in order to make a connection, pressure and heat must be applied to both to form a eutectic alloy of solder. Since there is a difference in the coefficient of thermal expansion between the two, the heat generated by these electronic components after the connection between the semiconductor chip 1 and the circuit board 9 and the change in the environmental temperature surrounding them cause a repeated shear stress at the joint (bump). Occurs, and there is a risk of joint breakage due to metal fatigue. Increasing the height of the bumps can prevent breakage due to thermal cycling to some extent, but does not eliminate the possibility of breakage.

When it is determined that the connection between the semiconductor chip 1 and the circuit board 9 is defective, the semiconductor chip 1 is separated from the circuit board 9 once, and then the semiconductor chip 1 and the circuit board 9 are separated again. In the case of connection, the semiconductor chip 1 and the circuit board 9 must be disassembled by melting the eutectic alloy of the solder, and in order to perform bonding again, the solder adhered to the electrode pads on the circuit board 9 must be disassembled. There is a problem that cleaning must be performed in order to remove.

As described above, conventionally, there has been no flip-chip type semiconductor device having a structure in which a bump electrode is hardly broken due to a difference in thermal expansion coefficient between a semiconductor chip and a circuit board and repair is easy.

According to the present invention, the bump electrodes are less likely to break due to the difference in the thermal expansion coefficient between the semiconductor chip and the circuit board.
It is another object of the present invention to provide a flip-chip type semiconductor device having a structure that can be easily repaired.

[0017]

The above problems can be solved by the following semiconductor device. FIG. 1 shows a side view of a main part of a flip-chip type semiconductor device of the present invention in which a first substrate having bumps and a second substrate having electrode pads are connected. That is, in the semiconductor device according to the present invention, as shown in FIG. 1A, a plurality of projecting insulators are formed on a substrate, and at least one of the insulators has a through hole in the center. A bump formed by filling the through-hole with a columnar metal body is provided as an external connection terminal, and between the insulator and the insulator,
A first substrate (11) on which at least one electrode pad is formed and a second substrate (11 ') are provided on a plurality of first insulators (16) provided on the first substrate (11). )
And a plurality of second insulators (16 ') provided on the second substrate (11') are alternately meshed with each other and pressed at room temperature to be integrally formed. The upper bump is electrically connected to the electrode pad (12a ') provided at a corresponding position on the other substrate.

Alternatively, as shown in FIG. 1B, a first substrate (21) in which only the bumps are formed at predetermined intervals.
When the surfaces of the second substrate (26), in which only the electrode pads (27) and the second insulator (28) are alternately formed, face each other, the first substrate (21) The upper bump is electrically connected to the electrode pad (27) provided at a corresponding position on the second substrate (26).

Further, as shown in FIGS. 5B and 5D, the method of repairing the semiconductor device includes a method of repairing the bumps on the first substrate (11) and the electrode pads (1) on the second substrate (11 ').
2a '), a test for electrical continuity is performed, and as a result, if it is determined that the bonding is defective, the first substrate (11) is pulled up with an appropriate force without heating, and the first substrate (11) is pulled up. The substrate (11) is separated from the second substrate (11 ′). Next, after repairing, a plurality of the first insulators (16) provided on the first substrate (11) and a plurality of the first insulators provided on the second substrate (11 ') again. The bumps and the electrode pads (12a ') are electrically connected by engaging and pressing the two insulators (16').

[0020]

According to the present invention, the following operation is obtained from the configuration shown in FIG. (1) Since the resin and the resin are formed so as to mesh with each other when the surfaces of the substrate and the surface of the substrate face each other, the connection of the two substrates does not require heating, and only pressurization is required. Easy connection. Therefore, the connection between the bump and the electrode pad is in a contact state, unlike the physical connection using the eutectic reaction of solder or the like. In addition, since the space between the bump and the pump is fixed by the contact of the highly flexible polyimide resin insulating layer, mismatching of the coefficient of thermal expansion between the two substrates can be reduced, and damage to the joint can be considerably reduced. .

(2) In the case of repairing due to poor bonding or the like, it is only necessary to lift the substrate upward with an appropriate force. Further, cleaning is very simple since cleaning after repair is unnecessary.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Two embodiments of the present invention will be specifically described below with reference to the drawings. A first embodiment of the present invention is:
This is shown in FIGS. 2, 3, 4, 5, and 1-a.

First, a method for manufacturing a substrate having bump electrodes and electrode pads will be described with reference to FIGS. In FIG. 2A, a thickness of 1.0 to 1.5 .mu.
An aluminum layer of about m is formed. Next, a photoresist (not shown) is applied to the entire surface, a photoresist pattern is formed using a photolithographic method, and the aluminum layer other than the region where the metallized layer 12 is formed is etched using the photoresist as a mask. Removed and metallized layer 12
To form Next, after removing the resist mask, CVD
An SiO ₂ film 13 serving as an insulating film having a thickness of 4 μm is formed on the entire surface by the CVD method (chemical vapor deposition method), and a metal resist layer 12 is formed on the metallized layer 12 by a patterned resist mask (not shown).
The iO ₂ film 13 is selectively removed. After that, the resist mask is removed.

In FIG. 2B, a chromium layer, a copper layer, and a nickel layer are sequentially formed on the entire surface by a vapor deposition method. These layers are collectively referred to as a barrier metal layer 14. The thickness of the barrier metal layer 14 is 3 μm. Next, a photoresist 1 is formed on the entire surface.
5 is applied, and a pattern of a photoresist 15 is formed by a photolithographic method.

In FIG. 2C, after the barrier metal layer 14 other than on the metallized layer 12 is removed by wet etching using the photoresist 15 as a mask, the resist mask 15 is removed.

In FIG. 2D, a photosensitive polyimide having a thickness of more than 10 μm is coated on the entire surface, and a polyimide resin having a through hole for filling a columnar metal layer at the center on the metallized layer 12 by photolithography. An insulating layer 16 is formed. In some cases, the formation of the polyimide resin insulating layer 16 may be repeated depending on the required thickness.

In FIG. 3A, a chromium layer, a copper layer, and a nickel layer are sequentially formed on the entire surface by a vapor deposition method. These layers are collectively referred to as a barrier metal layer 17. The thickness of the barrier metal layer 17 is 3 μm. Next, a photoresist 1 is formed on the entire surface.
8 is applied, and a pattern of a photoresist 18 is formed by photolithography so that only a through hole inside the polyimide resin insulating layer 16 is formed.

In FIG. 3B, a metal having good thermal or electrical conductivity, such as copper, nickel or gold, is placed inside the through hole by electroplating at 3 to 10 μm from the upper end of the polyimide resin insulating layer 16. The columnar metal layer 19 is formed so as to fill up to a certain degree. Next, the photoresist 18 is removed.

In FIG. 3C, a photoresist 20 is applied to the entire surface, and a pattern of the photoresist 20 is formed by a photolithographic method. In FIG. 3D, after the barrier metal layer 17 other than on the metallized layer 12 and around the columnar electrode layer 19 is removed by wet etching using the photoresist 20 as a mask, the resist mask 20 is removed. Thus, the bump composed of the polyimide resin insulating layer 16 and the columnar metal layer 19 and the electrode pads 12 composed of the metallization layer 12 and the barrier metal layers 14 and 17 on the left and right sides thereof.
a is formed.

With the above, the manufacturing process of the bump electrode is completed.
Next, a method of assembling the semiconductor device will be described. Fig. 4-
FIG. 3A is a plan view of the Si substrate 11 in the first embodiment created in the steps of FIGS. 2 and 3 of the present invention.

FIG. 4B is a cross-sectional view of the Si substrate 11 according to the first embodiment of the present invention, and is a cross-sectional view taken along line AA of FIG. 4-A. As is apparent from FIG. 4, the bump is formed by the metallized layer 12 and the barrier metal layer 1 formed thereon.
4, 17; a columnar metal layer 19 formed thereon; and a polyimide resin insulating layer 16 formed on the side surface of the columnar metal layer 19 such that the upper end is lower than the upper end of the columnar metal layer 19; The bumps are formed in a line at a predetermined interval. Further, between the bumps, the metallized layer 12 and the barrier metal layers 14 and 17 when the bumps are formed are formed.
Are left, and these become the electrode pads 12a.

FIG. 1A shows an Si substrate 1 as shown in FIG.
FIG. 3 is a cross-sectional view when the surfaces 1 and the surface of a Si substrate 11 ′ are faced to each other and connected. As for the connection method, the bumps are aligned in the same manner as in the conventional flip chip method, and the bump-like polyimide 16 on the Si substrate 11 is
The projecting polyimide 16 'of the i-substrate 11' is engaged with the two substrates and pressurized under appropriate pressure conditions to connect the two substrates. The pressure is desirably 10 to 50 g per bump depending on the bump size.

FIG. 5A is a perspective plan view showing an example of the layout of bumps and electrode pads of the flip-chip type semiconductor device according to the first embodiment of the present invention. Indicate the electrode pad 12a. The bumps and the electrode pads 12a are alternately arranged on the periphery of the Si substrate 11. On the other hand, as shown in FIG. 5B, which is a cross-sectional view taken along the line BB of FIG. 5A, electrode pads 12a 'are arranged on the Si substrate 11' at positions corresponding to the positions where the bumps are arranged on the Si substrate 11. Bumps are arranged at positions corresponding to the positions where the electrode pads 12a are arranged on the Si substrate 11.

Then, as shown in FIG. 5B, the bumps on the Si substrate 11 and the electrode pads 12a 'on the Si substrate 11'
The connection between the two substrates is performed by pushing down the Si substrate 11 with an appropriate force without heating the electrode pads 12a of the i substrate 11 and the bumps of the Si substrate 11 '.

FIG. 5C is a perspective plan view showing another example of the layout of the bumps and electrode pads of the flip-chip type semiconductor device according to the first embodiment of the present invention.
The bumps and the electrode pads 12a are provided on the surface of the i-substrate 11, and the bumps and the electrode pads 12a are arranged in a specific area on the Si substrate 11 in a dice pattern. Also, FIG.
As is clear from FIG.
An electrode pad 12a 'is arranged at a position corresponding to the position where the bump of the Si substrate 11 is arranged on the i substrate 11', and a bump of the Si substrate 11 'is arranged at a position corresponding to the position where the electrode pad 12a is arranged. ing.

While an example of the layout of bumps and electrode pads has been described above, the present invention is not limited to this example. For example, the arrangement of bumps and electrode pads in FIG. The arrangement of the pumps and the electrode pads may be different.

Next, a second embodiment of the present invention is shown in FIG. 6 and FIG. 1-b. 6A, a titanium layer, a molybdenum layer, a nickel layer, and a copper layer are sequentially formed on the entire surface of a ceramic substrate 21 by a sputtering method. These layers are collectively referred to as a barrier metal layer 22. Barrier metal layer 2
The thickness of 2 is 5 μm. Next, a photoresist 23 is applied on the entire surface, and a pattern of the photoresist 23 is formed by a photolithographic method.

In FIG. 6B, using the photoresist 23 as a mask, the barrier metal layer 22 other than the region where the columnar metal layer is to be formed is removed by wet etching. In some cases, heat treatment is performed in a reducing atmosphere at 750 ° C. or higher in order to increase the adhesion between the ceramic substrate 21 and the barrier metal layer 22.

In FIG. 6C, a photosensitive polyimide of 30 μm is applied on the entire surface, and a polyimide resin insulating layer 24 having a through hole for filling the columnar metal layer at the center thereof is formed on the barrier metal layer 22.

In FIG. 6-d, a metal having good thermal conductivity or good electrical conductivity such as copper, nickel or gold is electroplated inside the through hole 3 to 10 μm from the upper end of the polyimide resin insulating layer 24. The columnar metal layer 25 is formed by filling so as to swell to the extent. As a result, a bump including the barrier metal layer 22, the polyimide 24, and the columnar metal layer 25 is formed on the ceramic substrate 21.

FIG. 1B is a sectional view of a semiconductor device according to a second embodiment of the present invention. This is because, as shown in FIG. 6, one substrate has a columnar metal layer 25 on a barrier metal layer 22 and a columnar metal layer 25
Is a ceramic substrate 21 having only a bump composed of a polyimide resin insulating layer 24 formed so as to be lower than the upper end of the metallized layer 27 serving as an electrode pad and a polyimide resin insulating layer 28. It is a substrate 26 having only blocks alternately. Then, the ceramic substrate 21 and the substrate 26 are integrated by engaging the polyimide resin insulating layer, thereby electrically connecting the bumps and the electrode pads.

FIG. 7 is a sectional view of a semiconductor device according to a third embodiment of the present invention. This is a modification of the first embodiment.
One electrode pad 42 is disposed, and a bump of the substrate 41 is disposed at a position where the electrode pad 32 of the substrate 31 is disposed.
Further, by forming a projection-like polyimide serving as a dummy on each of the substrate 31 and the substrate 41, the substrate 31 is formed.
And the resin 33 of the substrate 41 are alternately meshed with each other.

As described above, in the present embodiment, in connecting the bumps and the electrode pads, the resin of both substrates is engaged with each other without utilizing the eutectic reaction of solder or the like.
The bump and the electrode pad are brought into contact. That is, the connection between the two substrates only requires pressurization, which can reduce the mismatch in the coefficient of thermal expansion between the substrates and can significantly reduce the damage to the bumps.

In the embodiment, chromium,
Although copper, nickel, or the like is used, any material may be used in consideration of the adhesion between the substrate and the metal, the metal and the insulator, and the conductivity of the metal, and any number of layers may be used according to the purpose. The substrate may be anything such as a Si substrate, a ceramic substrate, or a glass substrate. Further, in the first embodiment, bumps are formed on both substrates, and in the second embodiment, only one substrate has
Bumps were formed. Thus, either substrate may have bumps or electrode pads. In other words, it is only required that when the two substrates face each other, the resin and the resin formed on both substrates are engaged with each other.

Next, a method of repairing a flip-chip type semiconductor device according to the present invention will be described with reference to FIG. In general, after bonding the bump electrodes and the electrode pads of the two substrates, a continuity test is performed to confirm whether the bump electrodes and the electrode pads are electrically sufficiently bonded. As a result of the continuity test, when it is determined that the continuity is defective, repair is performed by the following method. That is, the two substrates that have been once engaged and integrated are separated. At this time, it is sufficient to physically separate them, and it is unnecessary to apply heat. Next, the two substrates are engaged again to be integrally formed, and the bumps and the electrode pads are connected again.
Again, no heating is required.

As described above, since the repair in the present invention does not require heating, the repair can be performed very easily.

[0047]

As described above, according to the present invention, 2
The bumps and the electrode pads can be connected by contacting the resin of the two substrates with the resin. That is,
Breakage hardly occurs due to a difference in thermal expansion coefficient from the circuit board. In addition, a semiconductor device that does not require cleaning after repair can be manufactured, which greatly contributes to higher performance and higher density of a semiconductor integrated circuit.

[Brief description of the drawings]

FIG. 1A is a principle diagram for explaining a first embodiment of the present invention, and FIG. 1B is a principle diagram for explaining a second embodiment of the present invention.

FIGS. 2A to 2D are process cross-sectional views illustrating a first embodiment of the present invention.

FIGS. 3A to 3D are process cross-sectional views illustrating a first embodiment of the present invention.

FIG. 4A is a plan view of a substrate according to the first embodiment of the present invention, and FIG. 4B is a cross-sectional view of the substrate according to the first embodiment of the present invention.

FIGS. 5A and 5C are plan views of the semiconductor device according to the first embodiment of the present invention, and FIGS. 5B and 5D are cross-sectional views of the semiconductor device according to the first embodiment of the present invention. is there.

FIGS. 6A to 6D are process sectional views illustrating a second embodiment of the present invention.

FIG. 7 is a cross-sectional view between substrates according to a third embodiment of the present invention.

FIGS. 8A to 8F are process cross-sectional views illustrating a conventional method of manufacturing a bump structure.

FIG. 9 is a cross-sectional view of a conventional semiconductor device.

[Explanation of symbols]

Reference Signs List 13 SiO ₂ film serving as insulating film 16 Polyimide resin serving as insulating layer 19 Columnar metal layer serving as bump electrode 22 Barrier metal layer serving as electrode pad 24 Polyimide resin serving as insulating layer 25 Columnar metal layer serving as bump electrode 27 Electrode pad Metallized layer 28 polyimide resin to be an insulating layer 34 columnar metal layer to be a bump electrode 44 columnar metal layer to be a bump electrode

Continuation of the front page (56) References JP-A-2-28932 (JP, A) JP-A-1-187948 (JP, A) JP-A-4-94131 (JP, A) JP-A-57-95640 (JP) , A) (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 21/60

Claims (5)

(57) [Claims] 1. A plurality of projecting insulators are formed on a substrate, and at least one of the insulators has a through hole at a center portion, and the through hole is filled with a conductor. Is provided as an external connection terminal, and the insulator
And at least one electrode pad between the
A semiconductor device provided as an external connection terminal . 2. A first substrate (11) and a second substrate (11 '), on each of which a plurality of projecting insulators are formed, are provided.
A plurality of first insulators (16) provided on the first substrate (11) and a plurality of second insulators (16 ') provided on the second substrate (11'); And at least one of the first insulators (16) includes:
A through hole is provided at a central portion, and a bump formed by filling the through hole with a conductor (19) is provided as an external connection terminal, and the bump corresponds to a corresponding one of the second substrate. A semiconductor device characterized by being electrically connected to an electrode pad (12a ') provided at a position. 3. The bump and electrode pad (12) on both the first substrate (11) and the second substrate (11 ').
3. The semiconductor device according to claim 2 , wherein a ') is formed. 4. A first substrate (21) comprising: only the bumps;
Alternatively, only the bump and the first insulator in the form of a protrusion are provided, and the second substrate (26) is provided with the electrode pad (27).
3. The semiconductor device according to claim 2 , further comprising only the second insulator having a protrusion shape. Wherein said Claim 2 'wherein the electrode pads (12a) of the electrical said bump and said second substrate of said first substrate of a semiconductor device according to any one of及至4 (11) (11)' A plurality of first insulators provided on the first substrate and a plurality of second insulators provided on the second substrate. (1
6 ') is engaged and pressurized to electrically connect the pump and the electrode pad (12a').