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JP2986413B2 - AIRIA GRID ARRAY PACKAGE - Google Patents

AIRIA GRID ARRAY PACKAGE

Info

Publication number
JP2986413B2
JP2986413B2 JP8219226A JP21922696A JP2986413B2 JP 2986413 B2 JP2986413 B2 JP 2986413B2 JP 8219226 A JP8219226 A JP 8219226A JP 21922696 A JP21922696 A JP 21922696A JP 2986413 B2 JP2986413 B2 JP 2986413B2
Authority
JP
Japan
Prior art keywords
circuit
semiconductor chip
opening
pads
solder ball
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP8219226A
Other languages
Japanese (ja)
Other versions
JPH1050884A (en
Inventor
董 平川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Jtekt Column Systems Corp
Original Assignee
Fuji Kiko Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Kiko Co Ltd filed Critical Fuji Kiko Co Ltd
Priority to JP8219226A priority Critical patent/JP2986413B2/en
Priority to US08/904,394 priority patent/US6011694A/en
Publication of JPH1050884A publication Critical patent/JPH1050884A/en
Application granted granted Critical
Publication of JP2986413B2 publication Critical patent/JP2986413B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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    • H01L2224/0601—Structure
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、エアリア・グリッ
ド・アレイ・パッケージの構造に係わるもので、更に詳
しくは、シンプルな構成ながら多ピン化・高密度化を図
り、また併せて低コスト化も図れるエアリア・グリッド
・アレイ・パッケージの構造に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of an air rear grid array package, and more particularly, to increase the number of pins and the density with a simple structure, and also reduce the cost. The present invention relates to a structure of an air rear grid array package that can be achieved.

【０００２】[0002]

【従来技術】エアリア・グリッド・アレイ・パッケージ
は、半導体チップとプリント基板を接続する技術とし
て、最近急速に普及してきた。この技術はいわゆるボー
ル・グリッド・アレイ、チップ・サイズ・パッケージと
して、リジッドな積層板を加工したプリント基板の片面
に格子状に配列したパッドを設け、このパッドに半田ボ
ールまたは半田ペースト等を取り付けることにより、こ
の基板とマザーボードと呼ばれるプリント基板との接続
を図るものである〔なお、この技術については、John
H. Lau 著のBall Grid Array Technology（McGraw Hill
社発行、1995）にも詳述されている〕。2. Description of the Related Art Recently, an air rear grid array package has rapidly spread as a technique for connecting a semiconductor chip and a printed circuit board. This technology uses a so-called ball grid array, a chip-size package, in which pads are arranged in a grid on one side of a printed circuit board that has been processed with a rigid laminate, and solder balls or solder paste is attached to these pads. The purpose of this technology is to connect this board to a printed board called a motherboard.
H. Lau's Ball Grid Array Technology (McGraw Hill
And published in 1995).

【０００３】これら従来のエアリア・グリッド・アレイ
・パッケージでは、例えば図６で示したように、絶縁性
基板Ａの第１面１と第２面２（表裏両面）に回路３，４
が形成され、スルーホール２２により両面の回路３，４
が接続されている。該基板Ａの裏側にはパッド９が格子
状に配列されて、ここに半田ボール１１が配置されてお
り、また基板Ａの表面には半導体チップ５が実装され、
半導体チップ５は表面の各回路３にボンディグワイヤー
１４等で電気的に接続され、モールド樹脂１９にて封止
されている（なお、従来技術を示す図６乃至図９におい
て、図面符号は本願発明のものとほぼ共通するようにし
てある）。In these conventional air rear grid array packages, for example, as shown in FIG. 6 , circuits 3 and 4 are provided on a first surface 1 and a second surface 2 (both front and back surfaces) of an insulating substrate A.
Are formed, and the circuits 3 and 4 on both sides are formed by the through holes 22.
Is connected. Pads 9 are arranged in a grid on the back side of the substrate A, on which solder balls 11 are arranged. On the surface of the substrate A, a semiconductor chip 5 is mounted.
The semiconductor chip 5 are electrically connected by a bonding wire 14 or the like to each circuit 3 of the surface are sealed by mold resin 19 (In FIG. 6 through FIG. 9 shows a prior art, reference numerals are present It is almost common to the invention).

【０００４】しかし、上記構造のエアリア・グリッド・
アレイ・パッケージでは、半導体チップを取り付ける面
と半田ボールを取り付ける面とが基板の反対側にあるた
め、全ての配線を表面から裏面へ引き回す必要があり、
その結果として通常は、基板の外周寄り付近に多数のス
ルホールを形成する必要があった。このスルホールは通
常、機械的に形成されるためコストが高くなるし、また
多ピン・高密度なパッケージでは、一定の大きさに収め
るためスルホール間の間隔を小さくする必要があり、そ
のために歩留りの低下や電蝕（エレクトロマイグレーシ
ョン）現象を生じる等の問題点があった。However, the air rear grid of the above structure
In the array package, the surface on which the semiconductor chip is mounted and the surface on which the solder balls are mounted are on the opposite side of the board, so all wiring must be routed from the front surface to the back surface.
As a result, it is usually necessary to form a large number of through holes near the outer periphery of the substrate. Usually, these through holes are mechanically formed, which increases the cost.In addition, in a high-pin-count, high-density package, it is necessary to reduce the distance between the through holes in order to keep a certain size. There are problems such as lowering and the occurrence of electrolytic corrosion (electromigration).

【０００５】この問題点を解決するために提案された技
術として、例えば特開平７−７４２８１公報に開示され
たものがある。これは、スルーホールの代わりに絶縁性
基板の第１面から第２面へ至るヴィアホール（ｖｉａ
ｈｏｌｅ）を設け、第１面とヴィア内部をめっきして配
線するものである。これは、パッドから直接第１面へ配
線することになるため、上記の配線引き回しの問題点は
かなり軽減される。As a technique proposed to solve this problem, there is a technique disclosed in, for example, Japanese Patent Application Laid-Open No. 7-74281. This is because a via hole (via) from the first surface to the second surface of the insulating substrate is used instead of the through hole.
hole), and wiring is performed by plating the first surface and the inside of the via. In this case, since the wiring is performed directly from the pad to the first surface, the above-mentioned problem of the wiring layout is considerably reduced.

【０００６】しかしこの構造の場合も、絶縁性基板の第
１面から第２面への配線の引き回しのためにヴィアホー
ルの形成が必要であり、これが両面での各回路の高密度
化を制限したり、高コストの原因になったりする問題点
があった。However, also in this structure, it is necessary to form a via hole in order to route the wiring from the first surface to the second surface of the insulating substrate, which limits the densification of each circuit on both surfaces. And cause high cost.

【０００７】また図７で示す如く、絶縁性基板Ａとして
ポリイミド等のフレキシブルな合成樹脂製テープを用
い、その第１面１（表面）に回路３を形成すると共に、
同面に半導体チップ５を搭載して、第１面１の半導体チ
ップ接続用パッド６と半導体チップ５とをボンディング
ワイヤー１４で電気的に接続して、モールド樹脂１９で
封止し、第２面（裏面）２から半田ボール取付け用の開
口部１３を形成して、半田ボール１０を取り付けるもの
もあった。As shown in FIG. 7 , a flexible synthetic resin tape such as polyimide is used as the insulating substrate A, and the circuit 3 is formed on the first surface 1 (front surface).
The semiconductor chip 5 is mounted on the same surface, and the semiconductor chip connection pads 6 on the first surface 1 are electrically connected to the semiconductor chip 5 with the bonding wires 14, and are sealed with the mold resin 19. In some cases, an opening 13 for attaching a solder ball is formed from the (back surface) 2 and the solder ball 10 is attached.

【０００８】この構造は、半田パッドの開口をテープ自
身の開口で行うので、リフロー時の半田の流出防止に感
光性液体レジストを塗布しておく必要がなく単純な構造
となるため、この点からは回路の高密度化や低コスト化
を図り易いと言える。しかし回路を基板の片面にしか行
わないため、ピン数に制約があって、多ピン化・高密度
化を図ることが難しかった。In this structure, since the opening of the solder pad is made by the opening of the tape itself, it is not necessary to apply a photosensitive liquid resist to prevent the solder from flowing out during reflow. It can be said that it is easy to increase the circuit density and reduce the cost. However, since the circuit is performed only on one side of the substrate, the number of pins is restricted, and it has been difficult to increase the number of pins and increase the density.

【０００９】また、絶縁性基板Ａとしてリジッド積層板
を用いず、図８で示す如くポリイミド等のフレキシブル
な合成樹脂製テープを用い、その第２面２（裏面）に回
路４を形成して、それを金属スラグ１５下面に接着剤２
１で貼り付けると共に、同じく該金属スラグ１５下面に
半導体チップ５を搭載し、該半導体チップ５と回路４の
半導体チップ接続用パッド７間を、ボンディングワイヤ
ー１４で電気的に接続し、モールド樹脂１９で封止し
て、回路４の半田チップ接続用パッド９に半田ボール１
１を取り付ける構造のものも提案されている（例えば、
特開平７−３２１２５０号公報、米国特許第５３９７９
２１号公報、米国特許第５４２０４６０号公報参照）。Further, without using the rigid laminated plate as the insulating substrate A, using a flexible plastic tape such as polyimide, as shown in Figure 8, to form a circuit 4 to the second surface 2 (back), Adhesive 2 on the lower surface of metal slag 15
1, the semiconductor chip 5 is mounted on the lower surface of the metal slug 15, and the semiconductor chip 5 and the semiconductor chip connecting pad 7 of the circuit 4 are electrically connected by the bonding wire 14. Then, the solder balls 1 are attached to the solder chip connection pads 9 of the circuit 4.
1 is also proposed (for example,
JP-A-7-321250, U.S. Pat.
21, U.S. Pat. No. 5,420,460).

【００１０】これは、キャビティーダウンＢＧＡ（Ｂａ
ｌｌ Ｇｒｉｄ Ａｒｒａｙ）パッケージとして用いる
場合に、テープへの回路形成が片面のみでよく、またＴ
ＡＢ（Ｔａｐｅ Ａｕｔｏｍａｔｅｄ Ｂｏｎｄｉｎ
ｇ）でのテープ技術を用いることで、リジッドな積層板
を用いたものより配線を高密度にできるから、上記のよ
うな配線引き回しの困難さはかなり軽減される。This is because a cavity-down BGA (Ba
When used as a package (II Grid Array), it is only necessary to form a circuit on the tape on one side only.
AB (Tape Automated Bondin)
By using the tape technology in g), the wiring density can be made higher than that using a rigid laminate, so that the above-mentioned difficulty in wiring routing is considerably reduced.

【００１１】しかしこの構造は、回路を基板の片面にし
か行わないため、ピン数に制約があって、通常３００乃
至４００ピン程度のものしか得られない、という問題点
があった。However, in this structure, since the circuit is formed only on one side of the substrate, there is a problem that the number of pins is restricted, and usually only about 300 to 400 pins are obtained.

【００１２】さらに図９で示したように、絶縁性基板Ａ
としてのフレキシブルな合成樹脂製テープの第１面（表
面）１に回路３を形成して、それを金属スラグ１５下面
に上記とは逆に回路３を上向きに接着剤２１で貼り付け
ると共に、同じく該金属スラグ１５下面に半導体チップ
５を搭載してボンディングワイヤー１４で電気的に接続
し、モールド樹脂１９で封止して、かつ該テープＡの第
２面から半田ボール取付け用の開口部１３を形成して、
半田ボール１０を取り付けるようにしたものも提案され
ている。[0012] As further shown in FIG. 9, an insulating substrate A
The circuit 3 is formed on the first surface (front surface) 1 of the flexible synthetic resin tape as above, and the circuit 3 is attached to the lower surface of the metal slag 15 with the adhesive 21 in the opposite direction to the above, and the same. The semiconductor chip 5 is mounted on the lower surface of the metal slag 15, electrically connected with the bonding wire 14, sealed with the mold resin 19, and the opening 13 for attaching the solder ball is formed from the second surface of the tape A. Forming
There has also been proposed one in which a solder ball 10 is attached.

【００１３】この構造も上記図８で示したものと同様
に、半田パッドの開口をテープ自身の開口で行うので、
リフロー時の半田の流出を防止用に感光性液体レジスト
の塗布する必要がなく、この面からは回路の高密度化や
低コスト化を図り易いと言えるが、やはり回路を基板の
片面にしか行わないため、ピン数に制約があって、通常
３００乃至４００ピン程度のものしか得られない、とい
う問題点があった。In this structure, similarly to the structure shown in FIG. 8 , the opening of the solder pad is made by the opening of the tape itself.
There is no need to apply a photosensitive liquid resist to prevent the solder from flowing out during reflow, and from this aspect it can be said that it is easy to increase the density and cost of the circuit, but the circuit is also applied to only one side of the board Therefore, there is a problem that the number of pins is limited, and usually only about 300 to 400 pins are obtained.

【００１４】なお、プリント回路板の形成でのレーザー
の利用は、従来主としてヴィアホール等の孔あけであ
り、ＹＡＧレーザー、エキシマ・レーザー或いは炭酸ガ
スレーザーを改良したインパクト・レーザーが用いられ
ている〔エキシマ・レーザーのプリント回路板への応用
については、例えば特開平５−１３６６５０公報、特開
平５−１５２７４４公報、特開平５−１５２７４８公報
等を参照。またインパクト・レーザーのプリント回路板
への応用については、例えばJ. M. Morrisonなど著の
“A Large Format Modified TEA CO2 Laser Based Proc
ess for Cost Effective Via Generation ”（1994 Int
ernational Conference on Multichip Modules，１９９
４年４月１３〜１５日，ｐ．３６９）を参照〕。The use of a laser for forming a printed circuit board is conventionally mainly used to form a hole such as a via hole, and an impact laser obtained by improving a YAG laser, an excimer laser or a carbon dioxide laser is used. For the application of excimer lasers to printed circuit boards, see, for example, JP-A-5-136650, JP-A-5-152744, and JP-A-5-152748. Regarding the application of impact lasers to printed circuit boards, see, for example, “A Large Format Modified TEA CO2 Laser Based Proc” by JM Morrison and others.
ess for Cost Effective Via Generation ”(1994 Int
ernational Conference on Multichip Modules, 199
April 13-15, 4th year, p. 369)].

【００１５】[0015]

【発明が解決しようとする課題】本発明は、従来の如き
片面のみの配線ではなく、また両面に配線をもち相互を
ヴィアホール等で接続した両面配線でもなく、従来のＢ
ＧＡパッケージを改良した第３の構造のエアリア・グリ
ッド・アレイ・パッケージの提供を課題としたものであ
る。換言すれば、簡単な構成ながら多ピンの半導体が実
装できると共に、配線の引回しの問題が無くなり多ピン
・高密度なエアリア・グリッド・アレイ・パッケージを
提供すること、またそれに加えて、このエアリア・グリ
ッド・アレイ・パッケージを低コストで提供することを
目的とした発明である。The present invention is not limited to the conventional single-sided wiring as in the prior art, nor to the double-sided wiring having wirings on both sides and connected to each other by via holes or the like.
It is an object of the present invention to provide an air rear grid array package having a third structure in which a GA package is improved. In other words, it is possible to provide a multi-pin, high-density air rear grid array package that can mount multi-pin semiconductors with a simple configuration and eliminate wiring routing problems. The invention aims at providing a grid array package at low cost.

【００１６】[0016]

【課題を解決するための手段】上記課題を解決するため
に、本発明に係るエアリア・グリッド・アレイ・パッケ
ージは、絶縁性基板Ａの第１面１と第２面２に、互いに
接続しない独立した回路３，４を形成し、各面１，２の
各回路３，４の一端部に半導体チップ接続用のパッド
６，７を、他端部に半田ボール取付け用のパッド８，９
を各々形成して、搭載した半導体チップ５と各面１，２
の半導体チップ接続用パッド６，７とを電気的に接続す
ると共に樹脂モールドし、かつ各面１，２の半田ボール
取付け用パッド８，９に各々半田ボール１０，１１を取
り付けるエアリア・グリッド・アレイ・パッケージにお
いて、 上記第１面１の回路３裏面へ通じる如く、第２面
２から半田ボール取付け用の開口部１３を形成して、該
開口部１３で露呈した回路３裏面を半田ボール取付け用
のパッド８とすると共に、該開口部１３内に、基板Ａの
絶縁層の厚み分に相当する導電性充填材１８を充填し
て、該充填材１８に半田ボール１０を取付けるものであ
る。 To solve the above SL problems SUMMARY OF THE INVENTION, Earia grid array package <br/> over di according to the present invention, the first surface 1 and the second surface of the insulative substrate A 2, each other
Form independent circuits 3 and 4 that are not connected,
A pad for connecting a semiconductor chip to one end of each circuit 3, 4
6, 7 and pads 8, 9 for attaching solder balls to the other end.
Are formed, and the mounted semiconductor chip 5 and each surface 1, 2
Are electrically connected to the semiconductor chip connection pads 6,7.
As well as resin molding, and solder balls on each side 1 and 2.
Solder balls 10 and 11 are attached to mounting pads 8 and 9, respectively.
Air rear grid array package
And the second surface so as to communicate with the back surface of the circuit 3 on the first surface 1.
2, an opening 13 for attaching a solder ball is formed.
Circuit 3 exposed at opening 13 for solder ball mounting
Of the substrate A in the opening 13
A conductive filler 18 corresponding to the thickness of the insulating layer is filled.
The solder balls 10 are attached to the filler 18.
You.

【００１７】また、上記第２面２の回路４裏面へ通じる
如く、第１面１から半導体チップ接続用の開口部１２を
形成して、該開口部１２で露呈した回路４裏面を半導体
チッ プ接続用のパッド７とすると共に、該開口部１２を
介して半導体チップ５と第２面２の回路４とを接続する
ものである。 Also, the second surface 2 leads to the back surface of the circuit 4.
As described above, the opening 12 for connecting the semiconductor chip is formed from the first surface 1.
The back surface of the circuit 4 formed and exposed in the opening 12
With a pad 7 for chip connection, the opening 12
The semiconductor chip 5 and the circuit 4 on the second surface 2 via the
Things.

【００１８】あるいは、上記第１面１の回路３裏面へ通
じる如く、第２面２から半導体チップ接続用の開口部１
２を形成して、該開口部１２で露呈した回路３裏面を半
導体チップ接続用のパッド６とすると共に、該開口部１
２を介して半導体チップ５と第１面１の回路３とを接続
するものである。 Alternatively, the first surface 1 may be connected to the back surface of the circuit 3.
As shown, the opening 1 for connecting the semiconductor chip from the second surface 2.
2 is formed, and the back surface of the circuit 3 exposed at the opening 12 is cut in half.
A pad 6 for connecting a conductive chip and the opening 1
2 connects the semiconductor chip 5 to the circuit 3 on the first surface 1
Is what you do.

【００１９】[0019]

【発明の実施の形態】上記構成のエアリア・グリッド・
アレイ・パッケージにおいて、絶縁性基板Ａの一端部で
は、第１面１の回路３裏面へ通じる如く、該基板Ａの第
２面２から開口部１３を形成して、該開口部１３で露呈
する回路３裏面を、第１面の回路３への半田ボール取付
け用パッド８としておくのがよい（例えば図１・図２・
図３・図４・図５参照）。 DETAILED DESCRIPTION OF THE INVENTION Earia grid of the structure and
In the array package , at one end of the insulating substrate A
Is connected to the back of the circuit 3 of the first surface 1 so that the
An opening 13 is formed from the two surfaces 2 and is exposed at the opening 13.
The back of the circuit 3 to be soldered to the circuit 3 on the first side
It is preferable that the pad 8 be used as the backup pad 8 (for example, FIGS.
(See FIGS. 3, 4, and 5).

【００２０】他方、該基板Ａの他端部では、第２面２の
回路４裏面へ通じる如く、第１面１から半導体チップ接
続用の開口部１２を形成して、該開口部１２で露呈した
回路４裏面を、第２面２の回路４との半導体チップ接続
用パッド７とし（例えば図１・図３・図４参照）、また
は、第１面１の回路３裏面へ通じる如く、第２面２から
半導体チップ接続用の開口部１２を形成して、該開口部
１２で露呈した回路３裏面を、第１面１の回路３との半
導体チップ接続用のパッド６としておくのがよい（例え
ば図２・図５参照）。 On the other hand, at the other end of the substrate A, the second surface 2
Connect the semiconductor chip from the first surface 1 so as to connect to the back of the circuit 4.
An opening 12 for connection is formed, and the opening 12 is exposed.
Connecting the back surface of the circuit 4 to the semiconductor chip 4 with the circuit 4 on the second surface 2
Pad 7 (for example, see FIGS. 1, 3, and 4).
From the second surface 2 so that it leads to the back of the circuit 3 on the first surface 1
An opening 12 for connecting a semiconductor chip is formed.
The back surface of the circuit 3 exposed at 12 is half of the circuit 3 on the first surface 1
It is preferable that the pad 6 is used for connecting the conductor chip (for example,
See FIG. 2 and FIG. 5).

【００２１】上記絶縁性基板Ａは、リジッドな積層板を
パネル状にして用いたものでもよいが、それに限らずフ
レキシブルな合成樹脂製のフィルムを用いてもよく、さ
らにそれをテープ状にして用いれば生産性が向上するの
で望ましい。The insulative substrate A may be a rigid laminated plate in the form of a panel. However, the present invention is not limited to this, and a flexible synthetic resin film may be used. This is desirable because productivity is improved.

【００２２】絶縁性基板Ａの半導体チップ接続用のパッ
ド６，７へ半導体チップ５を電気的に接続するには、ボ
ンディングワイヤー１４によってもよいが（例えば図１
・図２参照）、バンプ（ボールやペデスタルを含む）１
６，１７によるフリップチップボンディングによっても
よく（例えば図３参照）、さらに図示は省略するがＴＡ
Ｂで用いるギャングボンディングによってもよい。[0022] To electrically connect the semiconductor chip 5 to the pads 6 and 7 for the semiconductor chip connection of the insulating substrate A may by bonding wires 14 is (e.g. FIG. 1
- see Figure 2), bump (including a ball and pedestal) 1
6, 17 may be used ( for example, see FIG. 3 ) .
The gang bonding used in B may be used.

【００２３】絶縁性基板Ａの第１面１および第２面２の
各半田ボール取付け用パッド８，９に半田ボール１０，
１１を取り付ける場合に、基板Ａの厚み分だけ半田ボー
ル取付け用パッド８，９のレベルが異なってくるが、そ
のレベル差の解消のために、第１面１に取り付ける半田
ボール１０の外径を、第２面２の半田ボール取付け用パ
ッド９に取り付ける半田ボール１１よりも、基板Ａの絶
縁層の厚み分だけ大きくしておいてもよい（例えば図２
・図３参照）。Solder balls 10, 9 are attached to solder ball mounting pads 8, 9 on first surface 1 and second surface 2 of insulating substrate A.
When the solder ball 11 is mounted, the level of the solder ball mounting pads 8 and 9 differs by the thickness of the substrate A. To eliminate the level difference, the outer diameter of the solder ball 10 mounted on the first surface 1 is changed. , than the solder balls 11 attached to the second surface 2 of the solder ball mounting pads 9, Oite as large as the thickness of the insulating layer of the substrate a yet good (e.g. FIG. 2
・ See FIG. 3 ).

【００２４】また、半導体チップ５をフリップチップボ
ンディングで実装する場合も同様であり、基板Ａの第２
面２の半導体チップ接続用パッド７のバンプ１７を、第
１面１の半導体チップ接続用バンプ６に取り付けるバン
プ１６よりも、基板Ａの絶縁層の厚み分だけ大きくして
おいてもよい（例えば図３参照）。 Further, The same applies to the case of mounting the semiconductor chip 5 in a flip-chip bonding, the second substrate A
The bumps 17 of the semiconductor chip connection pads 7 of the surface 2 than the bump 16 attached to the first surface 1 of the semiconductor chip connection bumps 6, which may have contact by increasing by the thickness of the insulating layer of the substrate A (e.g. ( See FIG. 3 ).

【００２５】しかし、半田ボール１０，１１のレベル差
の解消は上記に限らず、第１面１の回路３裏面へ通じる
如く、第２面２から半田ボール取付け用の開口部１３を
形成し、該開口部１３で露呈した回路３裏面を半田ボー
ル取付け用のパッド８とし、該開口部１３内に基板Ａの
絶縁層の厚み分に相当する導電性充填材１８を充填して
おく。そして、第２面２の回路４への半田ボール１１は
そのパッド９へそのまま取り付けるが、第１面１の回路
３への半田ボール１０は、該充填材１８の下端面へ取り
付けるようにしてもよい（例えば図１参照）。 However, the level difference between the solder balls 10 and 11
Is not limited to the above, and leads to the circuit 3 back surface of the first surface 1
As described above, the opening 13 for attaching the solder ball is formed from the second surface 2.
The back surface of the circuit 3 formed and exposed at the opening 13 is
And a pad 8 for mounting the substrate A in the opening 13.
The conductive filler 18 corresponding to the thickness of the insulating layer is filled.
deep. Then, the solder ball 11 to the circuit 4 on the second surface 2 is
It is attached to the pad 9 as it is, but the circuit on the first surface 1
The solder ball 10 to 3 is taken to the lower end face of the filler 18.
It may be attached (for example, see FIG. 1).

【００２６】この導電性充填材１８を用いれば、第１面
１の回路３へ接続する半田ボール１０と、第２面２の回
路４への接続する半田ボール１１とを、外径が同じ大き
さのを用いても、取付けられた両半田ボール１０，１１
のレベルを一致させることができるようになる（上記図
１参照）。 If this conductive filler 18 is used, the first surface
A solder ball 10 connected to the circuit 3 of the first and second circuits 2
The solder balls 11 to be connected to the path 4 have the same outer diameter.
Even if the solder balls are used, both solder balls 10, 11
Level can be matched (see the figure above)
1).

【００２７】上記の絶縁性基板Ａについてより詳しく述
べると、絶縁層の第１・第２の両面に導電層を有する３
層構造をしたもので、絶縁層の典型的な厚みは２０〜１
００μｍであり、絶縁層と導電層の間に接着層を有して
いてもよい。絶縁層の樹脂成分としては、例えばエポキ
シ樹脂、ポリイミド樹脂、ビスマレイミドトリアジン樹
脂、またはポリシラン樹脂とすることが望ましく、熱硬
化性樹脂と熱可塑性樹脂のいずれも用いることができ
る。熱硬化性樹脂中では、エポキシ樹脂、ポリイミド樹
脂、ポリシアヌレート樹脂、ポリシラン樹脂、ポリベン
ツイミダゾール樹脂等が用いられる。The above-mentioned insulating substrate A will be described in more detail. The insulating substrate A has a conductive layer on both the first and second surfaces.
With a layer structure, the typical thickness of the insulating layer is 20 to 1
It is 00 μm, and may have an adhesive layer between the insulating layer and the conductive layer. The resin component of the insulating layer is preferably, for example, an epoxy resin, a polyimide resin, a bismaleimide triazine resin, or a polysilane resin, and any of a thermosetting resin and a thermoplastic resin can be used. Among the thermosetting resins, an epoxy resin, a polyimide resin, a polycyanurate resin, a polysilane resin, a polybenzimidazole resin and the like are used.

【００２８】上記絶縁層は補強材を含むことができ、そ
の際際の補強材としては、例えはガラス繊維のような無
機繊維や、アラミド繊維、テフロン繊維、ポリエーテル
エーテルケトン繊維、ポリベンツイミダゾール繊維等の
有機繊維であってもよい。上記有機繊維中で、特にアラ
ミド繊維やテフロン繊維は、レーザー加工が容易なため
に望ましいが、アラミド繊維、テフロン繊維はレーザー
等による加工性や、優れた電気特性を有しているために
望ましいが、アラミド繊維の中でもとりわけコポリパラ
フェニレン３、４’オキシジフェニルテレフタラミド繊
維は、低いイオン不純物と低い吸湿率のため、一層望ま
しい。The insulating layer may contain a reinforcing material. In this case, the reinforcing material may be, for example, an inorganic fiber such as a glass fiber, an aramid fiber, a Teflon fiber, a polyetheretherketone fiber, a polybenzimidazole. Organic fibers such as fibers may be used. Among the above organic fibers, in particular, aramid fibers and Teflon fibers are desirable because of easy laser processing, but aramid fibers and Teflon fibers are desirable because they have workability by laser or the like and have excellent electric characteristics. Of the aramid fibers, copolyparaphenylene 3,4'oxydiphenylterephthalamide fiber is more desirable because of its low ionic impurities and low moisture absorption.

【００２９】絶縁層は補強材を含まぬフィルム状やシー
ト状のものにすることができ、その場合の材料として
は、ポリエステル樹脂、ポリイミド樹脂、ポリエーテル
エーテルケトン樹脂、ポリアミド樹脂、とりわけアラミ
ド樹脂、特にポリパラフェニレンテレフタラミド樹脂と
することが望ましい。The insulating layer may be in the form of a film or sheet without a reinforcing material. In this case, the material may be a polyester resin, a polyimide resin, a polyetheretherketone resin, a polyamide resin, especially an aramid resin, In particular, it is desirable to use polyparaphenylene terephthalamide resin.

【００３０】上記絶縁性基板Ａには、絶縁層両面の導電
層を加工処理して回路３，４を形成してあり、その第１
面１の回路３や第２面２の回路４には、中央部に半導体
チップ５を搭載用の空白部（開口部、パドルを含む）を
有する。その近辺から外周寄りへ延びる回路３，４の内
側寄りの端部に、ワイヤーボンディングやフリップチッ
プボンディング等で半導体チップ５と電気的に接続する
ための半導体チップ接続用パッド６，７を形成してあ
る。また外周部へ延伸した該回路３，４の外側寄り端部
に、半田ボール１０，１１を取り付けるための半田ボー
ル取付け用パッド８，９を形成してある。Circuits 3 and 4 are formed on the insulating substrate A by processing the conductive layers on both sides of the insulating layer.
The circuit 3 on the surface 1 and the circuit 4 on the second surface 2 have a blank portion (including an opening and a paddle) for mounting the semiconductor chip 5 at the center. Semiconductor chip connection pads 6, 7 for electrically connecting to the semiconductor chip 5 by wire bonding, flip chip bonding, or the like are formed at the inner ends of the circuits 3, 4 extending from the vicinity to the outer periphery. is there. Solder ball mounting pads 8 and 9 for mounting solder balls 10 and 11 are formed at the outer end portions of the circuits 3 and 4 extending to the outer peripheral portion.

【００３１】上記の如く各回路３，４は、一端部に上記
半導体チップ接続用パッド６，７を有し、他端部に半田
ボール取付け用パッド８，９を有するが、第１面１と第
２面２にある各回路３，４は、互いが結合すること無く
独立して形成してある。As described above, each of the circuits 3 and 4 has the semiconductor chip connection pads 6 and 7 at one end and the solder ball attachment pads 8 and 9 at the other end. The circuits 3 and 4 on the second surface 2 are independently formed without being connected to each other.

【００３２】絶縁性基板Ａの各面１，２に形成された上
記各回路３，４の形成方法としてはは、通常、サブトラ
クティブ法でエッチングして、これにより回路加工する
のがよい。これで、上記の如く基板Ａの中央部に半導体
チップ搭載用の空白部を、その近辺から外周寄りへ延び
る回路３，４を形成して、その各一端部に半導体チップ
接続用パッド６，７を、各他端部に半田ボール取付け用
パッド８，９を形成しておくのがよい。As a method for forming each of the circuits 3 and 4 formed on each of the surfaces 1 and 2 of the insulating substrate A, usually, it is preferable to perform etching by a subtractive method and thereby process the circuit. Thus, a blank portion for mounting a semiconductor chip is formed in the center of the substrate A as described above, and circuits 3 and 4 extending from the vicinity thereof to the outer periphery are formed. It is preferable to form solder ball attachment pads 8 and 9 at the other end.

【００３３】絶縁性基板Ａに形成した半導体チップ接続
用パッド６，７、および半田ボール取付け用パッド８，
９のために、開口部１２，１３を形成しておく。それに
は例えば化学エッチング、レーザー加工、機械的ドリリ
ング、パンチング等の方法が採用できるが、レーザー加
工は精度が高く、また低コストのために望ましい。レー
ザーは、炭酸ガスレーザー、ＹＡＧレーザー、エキシマ
・レーザーのいずれも使用可能であるが、孔内の壁面を
滑らで荒らさずに加工するため、炭酸ガスレーザーの一
種であるインパクト・レーザーや、ＹＡＧレーザー、エ
キシマレーザーが好適である。The semiconductor chip connecting pads 6 and 7 formed on the insulating substrate A and the solder ball mounting pads 8 and
Openings 12 and 13 are formed in advance for 9. For example, methods such as chemical etching, laser processing, mechanical drilling, and punching can be employed, but laser processing is desirable because of its high accuracy and low cost. As the laser, any of a carbon dioxide gas laser, a YAG laser, and an excimer laser can be used. However, in order to process the wall surface inside the hole without making it smooth, an impact laser, which is a type of carbon dioxide laser, and a YAG laser And an excimer laser.

【００３４】図において、１４はボンディングワイヤ
ー、１９はモールド樹脂、２０は感光性液体レジスト、
２１は接着剤を各々示す。なお感光性液体レジスト２０
は、図示例では基板Ａの第２面２にだけ塗布してある
が、第１面１の回路４上を被覆するように塗布してもよ
いことは勿論である。In the figure, 14 is a bonding wire, 19 is a mold resin, 20 is a photosensitive liquid resist,
Reference numeral 21 denotes an adhesive. The photosensitive liquid resist 20
Is applied only to the second surface 2 of the substrate A in the illustrated example, but may be applied so as to cover the circuit 4 on the first surface 1.

【００３５】上記の如くして得られる本発明に係るエア
リア・グリッド・アレイ・パッケージでは、第１面１と
第２面２に各々回路３，４が形成されており、その各回
路３，４は半導体チップ５と各々独立して電気的に接続
されると共に、マザーボード（図示略）へも電気的に各
々独立して接続されることになる。そのため、従来の片
面のみに回路を形成したものと異なり、多ピン化・高密
度化を図れると共に、両面に回路３，４を有しながらそ
の間を接続するスルホールやヴィアホール等も不要とな
る。In the air rear grid array package according to the present invention obtained as described above, the circuits 3 and 4 are formed on the first surface 1 and the second surface 2, respectively. Are electrically and independently connected to the semiconductor chip 5, respectively, and are also electrically and independently connected to a motherboard (not shown). Therefore, unlike a conventional circuit in which a circuit is formed only on one side, the number of pins can be increased and the density can be increased, and a through-hole or a via-hole, which has circuits 3 and 4 on both sides and connects between them, becomes unnecessary.

【００３６】また本発明のエアリア・グリッド・アレイ
・パッケージで用いる基板は、リジッドな積層板をパネ
ル状で用いることもできるが、特にフレキシブルな合成
樹脂製フィルムをテープ状にしたものを用いることによ
り、回路の形成・開口部の形成・部分メッキ・半導体チ
ップの実装等の各工程を、連続的なものとして処理する
ことも可能となり、全体のコストを低減できるようにな
る。As the substrate used in the air rear grid array package of the present invention, a rigid laminated plate can be used in the form of a panel. In particular, a flexible synthetic resin film in the form of a tape is used. In addition, it is also possible to process each process such as forming a circuit, forming an opening, partially plating, and mounting a semiconductor chip as a continuous process, thereby reducing the overall cost.

【００３７】[0037]

【実施例】次に、本発明に係るエアリア・グリッド・ア
レイ・パッケージの実施例を述べる。絶縁性基板Ａとし
ては、絶縁層にポリイミド樹脂製で厚み４０μｍのフィ
ルムを用い、その第１面１と第２面２の両面に導電層と
して厚み１８μｍの銅箔を張りつけた両面銅張フィルム
を用い、それを幅４８ｍｍのテープ状とすると共に、従
来のＴＡＢ用テープと同様に両側縁寄りにスプロケット
（図示略）を形成しておく。Next, an embodiment of an air rear grid array package according to the present invention will be described. As the insulating substrate A, a double-sided copper-clad film made of a polyimide resin film having a thickness of 40 μm as an insulating layer and having a 18 μm-thick copper foil adhered as a conductive layer to both surfaces of the first surface 1 and the second surface 2 is used. It is used in the form of a tape having a width of 48 mm, and sprockets (not shown) are formed near both side edges similarly to the conventional TAB tape.

【００３８】上記絶縁性基板Ａに、各回路３，４・半導
体チップ接続用パッド６，７・半田ボール取付け用パッ
ド８，９等を形成するためのパターンニング、第２面２
の半導体チップ接続用パッド７のための開口部１２と、
第１面１の半田ボール取付け用パッド８のための開口部
１３の形成、および各回路３，４のパッド６，７，８，
９や半導体チップ搭載用のパドル部（空白部）のメッキ
必要箇所への金メッキ処理等を行う。これらの各工程
は、基板Ａのスプロケットに歯車を掛ける方式で連続的
に移動させながら、連続的に行うようにする。Patterning for forming circuits 3, 4; semiconductor chip connecting pads 6, 7; solder ball mounting pads 8, 9 and the like on the insulating substrate A;
Opening 12 for the semiconductor chip connection pad 7 of
Forming openings 13 for solder ball mounting pads 8 on first surface 1 and pads 6, 7, 8,
For example, gold plating is performed on portions of the paddle portion (blank portion) required for plating the semiconductor chip 9 and the semiconductor chip. Each of these steps is performed continuously while continuously moving the sprocket of the substrate A by a method in which a gear is put on the sprocket.

【００３９】上記絶縁性基板Ａ両面の銅箔に行うパター
ンニングは、ここではサブトラクティブ法でエッチング
して行っており、パターンの領域は、ここでは銅箔部分
の３５ｍｍ×３５ｍｍ程度とした。その際に、第１面１
の中央部には半導体チップ５を搭載するためのパドル部
を形成し、その近辺から外周部にかけて多数本の回路
３，４を形成する。The patterning performed on the copper foil on both surfaces of the insulating substrate A was performed by etching in a subtractive method, and the pattern area was set to about 35 mm × 35 mm of the copper foil portion. At that time, the first surface 1
A paddle portion for mounting the semiconductor chip 5 is formed at the center of the device, and a large number of circuits 3 and 4 are formed from the vicinity to the outer periphery.

【００４０】上記第１面１および第２面２の各回路３，
４の内側寄りの端部には、半導体チップ５と電気的に接
続するための半導体チップ接続用パッド６，７を形成
し、そこから外周部へ延伸した各回路３，４の他端部に
は、半田ボール１０，１１を取り付けるための半田ボー
ル取付け用パッド８，９を形成しておく。Each circuit 3 of the first surface 1 and the second surface 2
Semiconductor chip connection pads 6 and 7 for electrically connecting to the semiconductor chip 5 are formed on the inner end of the circuit 4, and the other ends of the circuits 3 and 4 extending therefrom to the outer periphery are formed. Are formed with solder ball mounting pads 8 and 9 for mounting the solder balls 10 and 11.

【００４１】上記の半導体チップ接続用パッド６，７
は、図１・図３・図４で示すように、基板Ａの内側寄り
端部に、第２面２の回路４裏面へ通じる如く、第１面１
から半導体チップ接続用の開口部１２を形成して、該開
口部１２で露呈した回路４裏面を、第２面２の回路４へ
の半導体チップ接続用パッド７とする。あるいは、図２
や図５で示す如く、第１面１の回路３裏面へ通じる如
く、第２面２から半導体チップ接続用の開口部１２を形
成して、該開口部１２で露呈した回路３裏面を、第１面
１の回路３への半導体チップ接続用のパッド６としてお
く。The above semiconductor chip connection pads 6, 7
Is closer to the inside of the substrate A as shown in FIGS. 1, 3, and 4.
At the end, the first surface 1 is connected to the back of the circuit 4 on the second surface 2.
An opening 12 for connecting a semiconductor chip is formed from
The back surface of the circuit 4 exposed at the mouth 12 is connected to the circuit 4 on the second surface 2.
Of the semiconductor chip connection pad 7. Alternatively, FIG.
5 and as shown in FIG.
In addition, an opening 12 for connecting a semiconductor chip is formed from the second surface 2.
And the back surface of the circuit 3 exposed at the opening 12
1 as a pad 6 for connecting a semiconductor chip to the circuit 3.
Good .

【００４２】上記の半導体チップ接続用パッド６，７の
内、図１及び図３で示すものは、第２面２のものを第１
面１のものより大きめに形成しておき、第１面１から絶
縁層にレーザー加工で開口部１２を形成して、第２面２
の回路４の裏面を露呈させてある。これらの実施例で
は、第１面での半導体チップ接続用パッド６の幅を８０
μｍ、ピッチを１３０μｍとし、第２面での半導体チッ
プ接続用パッド６の幅を１００μｍ、ピッチを１３０μ
ｍとし、第１面１からの開口部１２の内径を８０μｍと
してある。Of the above-mentioned semiconductor chip connection pads 6 and 7, those shown in FIGS.
The first surface 1 is formed larger than that of the first surface 1, the opening 12 is formed in the insulating layer from the first surface 1 by laser processing, and the second surface 2 is formed.
The back surface of the circuit 4 is exposed. In these examples, the width of the semiconductor chip connection pads 6 of the first surface 80
μm, the pitch is 130 μm, the width of the semiconductor chip connecting pad 6 on the second surface is 100 μm, and the pitch is 130 μm.
m, and the inner diameter of the opening 12 from the first surface 1 is 80 μm.

【００４３】他方、半田ボール取付け用パッド８，９の
内、第１面１のものは第２面２から基板Ａの絶縁層にレ
ーザー加工して開口部１３を形成して、露呈した第１面
１の回路３の裏面を半田ボール取付け用パッド８とす
る。そして図１で示す如く、第１面１の半田ボール取付
け用パッド８の開口部１３内に、絶縁層の厚みに相当す
る導電性樹脂またはメッキ層からなる導電性充填材１８
としてのバンプを充填しておく。その取付けは、両半田
ボール１０，１１は径を同一の大きさのものを用いるよ
うにして、第２面２の回路４への半田ボール１１はパッ
ド９へそのまま取付けるが、第１面１の回路３への半田
ボール１０は上記導電性充填材１８の下端面に取付け
る。 On the other hand, of the solder ball mounting pads 8 and 9, those of the first surface 1 are formed by laser processing the insulating layer of the substrate A from the second surface 2 to form an opening 13, and the exposed first portion 1 is exposed. surface
The back surface of the circuit 3 is a pad 8 for attaching a solder ball.
You. Then, as shown in FIG.
In the opening 13 of the connection pad 8, the thickness corresponding to the thickness of the insulating layer is provided.
Filler 18 made of conductive resin or plating layer
Is filled with bumps. Attach the two solders
Use balls 10 and 11 with the same diameter.
Thus, the solder ball 11 to the circuit 4 on the second surface 2 is
To the circuit 3 on the first surface 1
The ball 10 is attached to the lower end surface of the conductive filler 18.
You.

【００４４】上記半田ボール取付け用パッド８，９の大
きさは、ここでは開口部１３を０．５ｍｍで、ピッチを
１．２７ｍｍとした。上記のレーザー加工は、上記の如
く種々のものが用いられるが、ここではエキシマレーザ
ーを用い、レーザー光をマスクで絞って照射して行って
いる。The size of the solder ball mounting pads 8 and 9, wherein an opening 13 at 0.5mm was a 1.27mm pitch. As the above laser processing, various types are used as described above. Here, an excimer laser is used, and the laser beam is focused and irradiated with a mask.

【００４５】上記の如くして得られた基板Ａに半導体チ
ップ５を搭載して、図１・図２で示すものではボンディ
ングワイヤー１４により、また図３で示すものではバン
プ１７により、各々半導体チップ接続用パッド６，７と
接続しておくが、開口部１２から露呈した第１面１また
は第２面２の回路３，４裏面が同パッド６，７となって
いるものでは、各開口部１２を介して接続してある。 [0045] equipped with a semi-conductor chip 5 on the substrate A obtained as described above, are those shown in FIG. 1 and FIG 2 Bondi
3 and the bumping wire 14 shown in FIG.
And the semiconductor chip connection pads 6 and 7
The first surface 1 and the first surface 1
Means that the circuits 3 and 4 on the second surface 2 are the same pads 6 and 7
Are connected through the respective openings 12.

【００４６】その状態の半導体チップ５を中心して、基
板Ａの第１面１側をモールディング樹脂１９で全面的に
オーバーモールドして封止する。そして第２面２側か
ら、第１面１の半田ボール取付け用パッド８、および第
２面の取付け用パッド９に、各々半田ボール１０，１１
を取り付けておく。 With the semiconductor chip 5 in that state as the center, the first surface 1 side of the substrate A is entirely overmolded with a molding resin 19 and sealed. Then, from the second surface 2 side, solder balls 10 and 11 are attached to the solder ball attaching pad 8 on the first surface 1 and the attaching pad 9 on the second surface, respectively.
Is attached .

【００４７】これにより、基板Ａの第１面１と第２面２
で各面の回路３，４が互いに独立して多ピン化・高密度
化したエアリア・グリッド・アレイ・パッケージを製造
することができ、ここでは、第１面および第２面を併せ
て５４０のリード数をもつ多ピンのものが得られた。Thus, the first surface 1 and the second surface 2 of the substrate A
In this way, it is possible to manufacture an air rear grid array package in which the circuits 3 and 4 on each side are multi-pin and high-density independently of each other. A multi-pin device having the number of leads was obtained.

【００４８】なお、半田ボール１０，１１の取付けにつ
いては上記に限らず、図２及び図３で示す如く、第１面
１のパッド８へ取り付ける半田ボール１０を、第２面２
の半田ボール１１より外径が大きいものを用いても、両
半田ボール１０，１１のレベルを一致させることはでき
る。例えば絶縁層の厚みが上記の如く４０μｍであるな
ら、開口部１３もその厚み分の４０μｍだけ外径を大き
くして、大きい半田ボール１０を用いるようにしてもよ
い。 Note that the mounting of the solder balls 10 and 11
However, the present invention is not limited to the above, and as shown in FIGS.
The solder ball 10 to be attached to the first pad 8 is
Even if a solder ball having a larger outer diameter than the solder ball 11 is used,
It is not possible to match the levels of the solder balls 10 and 11
You. For example, the thickness of the insulating layer is 40 μm as described above.
The opening 13 also has a larger outer diameter by 40 μm for its thickness.
Therefore, a large solder ball 10 may be used.
No.

【００４９】また、半導体チップ５の搭載は、上記実施
例のように基板１へ直接に搭載するのに限らない。図２
で示すように、第１面１および第２面２に回路３，４・
半導体チップ接続用パッド６，７・半田ボール取付け用
パッド８，９を形成した基板Ａを、別体の金属スラグ１
５に接着剤２１で張り付けると共に半導体チップ５も該
金属スラグ１５に搭載して、基板Ａの各面３，４の各半
導体チップ接続用パッド６，７にワイヤーボンディグ等
で接続し、各半田ボール取付け用パッド８，９に半田ボ
ール１０，１１を取り付けるようにしてもよい。The mounting of the semiconductor chip 5 is not limited to the mounting directly on the substrate 1 as in the above embodiment. Figure 2
As shown in the figure, the circuits 3, 4.
The substrate A on which the semiconductor chip connecting pads 6 and 7 and the solder ball mounting pads 8 and 9 are formed is separated into a separate metal slug 1
5, the semiconductor chip 5 is also mounted on the metal slug 15, and connected to the semiconductor chip connection pads 6, 7 on the respective surfaces 3, 4 of the substrate A by wire bonding or the like. The solder balls 10, 11 may be attached to the solder ball attachment pads 8, 9.

【００５０】図示は省略したが、各半導体チッチ接続用
パッド６，７と半導体チップ５との電気的接続は、上記
に限らずＴＡＢで用いられるギャングボンディングによ
ることも可能である。[0050] Figure shows is omitted, but the electrical connection between the semiconductor Chitchi connection pads 6 and 7 and the semiconductor chip 5 is also possible by gang bonding used in TAB not limited to the above.

【００５１】[0051]

【発明の効果】上記の如く、本発明に係るエアリア・グ
リッド・アレイ・パッケージは、次の効果を奏する。As described above, the air rear grid array package according to the present invention has the following effects.

【００５２】１）本発明に係るエアリア・グリッド・ア
レイ・パッケージは、シンプルな構造と製造手段によ
り、基板の第１面と第２面に各々電気的に独立した回路
を形成して、該各回路を半導体チップと各々独立に電気
的に接続し、かつマザーボード（図示略）へも電気的に
独立して接続できるものとなる。1) The air rear grid array package according to the present invention forms an electrically independent circuit on each of the first surface and the second surface of the substrate by a simple structure and manufacturing means. The circuit can be electrically connected to the semiconductor chip independently of each other, and can also be electrically and independently connected to a motherboard (not shown).

【００５３】そのため、従来の片面のみに回路を形成し
たエアリア・グリッド・アレイ・パッケージと異なり、
約２倍の多ピン化・高密度化を図ることができる。また
従来の両面に回路を有するものと異なり、両面に回路を
有しながらそれらを接続するスルーホールやヴィアホー
ル等の特別な接続手段を不要とし、かつ配線の引回しも
容易となって、歩留りを向上させることもできる。Therefore, unlike the conventional air rear grid array package in which a circuit is formed only on one side,
About twice Ru can be made multi-pin and high density. Also different from the one having a circuit on both sides of <br/> conventional circuits on both sides
This eliminates the need for special connection means such as through holes and via holes that connect them, and also facilitates the routing of the wiring, thereby improving the yield.

【００５４】２）また本発明のエアリア・グリッド・ア
レイ・パッケージでは、その基板の絶縁性基板としてリ
ジッドなパネル状の板材を用いることもできるが、特に
フレキシブルなフィルムをテープ状にした絶縁性基板を
用いることにより、回路の形成・開口部の形成・半導体
チップの実装等の一連の工程を連続的に処理することが
できるようになり、エアリア・グリッド・アレイ・パッ
ケージ製造の全体のコストを低減することもできる。2) In the air rear grid array package of the present invention, a rigid panel-shaped plate material can be used as the insulating substrate of the substrate. By using, a series of processes such as circuit formation, opening formation, semiconductor chip mounting, etc. can be continuously processed, reducing the overall cost of manufacturing air rear grid array package You can also.

【００５５】３）さらに、本発明のエアリア・グリッド
・アレイ・パッケージで、第１面の半田ボール取付け用
パッドの開口部内に、絶縁層の厚みに相当する導電性充
填材を充填したものでは、第２面の回路への半田ボール
はそのままパッドへ取付けるが、第１面の回路への半田
ボールは上記導電性充填材の下端面に取付ける。そのた
め、両半田ボールは径を同一のものを用いても、取り付
けた両半田ボールのレベルを一致させることができ、パ
ッド間即ちボール間のピッチも一定となり、この点から
多ピン化・高密度化を図ることができ、かつコストダウ
ンを図ることができる。 3) Further, the air rear grid of the present invention
-For mounting solder balls on the first surface in an array package
In the pad opening, a conductive filler equivalent to the thickness of the insulating layer
In the case of the filling material, solder balls to the circuit on the second surface
Is attached to the pad as it is, but solder to the circuit on the first side
The ball is attached to the lower end surface of the conductive filler. That
Even if both solder balls have the same diameter,
The level of both solder balls can be matched,
The pitch between the balls, that is, between the balls is also constant, and from this point
High pin count and high density can be achieved, and cost down
Can be planned.

【００５６】４）しかも、絶縁性基板に半導体チップ接
続用の開口部を形成し、該開口部で露呈した第１面また
は第２面の回路裏面を半導体チップ接続用のパッドとす
ると共に、該開口部を介して半導体チップと接続したも
のでは、配線の引回しの問題が無くなり製造が容易とな
ると共に、この面でも多ピン化・高密度化とコストダウ
ンを図ることができる。 4) In addition, the semiconductor chip is connected to the insulating substrate.
An opening for connection, and the first surface or
Indicates that the back surface of the circuit on the second surface is a pad for connecting a semiconductor chip.
Connected to the semiconductor chip through the opening.
This eliminates the problem of wiring routing and makes manufacturing easier.
In addition, the number of pins and the density increase and cost down
Can be planned.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明に係るエアリア・グリッド・アレイ・パ
ッケージの実施例を示す一部の拡大縦断面図である。FIG. 1 is a partially enlarged longitudinal sectional view showing an embodiment of an air rear grid array package according to the present invention.

【図２】本発明に係るエアリア・グリッド・アレイ・パ
ッケージの他の実施例を示す一部の拡大縦断面図であ
る。FIG. 2 is a partially enlarged longitudinal sectional view showing another embodiment of the air rear grid array package according to the present invention.

【図３】本発明に係るエアリア・グリッド・アレイ・パ
ッケージの別の実施例を示す一部の拡大縦断面図であ
る。FIG. 3 is a partially enlarged longitudinal sectional view showing another embodiment of the air rear grid array package according to the present invention.

【図４】図１や図３で示した実施例で用いた絶縁性基板
の一部を示す拡大縦断面図である。 FIG. 4 is an insulating substrate used in the embodiment shown in FIGS.
It is an expanded longitudinal cross-sectional view which shows a part of.

【図５】図２で示した実施例で用いた絶縁性基板の一部
を示す拡大縦断面図である。 FIG. 5 is a part of an insulating substrate used in the embodiment shown in FIG . 2;
FIG.

【図６】従来のエアリア・グリッド・アレイ・パッケー
ジの例を示した拡大縦断面図である。 FIG. 6 shows a conventional air rear grid array package.
FIG. 4 is an enlarged vertical sectional view showing an example of the jig.

【図７】従来のエアリア・グリッド・アレイ・パッケー
ジの他の例の一部を示すの拡大縦断面図である。 FIG. 7 shows a conventional air rear grid array package.
It is an expanded longitudinal cross-sectional view which shows a part of other examples of J.

【図８】従来のエアリア・グリッド・アレイ・パッケー
ジの別の例の一部を示す拡大縦断面図である。 FIG. 8 shows a conventional air rear grid array package.
It is an expanded longitudinal cross-sectional view which shows a part of another example of J.

【図９】従来のエアリア・グリッド・アレイ・パッケー
ジの更に別の例の一部を示す拡大縦断面図である。 FIG. 9 shows a conventional air rear grid array package.
It is an expanded longitudinal cross-sectional view which shows a part of another example of J.

【符号の説明】[Explanation of symbols]

Ａ−絶縁性基板 １１−半田ボール ２
２−スルホール １−第１面 １２−開口部 ２−第２面 １３−開口部 ３−回路 １４−ボンディングワイヤー ４−回路 １５−金属スラグ ５−半導体チップ １６−バンプ ６−パッド １７−バンプ ７−パッド １８−導電性充填材 ８−パッド １９−モールド樹脂 ９−パッド ２０−感光性液体レジスト １０−半田ボール ２１−接着剤A-Insulating substrate 11-Solder ball 2
2-Through hole 1-First surface 12-Opening 2-Second surface 13-Opening 3-Circuit 14-Bonding wire 4-Circuit 15-Metal slug 5-Semiconductor chip 16-Bump 6-Pad 17-Bump 7- Pad 18-conductive filler 8-pad 19-mold resin 9-pad 20-photosensitive liquid resist 10-solder ball 21-adhesive

───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 21/60 H01L 23/12 H01L 23/28 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 6 , DB name) H01L 21/60 H01L 23/12 H01L 23/28

Claims (6)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】絶縁性基板Ａの第１面１と第２面２に、互
いに接続しない独立した回路３，４を形成し、各面１，
２の各回路３，４の一端部に半導体チップ接続用のパッ
ド６，７を、他端部に半田ボール取付け用のパッド８，
９を各々形成して、搭載した半導体チップ５と各面１，
２の半導体チップ接続用パッド６，７とを電気的に接続
すると共に樹脂モールドし、かつ各面１，２の半田ボー
ル取付け用パッド８，９に各々半田ボール１０，１１を
取り付けるエアリア・グリッド・アレイ・パッケージに
おいて、 上記第１面１の回路３裏面へ通じる如く、第２面２から
半田ボール取付け用の開口部１３を形成して、該開口部
１３で露呈した回路３裏面を半田ボール取付け用のパッ
ド８とすると共に、該開口部１３内に、基板Ａの絶縁層
の厚み分に相当する導電性充填材１８を充填して、該充
填材１８に半田ボール１０を取付けたことを特徴とす
る、 エアリア・グリッド・アレイ・パッケージ。1. A on the first surface 1 and the second surface 2 of the insulating substrate A, to form a circuit 3, 4 separate not connected to each other, each face 1,
2 , pads 6 and 7 for connecting a semiconductor chip to one end of each circuit 3 and 4 , and pads 8 and 7 for attaching a solder ball to the other end .
9, each forming a semiconductor chip 5 and each surface 1 with,
2 are electrically connected to the semiconductor chip connection pads 6 and 7, and resin-molded, and the solder balls 10 and 11 are mounted on the solder ball mounting pads 8 and 9 on each surface 1 and 2 , respectively. Aerial grid array package
Then, from the second surface 2 so as to communicate with the back surface of the circuit 3 on the first surface 1
An opening 13 for attaching a solder ball is formed.
13. The back surface of the circuit 3 exposed in step 13 is
And an insulating layer of the substrate A in the opening 13.
Is filled with a conductive filler 18 corresponding to the thickness of
The solder ball 10 is attached to the filler 18.
That, Earia grid array package. 【請求項２】絶縁性基板Ａの第１面１と第２面２に、互
いに接続しない独立した回路３，４を形成し、各面１，
２の各回路３，４の一端部に半導体チップ接続用のパッ
ド６，７を、他端部に半田ボール取付け用のパッド８，
９を各々形成して、搭載した半導体チップ５と各面１，
２の半導体チップ接続用パッド６，７とを電気的に接続
すると共に樹脂モールドし、かつ各面１，２の半田ボー
ル取付け用パッド８，９に各々半田ボール１０，１１を
取り付けるエアリア・グリッド・アレイ・パッケージに
おいて、 上記第２面２の回路４裏面へ通じる如く、第１面１から
半導体チップ接続用の開口部１２を形成して、該開口部
１２で露呈した回路４裏面を半導体チップ接続用のパッ
ド７とすると共に、該開口部１２を介して半導体チップ
５と第２面２の回路４とを接続したことを特徴とする、
エアリア・グリッド・アレイ・パッケージ。2. Independent circuits 3 and 4 that are not connected to each other are formed on a first surface 1 and a second surface 2 of an insulating substrate A ,
2 , pads 6 and 7 for connecting a semiconductor chip to one end of each circuit 3 and 4 , and pads 8 and 7 for attaching a solder ball to the other end .
9, each forming a semiconductor chip 5 and each surface 1 with,
2 are electrically connected to the semiconductor chip connection pads 6 and 7, and resin-molded, and the solder balls 10 and 11 are mounted on the solder ball mounting pads 8 and 9 on each surface 1 and 2 , respectively. Aerial grid array package
Then, from the first surface 1 so as to communicate with the back surface of the circuit 4 on the second surface 2
An opening 12 for connecting a semiconductor chip is formed.
The back surface of the circuit 4 exposed in Step 12 is connected to a package for connecting a semiconductor chip.
7 and a semiconductor chip through the opening 12.
5 and the circuit 4 on the second surface 2 are connected.
Air rear grid array package. 【請求項３】絶縁性基板Ａの第１面１と第２面２に、互
いに接続しない独立した回路３，４を形成し、各面１，
２の各回路３，４の一端部に半導体チップ接続用のパッ
ド６，７を、他端部に半田ボール取付け用のパッド８，
９を各々形成して、搭載した半導体チップ５と各面１，
２の半導体チップ接続用パッド６，７とを電気的に接続
すると共に樹脂モールドし、かつ各面１，２の半田ボー
ル取付け用パッド８，９に各々半田ボール１０，１１を
取り付けるエアリア・グリッド・アレイ・パッケージに
おいて、 上記第１面１の回路３裏面へ通じる如く、第２面２から
半導体チップ接続用の開口部１２を形成して、該開口部
１２で露呈した回路３裏面を半導体チップ接続用のパッ
ド６とすると共に、該開口部１２を介して半導体チップ
５と第１面１の回路３とを接続したことを特徴とする、
エアリア・グリッド・アレイ・パッケージ。Wherein the first surface 1 and the second surface 2 of the insulating substrate A, to form a circuit 3, 4 separate not connected to each other, each face 1,
2 , pads 6 and 7 for connecting a semiconductor chip to one end of each circuit 3 and 4 , and pads 8 and 7 for attaching a solder ball to the other end .
9, each forming a semiconductor chip 5 and each surface 1 with,
2 are electrically connected to the semiconductor chip connection pads 6 and 7, and resin-molded, and the solder balls 10 and 11 are mounted on the solder ball mounting pads 8 and 9 on each surface 1 and 2 , respectively. Aerial grid array package
Then, from the second surface 2 so as to communicate with the back surface of the circuit 3 on the first surface 1
An opening 12 for connecting a semiconductor chip is formed.
The back surface of the circuit 3 exposed in step 12 is
6 and a semiconductor chip through the opening 12.
5 and the circuit 3 of the first surface 1 are connected.
Air rear grid array package. 【請求項４】絶縁性基板Ａの第１面１と第２面２に、互
いに接続しない独立した回路３，４を形成し、各面１，
２の各回路３，４の一端部に半導体チップ接続用のパッ
ド６，７を、他端部に半田ボール取付け用のパッド８，
９を各々形成して、搭載した半導体チップ５と各面１，
２の半導体チップ接続用パッド６，７とを電気的に接続
すると共に樹脂モールドし、かつ各面１，２の半田ボー
ル取付け用パッド８，９に各々半田ボール１０，１１を
取り付けるエアリア・グリッド・アレイ・パッケージに
おいて、 上記第１面１の回路３裏面へ通じる如く、第２面２から
半田ボール取付け用の開口部１３を形成して、該開口部
１３で露呈した回路３裏面を半田ボール取付け用のパッ
ド８とすると共に、該開口部１３内に、基板Ａの絶縁層
の厚み分に相当する導電性充填材１８を充填して、該充
填材１８に半田ボール１０を取付け 、かつ、第２面２の回路４裏面へ通じる如く、第１面１か
ら半導体チップ接続用の開口部１２を形成して、該開口
部１２で露呈した回路４裏面を半導体チップ接続用のパ
ッド７とすると共に、該開口部１２を介して半導体チッ
プ５と第２面２の回路４とを接続したことを特徴とす
る、 エアリア・グリッド・アレイ・パッケージ。Wherein the first surface 1 and the second surface 2 of the insulating substrate A, to form a circuit 3, 4 separate not connected to each other, each face 1,
2 , pads 6 and 7 for connecting a semiconductor chip to one end of each circuit 3 and 4 , and pads 8 and 7 for attaching a solder ball to the other end .
9, each forming a semiconductor chip 5 and each surface 1 with,
2 are electrically connected to the semiconductor chip connection pads 6 and 7, and resin-molded, and the solder balls 10 and 11 are mounted on the solder ball mounting pads 8 and 9 on each surface 1 and 2 , respectively. Aerial grid array package
Then, from the second surface 2 so as to communicate with the back surface of the circuit 3 on the first surface 1
An opening 13 for attaching a solder ball is formed.
13. The back surface of the circuit 3 exposed in step 13 is
And an insulating layer of the substrate A in the opening 13.
Is filled with a conductive filler 18 corresponding to the thickness of
The solder balls 10 are attached to the filler 18 and the first surface 1 is connected to the second surface 2 so as to be connected to the back surface of the circuit 4.
Forming an opening 12 for connecting a semiconductor chip from the
The back surface of the circuit 4 exposed in the part 12 is
And the semiconductor chip through the opening 12.
Wherein the loop 5 and the circuit 4 on the second surface 2 are connected.
That, Earia grid array package. 【請求項５】絶縁性基板Ａの第１面１と第２面２に、互
いに接続しない独立した回路３，４を形成し、各面１，
２の各回路３，４の一端部に半導体チップ接続用のパッ
ド６，７を、他端部に半田ボール取付け用のパッド８，
９を各々形成して、搭載した半導体チップ５と各面１，
２の半導体チップ接続用パッド６，７とを電気的に接続
すると共に樹脂モールドし、かつ各面１，２の半田ボー
ル取付け用パッド８，９に各々半田ボール１０，１１を
取り付けるエアリア・グリッド・アレイ・パッケージに
おいて、 上記第１面１の回路３裏面へ通じる如く、第２面２から
半田ボール取付け用の開口部１３を形成して、該開口部
１３で露呈した回路３裏面を半田ボール取付け用パッド
８とすると共に、該開口部１３内に、基板Ａの絶縁層の
厚み分に相当する導電性充填材１８を充填して、該充填
材１８に半田ボール１０を取付け 、かつ、上記第１面１の回路３裏面へ通じる如く、第２面
２から半導体チップ接続用の開口部１２を形成して、該
開口部１２で露呈した回路３裏面を半導体チップ接続用
のパッド６とすると共に、該開口部１２を介して半導体
チップ５と第１面１の回路３とを接続したことを特徴と
する、 エアリア・グリッド・アレイ・パッケージ。5. A first surface 1 and the second surface of the insulative substrate A 2, to form a circuit 3, 4 separate not connected to each other, each face 1,
2 , pads 6 and 7 for connecting a semiconductor chip to one end of each circuit 3 and 4 , and pads 8 and 7 for attaching a solder ball to the other end .
9, each forming a semiconductor chip 5 and each surface 1 with,
2 are electrically connected to the semiconductor chip connection pads 6 and 7, and resin-molded, and the solder balls 10 and 11 are mounted on the solder ball mounting pads 8 and 9 on each surface 1 and 2 , respectively. Aerial grid array package
Then, from the second surface 2 so as to communicate with the back surface of the circuit 3 on the first surface 1
An opening 13 for attaching a solder ball is formed.
13 is a pad for attaching a solder ball to the back surface of the circuit 3 exposed at 13.
8 and the insulating layer of the substrate A in the opening 13.
The conductive filler 18 corresponding to the thickness is filled, and the filling is performed.
The solder ball 10 is attached to the material 18 and the second surface is connected to the back surface of the circuit 3 on the first surface 1.
2, an opening 12 for connecting a semiconductor chip is formed.
The back surface of the circuit 3 exposed at the opening 12 is used for connecting a semiconductor chip.
Pad 6 and a semiconductor through the opening 12.
The chip 5 and the circuit 3 on the first surface 1 are connected.
To, Earia grid array package. 【請求項６】絶縁性充填材１８を、導電性樹脂またはメ
ッキ層とした、請求項１，４または５に記載のエアリア
・グリッド・アレイ・パッケージ。6. An insulating filler 18 is made of a conductive resin or a resin.
The air rear grid array package according to claim 1, 4 or 5 , wherein the package is a stick layer .
JP8219226A 1996-08-01 1996-08-01 AIRIA GRID ARRAY PACKAGE Expired - Fee Related JP2986413B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP8219226A JP2986413B2 (en) 1996-08-01 1996-08-01 AIRIA GRID ARRAY PACKAGE
US08/904,394 US6011694A (en) 1996-08-01 1997-08-01 Ball grid array semiconductor package with solder ball openings in an insulative base

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8219226A JP2986413B2 (en) 1996-08-01 1996-08-01 AIRIA GRID ARRAY PACKAGE

Publications (2)

Publication Number Publication Date
JPH1050884A JPH1050884A (en) 1998-02-20
JP2986413B2 true JP2986413B2 (en) 1999-12-06

Family

ID=16732185

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8219226A Expired - Fee Related JP2986413B2 (en) 1996-08-01 1996-08-01 AIRIA GRID ARRAY PACKAGE

Country Status (1)

Country Link
JP (1) JP2986413B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6285077B1 (en) * 1999-08-19 2001-09-04 Lsi Logic Corporation Multiple layer tape ball grid array package
US6410861B1 (en) * 1999-12-03 2002-06-25 Motorola, Inc. Low profile interconnect structure
KR100713928B1 (en) 2006-02-08 2007-05-07 주식회사 하이닉스반도체 Semiconductor chip package

Also Published As

Publication number Publication date
JPH1050884A (en) 1998-02-20

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