JP2981366B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP2981366B2 JP2981366B2 JP5144751A JP14475193A JP2981366B2 JP 2981366 B2 JP2981366 B2 JP 2981366B2 JP 5144751 A JP5144751 A JP 5144751A JP 14475193 A JP14475193 A JP 14475193A JP 2981366 B2 JP2981366 B2 JP 2981366B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- wiring
- film
- semiconductor device
- teos
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
- Drying Of Semiconductors (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置の製造方法
に関し、更に詳しくは、半導体基板上の配線により生じ
た凹凸を平坦化する、層間絶縁膜の形成方法に関するも
のである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming an interlayer insulating film for flattening unevenness caused by wiring on a semiconductor substrate.
【０００２】[0002]
【従来の技術】半導体素子の高密度化、高集積化にとっ
て配線を層間絶縁膜を挟んで３次元的に積層する技術は
不可欠なものである。特に、ロジック系のＵＬＳＩで
は、３層以上のＡｌ配線が要求される。また、この配線
の三次元化に伴って、増大する表面段差を制御して埋め
込み平坦化する技術が必要となってくる。2. Description of the Related Art A technique for three-dimensionally stacking wirings with an interlayer insulating film interposed therebetween is indispensable for increasing the density and integration of semiconductor elements. In particular, a logic ULSI requires three or more layers of Al wiring. In addition, as the wiring becomes three-dimensional, a technique for controlling an increasing surface step and performing burying and flattening is required.
【０００３】現在、Ａｌ配線、Ａｌ合金配線や高融点導
体をバリアメタルとした積層構造配線等の層間絶縁膜形
成法として、低温成膜が可能で、優れた埋め込み平坦性
を示すＴＥＯＳ（テトラ・エトキシ・シラン）−Ｏ
3（オゾン）系常圧ＣＶＤ法が、微細デバイスにおける
層間絶縁膜の平坦化技術として、極めて有望なプロセス
として検討されている。At present, as a method of forming an interlayer insulating film such as an Al wiring, an Al alloy wiring or a laminated structure wiring using a high melting point conductor as a barrier metal, a TEOS (tetra-metal oxide) film which can be formed at a low temperature and has excellent buried flatness can be obtained. Ethoxy silane) -O
3 (Ozone) -based atmospheric pressure CVD is being studied as a very promising process as a technique for planarizing an interlayer insulating film in a fine device.
【０００４】[0004]
【発明が解決しようとする課題】上記のような、例え
ば、積層構造配線において、図４（ａ）に示すように、
成膜時に優れた埋め込み平坦性を示すＴＥＯＳ−Ｏ3 系
常圧ＣＶＤ膜９を用いると下地材料依存性のため、例え
ば、Ａｌ−Ｓｉ−Ｃｕ合金１ａとＴｉＷ合金（又はＷＳ
ｉ合金）１ｂからなるメタルの積層構造の下層配線１と
その下のＢＰＳＧ膜（図示せず。）では成長速度が異な
るために良好な平坦化形状が得られない等の問題が発生
している。そのために、図４（ｂ）に示すように、単一
の下地を得るために、ＴＥＯＳ−Ｏ3系常圧ＣＶＤ膜９
を形成する前にプラズマＴＥＯＳ膜１０を形成してい
る。なお、図４は従来技術における積層構造配線を有す
る半導体装置の要部断面図である。As shown in FIG. 4 (a), for example, in a wiring having a laminated structure as described above,
When a TEOS-O 3 -based atmospheric pressure CVD film 9 having excellent buried flatness during film formation is used, it depends on the underlying material. For example, an Al—Si—Cu alloy 1a and a TiW alloy (or WS
Since the growth rate is different between the lower wiring 1 and the BPSG film (not shown) therebelow, there is a problem that a good flattened shape cannot be obtained, etc. . Therefore, as shown in FIG. 4B, in order to obtain a single base, a TEOS-O 3 -based normal pressure CVD film 9 is formed.
The plasma TEOS film 10 is formed before the formation. FIG. 4 is a cross-sectional view of a main part of a semiconductor device having a laminated structure wiring according to the related art.
【０００５】しかし、プラズマＴＥＯＳ膜１０上に形成
したＴＥＯＳ−Ｏ3 系常圧ＣＶＤ膜９は良好な埋め込み
特性が得られるが、シラン系絶縁膜やプラズマＴＥＯＳ
膜と比較して膜中に水分を多量に含んでいる。そのた
め、メタル間のコンタクト特性やトランジスタ特性に影
響を及ぼして、デバイスの製品歩留まりや信頼性を下げ
る要因となっている。[0005] However, although the TEOS-O 3 -based normal pressure CVD film 9 formed on the plasma TEOS film 10 can obtain a good embedding property, the silane-based insulating film and the plasma TEOS
The film contains a large amount of water as compared with the film. Therefore, it affects the contact characteristics between metals and the characteristics of transistors, which is a factor that lowers the product yield and reliability of devices.
【０００６】本発明は、より水分の含まない、膜質の向
上した、良好な埋め込み特性が得られる層間絶縁膜の形
成方法を提供することを目的とする。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming an interlayer insulating film containing less moisture, having improved film quality, and obtaining good filling characteristics.
【０００７】[0007]
【課題を解決するための手段】本発明の半導体装置の製
造方法は、配線による半導体基板上の凹凸を平坦化する
工程を有する半導体装置の製造方法に於いて、上記半導
体基板上に上記配線を設けた後、窒素を含む有機ソース
を用いたプラズマＣＶＤ法により上記配線の全面を被覆
するように第１絶縁膜を堆積する第１工程と、ＴＥＯＳ
−Ｏ3系常圧ＣＶＤ法により上記第１絶縁膜上の凹凸を
埋めるように第２絶縁膜を堆積する第２工程とを有する
ことを特徴とするものである。According to a method of manufacturing a semiconductor device of the present invention, there is provided a method of manufacturing a semiconductor device having a step of flattening irregularities on a semiconductor substrate by wiring, wherein the wiring is formed on the semiconductor substrate. Forming a first insulating film so as to cover the entire surface of the wiring by a plasma CVD method using an organic source containing nitrogen;
The -O 3 an atmospheric pressure CVD method is characterized in that a second step of depositing a second insulating film so as to fill the unevenness on the first insulating film.
【０００８】[0008]
【作用】上記本発明を用いて、窒素を含む有機ソースを
用いたプラズマ系絶縁膜（ＳｉＯ2 膜）を形成すること
によって、窒化された表面の絶縁膜が形成され、ＴＥＯ
Ｓ−Ｏ3 系常圧ＣＶＤ膜の膜質が改善される。According to the present invention, by forming a plasma-based insulating film (SiO 2 film) using an organic source containing nitrogen, an insulating film having a nitrided surface is formed.
The film quality of the S—O 3 -based normal pressure CVD film is improved.
【０００９】[0009]
【実施例】以下に、一実施例の基づいて本発明を詳細に
説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail based on one embodiment.
【００１０】図１は本発明の一実施例の半導体装置の製
造方法を説明する図であり、図２（ａ）乃至（ｃ）は本
発明の他の実施例の半導体装置の製造方法を説明する図
であり、図３は本発明の他の実施例の半導体装置の製造
方法を説明する図である。FIG. 1 is a diagram for explaining a method of manufacturing a semiconductor device according to one embodiment of the present invention. FIGS. 2A to 2C are diagrams illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention. FIG. 3 is a diagram illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention.
【００１１】図１に示すように、半導体基板（図示せ
ず。）上に下層配線１、例えば、Ａｌ−Ｓｉ−Ｃｕ合金
１ａ上にＴｉＷ合金又はＴｉＮ合金１ｂが形成され、表
面には凹凸が生じている。なお、本実施例においては、
下層配線１に積層構造配線を用いているが、Ａｌ配線、
Ａｌ合金配線等も適用可能である。As shown in FIG. 1, a lower wiring 1 is formed on a semiconductor substrate (not shown), for example, a TiW alloy or a TiN alloy 1b is formed on an Al—Si—Cu alloy 1a. Has occurred. In this embodiment,
Although a multilayer structure wiring is used for the lower wiring 1, an Al wiring,
Al alloy wiring or the like is also applicable.
【００１２】上記凹凸を平坦化するため、まず、下層配
線１上に、以下の条件下で、窒素を含む有機ソース系プ
ラズマＣＶＤ法により第１絶縁膜２を堆積する。ガスと
して、Ｏ2及び有機ソースを共に流量約５３０ＳＣＣＭ
で流し、圧力を約９．０Ｔｏｒｒとし、基板（図示ぜ
ず。）の設定温度を約３９０℃とし、Ｒｆパワーを約４
５０Ｗとし、第１絶縁膜２を形成する。また、有機ソー
スとして、液体ソース（室温）でＴＥＯＳと蒸気圧がほ
ぼ等しい材料が用いられる。具体的には、ヘキサメチル
ジシラザンや、トリメチルシリルジエチルアミン等が適
用可能である。これより、下層配線１の表面及び側面を
第１絶縁膜２で被覆する。In order to flatten the irregularities, first, a first insulating film 2 is deposited on the lower wiring 1 by an organic source plasma CVD method containing nitrogen under the following conditions. As a gas, O 2 and an organic source are used together at a flow rate of about 530 SCCM.
At a pressure of about 9.0 Torr, a set temperature of a substrate (not shown) of about 390 ° C., and an Rf power of about 4
The first insulating film 2 is formed at 50 W. As the organic source, a material having a vapor pressure substantially equal to that of TEOS in a liquid source (room temperature) is used. Specifically, hexamethyldisilazane, trimethylsilyldiethylamine, or the like can be used. Thus, the surface and side surfaces of the lower wiring 1 are covered with the first insulating film 2.
【００１３】次に、第１絶縁膜２上に、以下の条件下
で、ＴＥＯＳ−Ｏ3系常圧ＣＶＤ法により第２絶縁膜３
を堆積する。ガスとして、ＴＥＯＳ（キャリアＮ2 ）を
約２．０ＳＬＭ、Ｏ2を約７．５ＳＬＭ、Ｏ3濃度を約
５．０％とし、基板（図示ぜず。）の設定温度を約３８
０℃として、ＴＥＯＳ−Ｏ3系常圧ＣＶＤ法を行う。こ
れにより、第１絶縁膜２上に残っている凹凸を埋め、成
膜時においても、リフロー形状が得られる平坦化絶縁膜
が形成できる。Next, a second insulating film 3 is formed on the first insulating film 2 by a TEOS-O 3 system atmospheric pressure CVD method under the following conditions.
Is deposited. As the gas, TEOS (carrier N 2 ) is about 2.0 SLM, O 2 is about 7.5 SLM, O 3 concentration is about 5.0%, and the set temperature of the substrate (not shown) is about 38.
At 0 ° C., a TEOS-O 3 normal pressure CVD method is performed. As a result, the unevenness remaining on the first insulating film 2 is filled, and a flattened insulating film capable of obtaining a reflow shape can be formed even during film formation.
【００１４】その後、複合段差や厳しい下地段差を有す
る場合、図２に示すように、エッチバック法を用いて、
層間絶縁膜の平坦化を更に向上させることができる。ま
ず、図２（ａ）に示すように、窒素を含む有機ソース系
プラズマＣＶＤ法により第１絶縁膜２を堆積した後、第
１絶縁膜２上にＴＥＯＳ−Ｏ3系常圧ＣＶＤ法を用いて
第２絶縁膜３を堆積する。その後、更に有機シラノール
系ガラス４を塗布し、熱処理により硬化させる。Thereafter, when there is a composite step or a severe base step, as shown in FIG.
The planarization of the interlayer insulating film can be further improved. First, as shown in FIG. 2A, a first insulating film 2 is deposited by an organic source-based plasma CVD method containing nitrogen, and then a TEOS-O 3 -based normal pressure CVD method is used on the first insulating film 2. Then, a second insulating film 3 is deposited. Thereafter, an organic silanol-based glass 4 is further applied and cured by heat treatment.
【００１５】続いて、図２（ｂ）に示すように、エッチ
バックを行った後、有機ソースとしてＴＥＯＳ又は窒素
を含む有機ソースを用いて、上述のプラズマＣＶＤ法と
同じ条件下で、プラズマＣＶＤ法を行い、第３絶縁膜５
を形成することで平坦化絶縁膜形成ができる。Subsequently, as shown in FIG. 2B, after performing an etch-back, the plasma CVD is performed under the same conditions as the above-mentioned plasma CVD using an organic source containing TEOS or nitrogen as an organic source. The third insulating film 5
Is formed, a planarization insulating film can be formed.
【００１６】次に、図２（ｃ）に示すように、下層配線
１上の層間絶縁膜をなす絶縁膜２，３或は２，３，５を
選択的に除去し、スルーホール６を形成した後、上層配
線７を形成し、スルーホール６を介して、下層配線１と
上層配線７との電気的接続を図る。Next, as shown in FIG. 2C, the insulating films 2, 3 or 2, 3, 5 forming an interlayer insulating film on the lower wiring 1 are selectively removed to form a through hole 6. After that, the upper wiring 7 is formed, and the lower wiring 1 and the upper wiring 7 are electrically connected via the through hole 6.
【００１７】また、図３に示すように、スパッタ技術で
コンタクトの穴埋めができない場合に、スルーホール６
にプラグ８を形成して、配線１，７間の電気的接続を行
っても良い。As shown in FIG. 3, when the contact hole cannot be filled by the sputtering technique,
A plug 8 may be formed at the end to make electrical connection between the wirings 1 and 7.
【００１８】実際に、ＴＥＯＳ−Ｏ3系常圧ＣＶＤ膜の
下地材料に対する膜質を評価したところ、表１に示すよ
うに、下地がＳｉ基板やプラズマ−ＴＥＯＳ膜に比べ
て、窒素を含む有機ソース系プラズマ膜は膜中水分量は
少なく、膜質が大幅に改善されていることが分かる。When the film quality of the TEOS-O 3 -based atmospheric pressure CVD film with respect to the underlying material was actually evaluated, as shown in Table 1, the organic source containing nitrogen was lower than that of the Si substrate or the plasma-TEOS film as shown in Table 1. It can be seen that the system plasma film has a small amount of water in the film and the film quality is greatly improved.
【００１９】[0019]
【表１】 [Table 1]
【００２０】[0020]
【発明の効果】以上、詳細に説明したように、本発明を
用いることにより、サブハーフミクロンの配線を平坦化
する際、下地に窒素を含む有機ソースを用いたプラズマ
系絶縁膜を形成することで、下地にプラズマ−ＴＥＯＳ
絶縁膜を形成した場合と比較して、ＴＥＯＳ−Ｏ3系常
圧ＣＶＤ法により形成された絶縁膜の、膜中水分量が減
少する等の膜質を改善することができる。このことによ
って、膜中の水分によるメタル間のコンタクト特性やト
ランジスタ特性の劣化を抑制し、デバイスの製品歩留ま
りや信頼性を向上させることができる。As described above in detail, by using the present invention, it is possible to form a plasma-based insulating film using an organic source containing nitrogen as a base when planarizing sub-half micron wiring. Then, plasma-TEOS on the base
Compared with the case where the insulating film is formed, the quality of the insulating film formed by the TEOS-O 3 -based normal pressure CVD method, such as a decrease in the amount of moisture in the film, can be improved. As a result, deterioration of contact characteristics between metals and transistor characteristics due to moisture in the film can be suppressed, and product yield and reliability of the device can be improved.
【図１】本発明の一実施例の半導体装置の製造方法を説
明する図である。FIG. 1 is a diagram illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
【図２】本発明の他の実施例の半導体装置の製造方法を
説明する図である。FIG. 2 is a diagram illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention.
【図３】本発明の他の実施例の半導体装置の製造方法を
説明する図である。FIG. 3 is a diagram illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention.
【図４】従来技術における配線を有する半導体装置の要
部断面図である。FIG. 4 is a cross-sectional view of a main part of a semiconductor device having a wiring according to a conventional technique.
１ 下層配線 １ａ Ａｌ−Ｓｉ−Ｃｕ合金層 １ｂ ＴｉＷ合金層又はＷＳｉ合金層 ２ 第１絶縁膜 ３ 第２絶縁膜 ４ 有機シラノール系ガラス ５ 第３絶縁膜 ６ スルーホール ７ 上層配線 ８ プラグ DESCRIPTION OF SYMBOLS 1 Lower wiring 1a Al-Si-Cu alloy layer 1b TiW alloy layer or WSi alloy layer 2 First insulating film 3 Second insulating film 4 Organosilanol-based glass 5 Third insulating film 6 Through hole 7 Upper wiring 8 Plug
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 21/31 H01L 21/312 - 21/314 H01L 21/316 H01L 21/318 - 21/32 H01L 21/3205 H01L 21/321 H01L 21/3213 H01L 21/47 - 21/475 H01L 21/768 ──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int.Cl. 6 , DB name) H01L 21/31 H01L 21/312-21/314 H01L 21/316 H01L 21/318-21/32 H01L 21 / 3205 H01L 21/321 H01L 21/3213 H01L 21/47-21/475 H01L 21/768
Claims (1)
する工程を有する半導体装置の製造方法に於いて、 上記半導体基板上に上記配線を設けた後、窒素を含む有
機ソースを用いたプラズマＣＶＤ法により上記配線の全
面を被覆するように第１絶縁膜を堆積する第１工程と、 ＴＥＯＳ−Ｏ3系常圧ＣＶＤ法により上記第１絶縁膜上
の凹凸を埋めるように第２絶縁膜を堆積する第２工程と
を有することを特徴とする、半導体装置の製造方法。1. A method of manufacturing a semiconductor device, comprising the step of flattening irregularities on a semiconductor substrate by wiring, wherein the wiring is provided on the semiconductor substrate, and plasma CVD is performed using an organic source containing nitrogen. a first step of depositing a first insulating film so as to cover the entire surface of the wiring by law, the TEOS-O 3 based atmospheric pressure CVD a second insulating film so as to fill the unevenness on the first insulating film A method of manufacturing a semiconductor device, comprising: a second step of depositing.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5144751A JP2981366B2 (en) | 1993-06-16 | 1993-06-16 | Method for manufacturing semiconductor device |
| KR1019940010935A KR0149468B1 (en) | 1993-06-16 | 1994-05-19 | Manufacturing Method of Semiconductor Device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5144751A JP2981366B2 (en) | 1993-06-16 | 1993-06-16 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0714917A JPH0714917A (en) | 1995-01-17 |
| JP2981366B2 true JP2981366B2 (en) | 1999-11-22 |
Family
ID=15369533
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5144751A Expired - Lifetime JP2981366B2 (en) | 1993-06-16 | 1993-06-16 | Method for manufacturing semiconductor device |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP2981366B2 (en) |
| KR (1) | KR0149468B1 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100230365B1 (en) * | 1996-06-29 | 1999-11-15 | 윤종용 | Method for interlayer insulation film formatiom of semiconductor |
| KR100419878B1 (en) * | 1997-12-11 | 2004-05-20 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device |
| KR100659394B1 (en) | 2005-08-08 | 2006-12-19 | 삼성전자주식회사 | Method of forming insulating film and method of manufacturing semiconductor device using same |
-
1993
- 1993-06-16 JP JP5144751A patent/JP2981366B2/en not_active Expired - Lifetime
-
1994
- 1994-05-19 KR KR1019940010935A patent/KR0149468B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0714917A (en) | 1995-01-17 |
| KR0149468B1 (en) | 1998-12-01 |
| KR950001861A (en) | 1995-01-04 |
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