JP2981279B2 - Input/Output Circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE PRESENT EMBODIMENTS [Object of the Invention] (Field of Industrial Application) The present invention relates to an input/output circuit for transmitting signals between ICs via a transmission line.

(Prior Art) In recent years, as systems have become larger and faster, the demands on the LSIs that make up these systems are becoming increasingly severe. Specifically, they require high-speed operation, low power consumption, high density integration, etc. At present, there is no process that satisfies all of these demands, and it is difficult to find an LSI that meets the conditions.
I is desired.

When considering the CMOS process, it fully meets the two requirements of low power consumption and high density integration, and the current miniaturized CMOS is also increasing the internal operating speed of the IC. However, when configuring a large-scale system,
The operating speed of the entire system is limited by the signal transmission speed between ICs.

When transmitting signals between ICs, ECL circuits are superior to CMOS output circuits in terms of high-speed signal transmission. Therefore, when high speed is required, input and output are usually performed according to ECL logic to configure the system. In particular, BiCM, which forms CMOS elements and bipolar elements on the same chip, is
By using the OS process to construct the logic section with CMOS transistors and the input/output section with bipolar transistors, the logic section can be constructed with CMOS and the input/output circuits with ECL, making it possible to construct a system that operates at high speed.

However, when compared in the development phase, the BiCMOS process had problems such as a more complicated manufacturing process, lower yields, and a lower integration level of the created elements than the single CMOS process.

(Problem to be solved by the invention) In conventional CMOS ICs, when applied to large-scale, high-speed systems, a certain degree of high speed was achieved within the circuit, but the operating speed of the CMOS input/output circuits limited the operating speed of the entire system.

An object of the present invention is to provide an input/output circuit that performs high-speed signal transmission using a CMOS process.

[Configuration of the invention] (Means for solving the problem) In order to achieve the above object, an input/output circuit in which an output circuit of a first IC is connected to an input circuit of a second IC via a transmission line includes an output circuit of the first IC, which outputs a logic signal of a logical value as a current change, a P-channel transistor and an N-channel transistor are connected in series, the source electrodes of the P-channel transistor and the N-channel transistor are connected in common, the drain electrodes are connected to a first reference potential and a second reference potential, and the gate electrodes are connected to a first reference potential and a second reference potential.
and a transmission line connected between a common source terminal of the P-channel transistor and the N-channel transistor and the first IC output circuit.

(Function) The output circuit of the first IC has a circuit that outputs the logic signal of the logic circuit as a current change. This outputs a current-mode logic signal. The current output from this output signal is transmitted to the input circuit of the second IC via a transmission line. The input circuit of the second IC uses the drain electrodes of a P-channel transistor and an N-channel transistor connected in common as input terminals, and transmits a signal current depending on the difference in the logic value of the transmission signal to the second IC.

According to the present invention, it is possible to configure a circuit that defines the logic level of a transmission signal by current mode and simultaneously matches the impedance with the transmission line, so that high-speed operation is possible even in a CMOS input/output circuit. In addition, it is resistant to the variation in characteristics of the component elements that depends on the manufacturing process,
Lower power consumption can be achieved compared to ECL input/output circuits.
In addition, since it is easy to achieve matching termination with low impedance for a wide range of input currents, it is a configuration that makes it easy to achieve matching with the transmission line regardless of the input signal level. This realizes a CMOS input/output circuit that transmits high-speed signals between ICs via the transmission line.

(Embodiment) Hereinafter, an embodiment of the present invention will be described with reference to a configuration diagram.

FIG. 1(a) is a block diagram showing one embodiment (basic concept) of the present invention. The output circuit of the first IC constitutes a current push-pull circuit, and switches between the sinking and extracting of the output current according to the logic value of the logic signal of the logic circuit 11. The signal transmitted via the transmission line 7 is transmitted to the input circuit of the second IC. In the input circuit of the second IC, the common source electrodes of the N-channel transistor 8 and the P-channel transistor 9 are connected to the transmission line 7 as the input terminal of the input circuit of the second IC, and the respective gate electrodes are connected to the voltage source 6b or 6c which provides the gate potential. The drain electrode 5 of the N-channel transistor 8 and the
The drain electrode 4 of the channel transistor 9 transmits a logic signal to the second IC as an output terminal of the input circuit of the second IC.

Next, the operation of the circuit shown in Fig. 1(a) will be described. The current sources 1 and 2 are connected to the logic circuit 15.
The first IC outputs a current corresponding to the logic signal from the output terminal 10 to the transmission line 7. This current is transmitted to the input terminal of the second IC via the transmission line 7, and the N-channel transistor 8 is turned on in response to the logic signal.
and a common source electrode of P-channel transistor 9. As a result, a current corresponding to one of the logic signals is sent to the input terminal of the input circuit of the second IC via transmission line 7 and flows to output terminal 4 via transistor 9. A current corresponding to the other logic signal is drawn in via transmission line 7 and receives the current flowing from output terminal 5 of the second IC to transistor 8.

With this configuration, the CMOS input/output circuit transmits current-mode signals and simultaneously matches the impedance of the transmission line, thereby increasing the speed of signal input/output. Also, the input impedance seen from the common source electrode of the second IC circuit is 1.0 V for transistor 8.
The impedance of the output is almost constant for a wide range of input current values, so the change in the input impedance of the circuit relative to the input current can be reduced, and the impedance of the transmission line can be well matched. This is shown in Figure 1(b). The impedance of the transmission line and the output is almost constant for a wide range of input current values, so the change in the input impedance of the circuit relative to the input current can be reduced, and the impedance of the transmission line can be well matched.
Even if there is no impedance matching with the input impedance of the IC, it is possible to suppress the decrease in operating speed caused by the capacitive load.

Even if the input current from current source 1 or 2 changes significantly, there is almost no change in the common source electrode potential of transistors 8 and 9. The DC potential of output terminal 10 of the first IC becomes the common source potential of transistors 8 and 9 of the input circuit of the second IC.

A schematic diagram of another embodiment of the present invention is shown in Fig. 2. The main components of the configuration are similar to those of the circuit shown in Fig. 1(a), but a matching resistor 12 is connected to the output terminal 10 to achieve impedance matching between the transmission line and the first output circuit.

In this circuit configuration, the problem of the output impedance of the current sources 1 and 2 being high is improved, and by setting the matching resistor 12 to a value that matches the transmission line, reflection of the transmission signal in the first output circuit is suppressed, enabling faster signal transmission.

3 shows a specific example of the configuration of the matching resistor 12. It is made up of a series circuit of a resistor R and a capacitor C, and satisfies the following relationship.

CR>1/2πfc where fc is the frequency of the signal to be transmitted.

Next, an example of a circuit for realizing the present invention will be described.

FIG. 4 is a circuit diagram showing an example of a configuration corresponding to the output circuit of the first IC shown in FIG. 1(a).

The connection relationship of each element is as follows. Input terminals 18 and 19 receive differential signals from the logic circuit. Input terminals 18, 1
The transistors 14 and 15 have their source electrodes connected to the drain electrode of the transistor 13. The transistor 13 provides a current. The transistors 14 and 15 have their source electrodes connected to the drain electrode of the transistor 13.
The drain electrode of transistor 14 is connected to the drain of transistor 23,
The drain electrode of transistor 15 is commonly connected to the drain and gate electrodes of transistor 24, and the source electrode of transistor 24 is connected to reference potential 100.
0. Transistors 23 and 6, transistors 11 and 12, and transistors 24 and 32 each constitute a so-called current mirror circuit, and the drain electrodes of transistors 12 and 32 are connected together to form an output terminal 17. Similarly, transistors 24 and 20, transistors 21 and 22, and transistors 23 and 31 each constitute a current mirror circuit, and the drain electrodes of transistors 22 and 31 are connected together to form an output terminal
The number is 16.

Next, the operation of this circuit will be explained. Consider the case where the logic signal of the logic circuit is "L" at input terminal 18 and "H" at input terminal 19. At this time, no current flows through transistor 15, and a current provided by transistor 13 flows through transistor 14. This current passes through the current mirror circuit consisting of transistors 23 and 31 and becomes the drain current of transistor 31. Since no current flows through transistor 22, output terminal 16 operates in the direction of drawing in current from the transmission line. Conversely, transistors 23 and 6
And, through the current mirror circuit with transistors 11 and 12, output terminal 17 operates in the direction of pushing current out to the transmission line. When the logic signal of the logic circuit is input to input terminal 18 at "H" and input terminal 19 at "L", the opposite operating principle to the above is used, and output terminal 16 operates in the direction of drawing current from the transmission line.

FIG. 5 is a circuit diagram showing the input circuit of the second IC shown in FIG. 1(a).
The transistors 52, 53 and 54 form a current mirror circuit, and the drain electrode of the transistor 54 is connected to the drain electrode of the transistor 58.
The gate electrode of the transistor 58 is connected to the drain electrode of the transistor 59. The source electrode of the transistor 58 is connected to the source electrode of the transistor 56. The drain electrode of the transistor 56 is connected to the reference potential 110.
The gate electrode of the transistor 56 is connected to the gate electrode of the transistor 57, which is also connected to a voltage source 130. The drain electrode of the transistor 57 is connected to a reference potential 110.
and its source electrode is connected to the source electrode of transistor 59. The common source connection electrode of transistor 57 and transistor 59 is connected to an input terminal 70 of the circuit.
The drain terminal of the transistor 59 is connected to the drain terminal of the transistor 60 and is also connected to the gate terminal of the transistor 60, and the source electrode of the transistor 60 is connected to the reference potential 120.
5. The transistors 60 and 61 form a current mirror circuit, and the transistors 55 and
The drain terminals of the 61 and 71 are connected in common, and the output terminal of the circuit is
and is connected.

The operation of this circuit will now be described. When there is no input to the input terminal 70, the common gate electrode 130 of the transistors 56 and 57
These currents flow in the directions of transistors 58 and 59, respectively.
The circuit maintains equilibrium. As a result, ideally, equal currents would flow through the drain electrodes of transistors 55 and 61 that make up the output terminal 71 of the circuit, making the output terminal 71 undefined. However, when current is drawn from input terminal 70, the balance between transistors 57 and 59 is lost, the drain current of transistor 57 increases and the drain current of transistor 59 decreases. This causes the transistor current of transistor 61 to decrease, resulting in an output potential of "H" at output terminal 71.
Conversely, when a current is applied to the input terminal 70, the opposite operation to that described above occurs, and the drain current of the transistor 61 increases, causing the output potential of the output terminal 71 to go low.

In particular, when transmitting signals at high speed using this circuit,
The current value of the current source 80 may be set in accordance with the ratio of the channel lengths and widths of the transistors 56, 57, 58, and 59 so as to match with the transmission line.

FIG. 6 shows an embodiment of a circuit diagram for realizing an input circuit of a second IC different from that of FIG. 5, and is a circuit in which the input stage of the circuit shown in FIG. 5 is implemented as a differential input.

This circuit can be used to configure the input circuit of the second IC even when the logic signal from the transmission line is a differential signal. The operating principle is the same as that of the circuit shown in Figure 5. For example, a current is drawn from input terminal 170 and a current is drawn from input terminal 171.
When a signal is input in the direction that draws current to the drain of transistor 96, the drain current of transistor
The drain current of transistor 98 increases.
The drain current of the transistor 95 increases through the current mirror circuit formed by the transistors 92 and 93 or the transistors 94 and 95. As a result, the output terminal 172 is at the output potential "H".
In this particular case, transistors 90 and 91, transistors 92 and 93, and transistors 94 and 95 each constitute a current mirror circuit, and the current gain is doubled.

Fig. 7 is a circuit diagram of the circuit of Fig. 5 with an additional circuit added. The operating principle is the same as the circuit shown in Fig. 5, and the potential of the output terminal is given according to the change in the current input from the transmission line. With this configuration, the current gain is doubled compared to the circuit shown in Fig. 5.

Fig. 8 is a circuit diagram formed by adding an additional circuit to the circuit of Fig. 6. This also makes it possible to form an input circuit, and the current gain is doubled compared to the circuit of Fig. 6.

In the embodiment described above, the circuit configuration is CMOS.
However, the circuit can also be constructed using bipolar elements.

In addition, the CMOS input/output circuit explained here can also be used as a circuit to transmit ECL logic,
It is also possible to maintain compatibility with ECL circuits that are currently widely used in high-speed systems.

[Advantages of the Invention] As described above, according to the present invention, the output circuit includes a circuit that provides the logic value of a logic signal as a change in output current, and the logic value is defined by the current, so that the CMOS output circuit can transmit signals at high speed. Also, the input circuit can be configured with impedance matching for a wide range of transmission currents, so that
It is easy to match with the transmission line and enables high-speed circuit operation, making it possible to realize CMOS input/output circuits even in systems that require high speed.

[Brief description of the drawings]

Fig. 1 is a diagram for proving one embodiment of the input/output circuit of the present invention, Fig. 2 is a diagram showing another embodiment of the input/output circuit of the present invention, Fig. 3 is a diagram showing the matching circuit shown in Fig. 2, Fig. 4 is a diagram showing one embodiment of the output circuit of the present invention, Fig. 5 is a diagram showing one embodiment of the single-phase input circuit of the present invention, Fig. 6 is a diagram showing one embodiment of the differential input circuit of the present invention, Fig. 7 is a diagram showing another embodiment of the single-phase input circuit of the present invention, and Fig. 8 is a diagram showing another embodiment of the differential input circuit used in the present invention. 1, 2, 80 ... current source, 18, 19, 70, 170, 171 ... input terminal, 4,
5,10,16,17,71,172……Output terminal, 8,9,13,14,15,20,21,
22, 23, 24, 31, 32, 51-61, 90-98...MOS transistors,
7...transmission line, 6b, 6c, 36, 100, 110, 120, 130...voltage source,
11...Logic circuit, 12...Matching resistor.

Continued from the front page (72) Inventor: Shigeru Tanaka 1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa-ken Toshiba Research Laboratory, Ltd. (58) Field of investigation (Int.Cl. ⁶ , DB name): H03K 19/0175

Claims (3)

(57) [Claims] [Claim 1] An input/output circuit in which an output circuit of a first IC is connected to an input circuit of a second IC via a transmission line, comprising: an output circuit of the first IC in which a logic signal of a logical value is output as a current change; an input circuit in which a P-channel transistor and an N-channel transistor are connected in series, the source electrodes of the P-channel transistor and the N-channel transistor are connected in common, the drain electrodes are connected to a first reference potential and a second reference potential, and the gate electrodes are connected to a first voltage source or a second voltage source; and a transmission line connected between the common source terminal of the P-channel transistor and the N-channel transistor and the output circuit of the first IC. 2. The input/output circuit according to claim 1, wherein a matching resistor is connected to the output terminal of the output circuit of said first IC. [Claim 3] The input/output circuit according to claim 1, characterized in that the input circuit of the first IC is an input circuit in which the drain electrodes of the P-channel transistor and the N-channel transistor are connected to a current-voltage conversion circuit between the first reference potential and the second reference potential.