JP2980853B2 - Apparatus and method for estimating performance of integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit performance estimating apparatus and method for estimating an area, an operating speed, and power consumption of an integrated circuit at a register transfer level designing stage.

[0002]

2. Description of the Related Art In recent years, with the rapid spread of portable information devices such as portable telephones and portable terminals, low power consumption of LSIs has become an important issue. As a technique for reducing power consumption, there is an estimation technique for estimating power consumption when designing an LSI.

Conventionally, power consumption of an LSI has been estimated by:
Power consumption analysis tools have been used for logic circuits after logic design by manual or logic synthesis, or logic circuits back-annotated with physical information after layout design.

Japanese Patent Application Laid-Open No. 7-160748 discloses a hardware description language (hereinafter referred to as HDL) before logic design.
Abbreviated. ) Is disclosed. This is a method of identifying a description unit of the HDL, calculating a delay time and a circuit scale for each description unit, and then multiplying the circuit scale by a clock frequency to calculate power consumption.

[0005]

However, the conventional method for estimating the power consumption of an LSI does not satisfy the performance requirements in a design flow based on performance estimation for a logic circuit at the time of logic design or layout design. To
Since the modification of the HDL description and the re-function verification and re-synthesis and the re-layout required for the modification are required, there is a problem that the design period is lengthened.

In the method for estimating power consumption of an LSI disclosed in Japanese Patent Application Laid-Open No. 7-160748,
When calculating the delay time and the circuit size of the operators included in the DL description, the configuration of the circuit for realizing the delay time is not taken into account. Therefore, the configuration in which the circuit area is small increases the delay time and the configuration in which the delay time is small. In this case, there is a problem that a design space expressed by a trade-off between the area and the delay time that the area becomes large cannot be searched, and an accurate estimation of a result of logic synthesis cannot be performed. Furthermore, since power consumption is calculated based only on the circuit scale, only average power consumption can be obtained, and there is a problem that low power consumption design cannot be performed based on the activation probability. .

[0007] As the scale of LSIs increases, the modification after detailed design requires enormous man-hours, and in the early stages of design, the area, operating speed, and power consumption in view of the detailed design of the post-process are highly accurate. It is necessary to make an estimate.

In view of the above problems, an object of the present invention is to make it possible to estimate the area, operation speed, and power consumption of an LSI at an early stage of a design stage.

[0009]

In order to achieve the above object, the present invention calculates an activation probability of a functional component in an integrated circuit at a register transfer level, and calculates a circuit area, an operation speed, and power consumption. To satisfy each prescribed performance,
A logic macro is selected from a logic macro library and assigned to each functional component.

[0010] A first integrated circuit performance estimating apparatus according to the present invention.
Location is design information of a register transfer level in an integrated circuit comprising a plurality of functional components is input, a connection information converting means for converting the design information in the connection information of the plurality of functional components are connected to each other, each of said function the activation probability of parts required
Activation probability setting means for setting the obtained activation probability for each of the functional components; and a logic macro for storing a plurality of logic macros having the same function but different circuit configurations and realizing the respective functional components. Library, calculate the area, operation speed, and power consumption for each of the functional components of the integrated circuit,
Macro allocating means for respectively selecting a logic macro from the logic macro library so as to satisfy a predetermined performance of the integrated circuit based on a calculation result, and allocating the selected logic macro to each functional component; and the macro allocating means And an assignment information output means for outputting the logic macros assigned by (1) as assignment information .

According to the first integrated circuit performance estimation device,
The logic macro library has the same function and a different circuit configuration, and stores a plurality of logic macros for realizing the functional components. The macro allocating means assigns the logical macro to each functional component so as to satisfy a predetermined performance. Assign. On the other hand, if the predetermined performance is not satisfied, RT
The HDL description of L can be changed. The activation probability setting means receives an activation probability of a bit of an input signal input to each functional component or an activation probability of a bit of an output signal output from the functional component, and determines the activation probability for each device.
Since it is set as a functional component , power consumption can be reduced in accordance with an actual circuit.

In the first device for estimating the performance of an integrated circuit,
The macro allocating unit is configured to generate, for each of the functional components, an allocation candidate list that is a list of assignable logical macros among a plurality of logical macros stored in the logical macro library. And a macro selection unit that selects a logic macro that minimizes the value of the performance evaluation function from the allocation candidate list, and an area and an operation speed for each of the functional components of the integrated circuit based on the selected logic macro. A performance estimating element calculating unit for calculating a performance estimating element composed of power consumption; and a performance estimating unit for calculating the performance evaluation function based on the performance estimating element calculated by the performance estimating element calculating unit and outputting the function to the macro selecting unit. It is preferable to have

In a first integrated circuit performance estimation device,
The logic macro includes a gate number calculation formula for calculating the number of gates from the bit width of the logic macro, a delay calculation formula for calculating the delay time of the logic macro from the bit width, and a moving charge amount per bit. It is preferable to have.

A second integrated circuit performance estimating apparatus according to the present invention.
Location includes a logical macro library that stores a plurality of logical macro having a gate, a connection information input means for connection information is input of the integrated circuit using the logical macro, each activity for each logical macro Activation probability information input means for inputting activation probability information representing activation probability; circuit area calculating means for calculating an area of the integrated circuit from a sum of the gate numbers of the respective logic macros; Virtual wiring delay calculating means for calculating a virtual wiring connecting the logic macros to each other based on an area of the integrated circuit, and calculating a delay time of the virtual wiring from a wiring length, a wiring resistance, and a wiring capacitance in the virtual wiring; Operating speed calculating means for calculating an operating speed of the integrated circuit from a delay time of each of the logic macros and a delay time of the virtual wiring; And a power consumption calculation means for calculating power consumption from the wiring capacitance and mobile charge amount per bit of the logic macro and the activation probability.

According to the second integrated circuit performance estimation device,
The circuit area calculation means calculates the area of the integrated circuit from the total number of gates, and the virtual wiring delay calculation means calculates virtual wiring connecting the logic macros to each other based on the calculated circuit area. Since the delay time of the virtual wiring is calculated from the wiring length, the wiring resistance, and the wiring capacitance, not only the logic part of the circuit but also the wiring delay and the weighted capacitance can be obtained.

A method for estimating the performance of a first integrated circuit according to the present invention
The method is intended for a method for estimating the performance of an integrated circuit at a register transfer level, comprising a plurality of functional components, and having a same function but a different circuit configuration, and storing a plurality of logic macros for realizing the functional components. A logic macro library preparation step of preparing a macro library; and a connection information conversion step of receiving design information at a register transfer level of the integrated circuit and converting the design information into connection information for connecting the plurality of functional components. , determined the activation probability for each functional component
An activation probability setting step of setting the obtained activation probability for each of the functional components ; and calculating an area, an operation speed, and power consumption for each of the functional components of the integrated circuit. A macro assignment step of selecting a logic macro from the logic macro library to satisfy the performance of the above, and assigning the selected logic macro to each of the functional components, and a logic macro assigned to each of the functional components as assignment information. have an allocation information output step of outputting
You.

According to the first method for estimating the performance of an integrated circuit,
A logic macro library having a plurality of logic macros having the same functions and different circuit configurations and realizing the functional components is prepared in advance, and each functional component is designed to satisfy a predetermined performance in the macro allocating process. Assign a logic macro to it. On the other hand, if the predetermined performance is not satisfied, the HDL description of the RTL can be changed before performing the logic synthesis. Further, in the activation probability setting step, the activation probability of the bit of the input signal input to each functional component or the activation probability of the bit of the output signal output from the functional component is set for each functional component. And low power consumption can be achieved.

In a first integrated circuit performance estimation method,
The macro allocating step is an allocation candidate list creating step of creating, for each of the functional components, an allocation candidate list that is a list of assignable logical macros among a plurality of logical macros stored in the logical macro library. When,
A performance evaluation function creating step of creating a performance evaluation function for each functional component; and a logic macro selecting step of selecting a logic macro that minimizes the value of the performance evaluation function from the allocation candidate list for each of the functional components. A performance estimation step of estimating the performance of the integrated circuit by calculating an area, an operation speed, and power consumption of the integrated circuit; and a performance determination of determining whether the estimated performance satisfies a predetermined performance. And a performance evaluation function adjusting step of adjusting the performance evaluation function when the estimated performance does not satisfy the predetermined performance, and selecting the logic macro until the estimated performance satisfies the predetermined performance. It is preferable to include an iterative process of repeating a process, the performance estimation process, the performance determination process, and the performance evaluation function adjustment process .

In a first method for estimating the performance of an integrated circuit,
The performance evaluation function of the performance evaluation function creating step has a weighted parameter added thereto, and has a weighted capacity which is a product of the number of gates, a delay time, an activation probability and a capacity, and the performance evaluation function adjustment The step exists on the critical path when the predetermined performance is not satisfied with respect to any of the area, operation speed, and power consumption of the integrated circuit including the functional components realized by the selected logic macro A delay time adjusting step of adjusting the performance evaluation function by changing a delay time weighting parameter of the performance evaluation function in the functional component to be executed, and a functional component having a high activation probability on a path other than the critical path. A capacity for adjusting the performance evaluation function by changing a weighting parameter of a weighted capacity of the performance evaluation function And settling step, preferably includes a gate speed adjusting step of adjusting said performance evaluation function by changing the weighting parameter of the number of gates in the performance evaluation function in the remaining functional components.

A method for estimating the performance of a second integrated circuit according to the present invention
The method comprises the steps of: inputting connection information of an integrated circuit constituted by using a plurality of logic macros having gates; and inputting activation probability information representing activation probabilities for the respective logic macros. An activation probability information inputting step, a circuit area calculating step of calculating an area of the integrated circuit from a sum of the gate numbers of the respective logic macros, and a virtual wiring connecting the logic macros to each other based on the circuit area. A virtual wiring delay calculating step of estimating and calculating a delay time of the virtual wiring from a wiring length, a wiring resistance, and a wiring capacitance in the virtual wiring; and calculating the delay time of each logical macro and the delay time of the virtual wiring. An operation speed calculation step of calculating an operation speed of the integrated circuit; an activation probability of each of the logic macros; a moving charge amount per bit of the logic macro; And a power calculating step of calculating a power consumption and a capacity.

According to the second integrated circuit performance estimation method,
In the circuit area calculation step, the area of the integrated circuit is calculated from the sum of the number of gates, and in the virtual wiring delay calculation step, the virtual wiring connecting the logic macros to each other is estimated based on the circuit area, and the wiring length and the wiring in the virtual wiring Since the delay time of the virtual wiring is calculated from the resistance and the wiring capacitance, not only the logic part of the circuit but also the wiring delay and weighted capacitance can be obtained.

In a second integrated circuit performance estimation method,
A logic macro arrangement for setting a square region having the circuit area calculated in the circuit area calculation step between the circuit area calculation step and the virtual wiring delay calculation step, and arranging the logic macro in the square area that it comprises a process
Is preferred.

In a second method for estimating the performance of an integrated circuit,
The power consumption calculating step includes calculating the amount of mobile charge per bit of the logic macro and an activation probability that each bit of an input signal or an output signal of the logic macro in the integrated circuit is activated. comprise a step of calculating an average movement amount of charge logic macro, and a step of calculating the power consumption of the logic macro and a operating speed of the power supply voltage and circuit during operation of said average moving amount of charge the integrated circuit
Is preferred.

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) A first embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a functional block diagram of an apparatus for estimating the performance of an integrated circuit at a register transfer level according to a first embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a logic macro for storing a logic macro for realizing a functional component including an operator such as a register, an adder, or a multiplier, which is a component of an integrated circuit of a register transfer level (hereinafter abbreviated as RTL). Library. The logic macro library 1 stores a plurality of logic macros having the same function for each functional component and different circuit configurations. Reference numeral 2 denotes a performance request file in which predetermined target values of the circuit area, operation speed, and power consumption are set. Reference numeral 3 denotes a connection information conversion unit which receives a file in which the RTL design information 10 is described using HDL and converts the RTL design information into connection information of functional components such as registers and operators. Reference numeral 4 denotes activation probability setting means for setting the activation probability of each functional component in connection information. Numeral 5 is a macro allocating means for selecting a logical macro corresponding to each functional component so as to satisfy a predetermined performance given from the performance request file 2. The macro allocating means 5 includes an allocation candidate list creator 51 that creates a list of logical macros to be assigned to each functional component from the logical macro library 1, and an appropriate logical macro from the created assignment candidate list. It comprises a macro selection unit 52 to be selected, and a performance estimating unit 53 that calculates and estimates the circuit area, operation speed, and power consumption using the selected logic macro. Reference numeral 6 denotes assignment information output means for outputting the assignment result of the macro assignment means 5 as assignment information.

Hereinafter, the operation of the integrated circuit performance estimating apparatus configured as described above will be described with reference to the drawings.

FIG. 2 is a flow chart showing a performance estimation method in the integrated circuit performance estimation device according to the first embodiment.
It is assumed that a logic macro library 1 storing logic macros for realizing functional components including operators such as registers, adders, and multipliers, which are components of the RTL circuit, is prepared in advance.

As shown in FIG. 2, first, in the connection information conversion step ST1, the R input to the connection information conversion means 3 is input.
The TL design information 10 is converted into connection information of functional components such as registers and operators, and is output to the activation probability setting means 4.

Next, in the activation probability setting step ST2, the activation probability setting means 4 stochastically activates each bit of each functional component from the activation probability of the input pin of the logic circuit given by the designer. The activation probability is obtained, and the activation probability is set for each functional component in a vector representation of bits. For example, 2
In the case of an input AND, assuming that the probability that the output signal becomes 1 is P1, P1 is (activation probability of one input ÷ 2) × (activation probability of the other input ÷ 2), and the activation probability is (1-P1)
× P1 × 2. The activation probabilities of the 4-bit input pins are (1,1,1,1) and (1,1,1,2), respectively.
In the case of (1, 0.5), the activation probability of the two-input AND is (0.375, 0.375, 0.375, 0.22). After that, the connection information of the functional component for which the activation probability has been set is transferred to the macro allocating unit 5.
Output to

Next, in a performance estimation and allocation step ST3 as a macro allocation step, the allocation candidate list creating section 51 in the macro allocation means 5 can allocate each functional component from the logical macro library 1, ie, each functional component. Are selected, and an assignment candidate list is created. Thereafter, the macro selecting unit 52 sequentially evaluates whether or not the logical macros in the allocation candidate list satisfy the performance requirements described in the performance requirement file 2 in the performance estimating unit 53, and determines an optimal logical macro from the evaluation result. select.

Next, in the assignment information output step ST4, the assignment information output means 6 outputs the selected logic macro to the result storage file as an assignment result.

FIG. 3 shows information possessed by each logic macro stored in the logic macro library 1. The logic macro is a name 11 of the logic macro and a function 1 of the logic macro.
2, a gate number calculation function 13 as a logic macro gate number calculation formula, a delay calculation function 14 as a logic macro delay calculation formula, and a moving charge amount 15 per bit of the logic macro. When the logic macro is a register, the logic macro further has a setup time 16 and a moving charge amount 17 due to a clock.

FIG. 4A is a graph showing the relationship between the bit width of the logic macro and the number of gates, and FIG. 4B is a graph showing the relationship between the bit width of the logic macro and the delay time. The gate number calculation function 13 can be expressed as a linear function of the bit width as shown by straight lines 18a and 18b shown in FIG. On the other hand, the case where the delay calculation function 14 can be expressed as a linear function of the bit width like a straight line 19a shown in FIG.
(B) may be a constant irrespective of the bit width like the straight line 19b. Arithmetic operators are the former linear function type, and binary logical operators and registers are the latter constant type.

In general, the power consumption by one hardware resource can be obtained by the following formula: power consumption = activation probability × capacity × square of power supply voltage × clock frequency (1).

The power consumption of the logic macro in this embodiment is calculated by using the activation probabilities of all the input and output signals of the logic macro and the amount of mobile charge per bit obtained from the logic macro library 1 using the following equation (1). Activation probability of ×
The calculation is performed by replacing the average moving charge amount per unit time represented by the term of the capacity with the equation (2) as a weighted capacity.

Activation probability × capacity = weighted capacity = Σ (activation probability of bit i) × moving charge amount per bit (2) where i represents a positive integer.

Here, the activation probability of the bit i in the equation (2) depends on the type of the logic macro. For example, when the output signal has a bit width as in a register, a logical operation, or an arithmetic operation, the activation probability of the output signal is used. on the other hand,
When the output signal is one bit as in the comparison operation, the one having the larger activation probability of the two input signals is used.

The amount of mobile charges per bit set in the logic macro library 1 is obtained by, for example, realizing a logic macro using, for example, an 8-bit logic circuit and performing a simulation with the activation probability of an input signal being 1. Ask for it.

The power consumption of the register is obtained as the sum of the power consumption when the input signal changes and the power consumption by the clock. That is, the power consumption when the input signal changes is obtained by using the activation probability of the output signal.
Using the moving charge amount 17 by the clock obtained from
(The amount of mobile charge × the square of the power supply voltage × the clock frequency).

The operation of the macro allocating means 5 shown in FIG. 1 will be described below with reference to the drawings.

FIG. 5 is a flowchart showing details of the performance estimation and allocation step ST3 shown in FIG. As shown in FIG.
In the assignment candidate list creation step ST31, the assignment candidate list creation unit 51 creates an assignment candidate list by selecting a corresponding logic macro for each functional component of the integrated circuit at the register transfer level from the logic macro library 1,
Register in the allocation candidate table.

FIG. 6 shows a logical macro targeted by the present apparatus and an assignment candidate table created by the assignment candidate list creating section 51. The logic macro 20 shown in FIG. This is an 8-bit addition logic macro for adding the result S and outputting the result S. The table shown in FIG. 6B is an assignment candidate table for the logic macro 20.

Here, with respect to the addition of the logic macros 20 shown in FIG. 6A, the logic macro library 1 defines rpl (ripple carry adder) and cla (carry look Ahead adder) is obtained. As a result, FIG.
The names 21, the number of gates 22, the delay 23 and the weighted capacity 24 of rpl and cla are stored in the allocation candidate table shown in FIG. The gate number 22 and the delay 23 are obtained by substituting the gate number into the gate number calculation function 13 and the delay calculation function 14 of each logic macro shown in FIG. The weighted capacity 24 is obtained using equation (2). At this time, the delay 23 obtained by the gate number calculation function 13
Is not registered in the allocation candidate table when the operation speed exceeds the operation speed given from the performance request file 2.

Next, in the performance evaluation function creation step ST32, the allocation candidate list creation unit 51 including the performance determinant calculation unit creates a performance evaluation function of each logic macro for each logic macro. The performance evaluation function F is represented by the following equation (3).

F = K 1 · number of gates · a + K 2 · delay · b + K 3 · weighted capacity · c (3) where K 1, K 2, and K 3 are designers for terms of the number of gates, delay, and weighted capacity. Is a weighting parameter specified, and priority can be given to the area, the operation speed, or the power consumption for the performance request. Here, a, b and c are scaling factors for digit alignment of each term.

The allocation candidate list creating section 51 does not necessarily need to include a performance determining element calculating section, but may be provided in the macro allocating means 5.

Next, in the logic macro selection step ST33, the macro selection unit 52 shown in FIG. 1 makes the logic macro which minimizes the value of the performance evaluation function F from the assignment candidate list created for each functional component. Select each.

Next, in the performance estimation step ST34, if the logic macro selected from the allocation candidate list here is referred to as a temporary allocation macro, the performance estimation unit 53 After calculating the number of gates, the operation speed, and the power consumption, in a determination step ST35, it is determined whether or not the performance requirement specified in the performance requirement file 2 is satisfied. The number of gates of the circuit is obtained as the sum of the number of gates of the provisionally allocated macro. The path delay is obtained by using the sum of the delays of the temporary allocation macros on the path between the registers, and the maximum value of the path delay is used as the operation speed of the circuit. Further, the power consumption is obtained by substituting the weighted capacity, the power supply voltage, and the operation speed of the temporarily allocated macro into the following equation (4).
The power supply voltage is given by a designer.

Power consumption = {weighted capacity of logic macro × square of power supply voltage} operating speed (4)

If the predetermined performance requirement is satisfied, the provisionally allocated macro is allocated as an optimal logic macro, and the processing is terminated. If not, the performance evaluation function adjusting step ST36
, The weighting parameters K1 to K of the performance evaluation function F
After changing the number 3, the process is repeated from the logic macro selection step ST33 until the performance requirement is satisfied.

In the performance evaluation function adjusting step ST36,
The weighting parameters K1 to K3 of the performance evaluation function F shown in Expression (3) are changed for each functional component. That is,
A delay time adjusting step of increasing the delay weight K2 by a factor of (estimated operating speed / required operating speed) for a functional component existing on a critical path exceeding an operating speed given as a performance requirement for each term; A capacity adjusting step of increasing the weight K3 of the weighted capacity to (estimated power consumption / required power consumption) times for a functional component existing on a path that is not a critical path and having a high activation probability; To increase the weight K1 of the number of gates by a factor of (estimated area / required area). However, if the upper limits of K1, K2, and K3 are set in advance, and the weights of the evaluation functions of all the functional components exceed the range and the performance evaluation function F cannot be set, an error is determined in the error determination step ST37. Judge and end.

As described above, according to the present embodiment, the logic macro library and each functional component constituting the circuit are designed to satisfy the performance requirements of the area, operation speed, and power consumption of the integrated circuit at the register transfer level. Providing a macro selector and a performance estimator for selecting a logic macro that minimizes the value of the performance evaluation function to perform high-precision performance estimation in consideration of a trade-off between area, operation speed, and power consumption it can.

A plurality of logic macros having the same function but different circuit configurations are stored in the logic macro library, and each logic macro has a gate number calculation function and a delay calculation function as functions of the bit width. Further, by having the amount of mobile charge per bit, the number of gates, delay, and weighted capacity of a logic macro that is a candidate for allocating appropriate functional components can be obtained from the bit width and the activation probability of each bit. In addition, the calculation of the performance evaluation function at the time of allocation can be performed easily and reliably.

The method for estimating the performance of an integrated circuit includes an allocation candidate list creation step, a performance evaluation function setting step, and a logic macro selection for selecting a logic macro that minimizes the value of the performance evaluation function from the allocation candidate list. Process and performance estimation process, and prioritize the area, operation speed, and power consumption by repeating the adjustment of the performance evaluation function until a predetermined performance requirement is satisfied, and the circuit area, delay, and A logic macro can be assigned in consideration of a trade-off with power consumption.

Further, by obtaining the weighted capacity of the logic macro from the amount of mobile charge per bit and the activation probability of each bit, the logic can be obtained even if the input signal includes a bit that changes frequently and a bit that hardly changes. The amount of mobile charges inside the macro can be accurately estimated, and the power consumption in RTL can be estimated.

Further, the functional components are divided into the functional components on the critical path, the functional components not on the critical path and having a high activation probability, and the remaining functional components, and the weighting parameters of the performance evaluation function when the logic macro is selected are changed. By doing so, it becomes possible to assign a logic macro in consideration of a trade-off between circuit area, delay, and power consumption for each functional component.

In the first embodiment, the activation probability is determined stochastically in the activation probability setting means or the activation probability setting step. However, a simulation using test data is performed in advance, and the RTL description is used. The activation probability may be obtained from the number of transitions of the variable.

(Second Embodiment) Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.

FIG. 7 is a functional block diagram of an apparatus for estimating the performance of an integrated circuit at the register transfer level according to the second embodiment of the present invention. In FIG. 7, reference numeral 1 denotes a logic macro library for storing logic macros for realizing functional components including operators such as registers, adders, and multipliers, which are components of an RTL integrated circuit. Reference numeral 30 denotes logic macro connection information obtained by converting RTL design information as connection information of functional components such as registers and operators, and reference numeral 31 denotes logic macro activation probability information for setting the activation probability of each functional component in the connection information. is there. Reference numeral 32 denotes an RTL integrated circuit performance estimating unit, which includes a circuit area calculator 321 for calculating a circuit area, a wiring estimator 322 for estimating circuit wiring, an operation speed calculator 323 for calculating an operation speed of the circuit, and a circuit. And a power consumption calculation unit 324 for calculating the power consumption of the power supply. The logic macro connection information 30 and the logic macro activation probability information 31
Is the same information as the information passed from the macro selection unit 52 to the performance estimation unit 53 shown in FIG.

The logic macro connection information 30 is stored in the performance estimation means 3
2 and a reference relationship with the logic macro stored in the logic macro library 1 is created.

Hereinafter, the operation of the integrated circuit performance estimating apparatus configured as described above will be described with reference to the drawings.

FIG. 8 is a flowchart showing a performance estimating method in the integrated circuit performance estimating apparatus according to the second embodiment.

As shown in FIG. 8, the connection information of the logic macro is input in advance in the connection information input step, and the logic macro activation probability information is input in the activation probability information input step.

First, in the circuit area calculation step ST11, the circuit area calculation section 321 sets the logic macro library 1
, The number of gates of each logic macro is calculated from the gate number calculation function stored in, and the area of the circuit is calculated by multiplying the sum of the number of gates by the first constant to obtain the estimated area of the circuit. The first constant is obtained by obtaining the relationship between the number of gates and the area from the accumulated data of the layout result.

Next, in a virtual wiring length calculating step ST12 as a virtual wiring delay calculating step, the wiring estimating section 322
Is calculated by estimating the virtual wiring length by multiplying the number of fan-outs of connections between logic macros by a second constant based on the estimated area. The second constant is obtained by obtaining the relationship between the number of fanouts, the area, and the wiring length from the accumulated data of the layout result. Thereafter, in a resistance and capacitance calculation step ST13 as a virtual wiring delay calculation step, a resistance and a wiring capacitance of a connection portion between the logic macros are obtained from the calculated virtual wiring length.

Next, in the operation speed calculation step ST14, the operation speed calculation section 323 sets the logical macro connection information 30
Search all paths of the path between the register, the path between the input pin and the register, the path between the register and the output pin, and the path between the input pin and the output pin, and pass through the path. A path delay which is a signal delay time is obtained. The path delay is the sum of the delay of the logic macro existing on the path, the setup time of the register, and the wiring delay. Here, the delay of the logic macro is obtained by substituting the bit width into the delay calculation function stored in the logic macro library 1, the setup time is obtained from the logic macro library 1, and the wiring delay is calculated in the resistance and capacitance calculation step. It is obtained by multiplying the wiring resistance and the wiring capacitance obtained in ST13.

Next, in the power consumption calculating step ST15, the power consumption calculating section 324 stores the logic macro activation probability information 31 and the one stored in the logic macro library 1.
The weighted capacity inside the logic macro is determined from the amount of mobile charge per bit. The activation probability of the logic macro is used as the activation probability of the connection information output from the logic macro, and the weighted capacitance of the wiring is obtained from the wiring capacitance obtained in the resistance and capacitance calculation step ST13. Using the following equation (5), the power consumption of the circuit is determined from the sum of the weighted capacitances of all the logic macros and wirings.

Power consumption = (Σweighted capacitance of logic macro + Σweighted capacitance of wiring) × square of power supply voltage ÷ operating speed (5) As described above, according to the present embodiment, the circuit area is calculated. By providing a circuit area calculation unit and a wiring estimation unit that calculates and estimates a virtual wiring length of a connection between logic macros based on the calculated area, it is possible to obtain not only the logic unit but also the wiring delay and weighted capacitance. Thus, the operation speed and the power consumption can be estimated with higher accuracy.

(Third Embodiment) Hereinafter, a third embodiment of the present invention will be described with reference to the drawings.

FIG. 9 is a flowchart showing a performance estimation method in the integrated circuit performance estimation device according to the third embodiment.
In FIG. 9, the same components as those described in the second embodiment are denoted by the same reference numerals, and description thereof will be omitted. The configuration of the integrated circuit performance estimating apparatus according to the present embodiment is the same as that of the integrated circuit performance estimating apparatus according to the second embodiment shown in FIG.

In the logic macro arranging step ST21 after the circuit area calculating step ST11, the circuit area calculating step ST1
A rectangular region having the estimated area obtained in step 1 is set, and the layout is determined so that the wiring length of the connection between the logic macros and the overlap of the logic macros are minimized in the rectangular region.

Next, in the virtual wire length calculating step ST12, it is assumed that there is a terminal connected to the center of the arranged logic macro, and the virtual wire length is obtained using a spanning tree. As described above, according to the present embodiment, by further including the logic macro arranging step of arranging the logic macro within the estimated area, the virtual wiring length of the connection between the logic macros can be more accurately obtained, and the higher accuracy can be obtained. It is possible to estimate the operating speed and power consumption.

[0073]

The performance estimation of the first integrated circuit according to the present invention
According to the apparatus, since the macro allocating means allocates the logic macro to each functional component so as to satisfy the predetermined performance, the performance of the RTL integrated circuit can be accurately estimated. Further, when the predetermined performance is not satisfied, the HDL description of the RTL can be changed before performing the logic synthesis, so that the efficiency of LSI design can be improved.

Further, since the activation probability is set in the connection information of the circuit based on the activation probability of the functional component, the power consumption can be reduced in accordance with the actual circuit.

In the first integrated circuit performance estimation device,
Macro allocating means for allocating a list of logical macros that can be allocated among a plurality of logical macros, and a macro selecting unit for selecting a logical macro that minimizes the value of the performance evaluation function from the allocation candidate list And a performance estimation element calculation unit that calculates a performance estimation element consisting of the area, operation speed, and power consumption of the integrated circuit based on the selected logic macro,
Having a performance estimating unit that calculates a performance evaluation function based on the performance estimating element and outputs it to the macro selection unit, prioritizes the area, the operating speed, and the power consumption; A logic macro can be reliably assigned in consideration of a trade-off between delay and power consumption.

In the first integrated circuit performance estimating apparatus,
Each logic macro has an equation for calculating the number of gates and an equation for calculating delay as a function of the bit width, and if it has the amount of mobile charge per bit, it can be appropriately determined from the bit width and the activation probability of each bit. Since the number of gates, delay, and weighted capacity of a logic macro that is a candidate for allocation of a functional component can be obtained, a performance evaluation function at the time of allocation can be easily and reliably calculated.

A second integrated circuit performance estimating apparatus according to the present invention
According to the arrangement, since the delay time of the virtual wiring is calculated from the wiring length, the wiring resistance, and the wiring capacitance in the virtual wiring, not only the logic part of the circuit but also the wiring delay and the weighted capacitance can be obtained. Alternatively, power consumption can be estimated with higher accuracy.

Method for Estimating Performance of First Integrated Circuit According to the Present Invention
According to the method, a logic macro is assigned to each functional component so as to satisfy a predetermined performance in the macro assignment step, so that the performance estimation of the RTL integrated circuit can be performed with high accuracy. Further, when the predetermined performance is not satisfied, the HDL description of the RTL can be changed before performing the logic synthesis, so that the efficiency of LSI design can be improved.

Further, since the activation probability is set in the connection information of the circuit based on the activation probability of the functional component, the power consumption can be reduced according to the actual circuit.

In the first method for estimating the performance of an integrated circuit,
A macro assignment step, an assignment candidate list creation step of creating an assignment candidate list that is a list of assignable logic macros among a plurality of logic macros; and a performance evaluation function creation step of creating a performance evaluation function for each functional component. A logic macro selection step of selecting a logic macro that minimizes the value of the performance evaluation function from the assignment candidate list for each functional component, calculating the area, operation speed, and power consumption of the integrated circuit, and A performance estimating step of estimating the estimated performance, a performance determining step of determining whether the estimated performance satisfies a predetermined performance, and a performance evaluation function adjusting step of adjusting a performance evaluation function when the predetermined performance is not satisfied. If it is provided, it is possible to assign priorities to the area, the operation speed, and the power consumption, and to allocate a logic macro in consideration of a trade-off between the area, the delay, and the power consumption for each functional component.

In the first method for estimating the performance of an integrated circuit,
The performance evaluation function adjustment step adjusts the performance evaluation function,
Delay time adjustment step, capacity adjustment step and gate number adjustment step
If the specified performance is not satisfied for any of the area, operation speed, and power consumption of the integrated circuit composed of the functional components realized by the selected logic macro, By dividing the functional components with high activation probability and the remaining functional components on the paths other than the critical path and changing the weighting parameters of the evaluation function when selecting the logic macro, the area, delay and consumption for each functional component A logic macro can be reliably assigned in consideration of a trade-off with power.

Method for Estimating Performance of Second Integrated Circuit According to the Present Invention
According to the method, the delay time of the virtual wiring is calculated from the wiring length, the wiring resistance, and the wiring capacitance in the virtual wiring, so that not only the logic part of the circuit but also the wiring delay and the weighted capacitance can be obtained. Alternatively, power consumption can be estimated with higher accuracy.

In the second method for estimating the performance of an integrated circuit,
Between the circuit area calculating step and the virtual wiring delay calculation step includes a logic macro placement step of setting the rectangular region having a circuit area which is calculated in circuit area calculating step, placing a logic macro said shaped region With this, the virtual wiring length of the connection between the logic macros can be determined more accurately.
The operation speed or power consumption can be estimated with higher accuracy.

In the second method for estimating the performance of an integrated circuit,
The power consumption calculation process determines the average level of logic macros per unit time.
Calculating the average moving charge amount and the power consumption of the logic macro
Calculating the weighted capacity of the logic macro from the amount of mobile charge per bit and the activation probability of each bit. Even when bits that do not exist are mixed, the amount of mobile charges inside the logic macro can be accurately calculated, so that the power consumption of the integrated circuit in the RTL can be reliably estimated.

[Brief description of the drawings]

FIG. 1 is a functional block diagram of a device for estimating the performance of an integrated circuit at a register transfer level according to a first embodiment of the present invention;

FIG. 2 is a flowchart showing a performance estimation method in the integrated circuit performance estimation device according to the first embodiment of the present invention.

FIG. 3 is a diagram showing a list of information held by a logic macro stored in a macro library in the performance estimation device logic of the integrated circuit according to the first embodiment of the present invention;

FIG. 4A is a graph showing the relationship between the bit width of a logic macro and the number of gates. (B) is a graph showing the relationship between the bit width of the logic macro and the delay time.

FIG. 5 is a flowchart showing details of performance estimation and allocation steps in the integrated circuit performance estimation method according to the first embodiment of the present invention.

FIG. 6A is a diagram illustrating an example of a logic macro in the integrated circuit performance estimating apparatus according to the first embodiment of the present invention. FIG. 2B is a diagram illustrating an example of an assignment candidate table in the integrated circuit performance estimation device according to the first embodiment of the present invention.

FIG. 7 is a functional block diagram of an apparatus for estimating the performance of an integrated circuit at a register transfer level according to a second embodiment of the present invention;

FIG. 8 is a flowchart illustrating a performance estimation method in an integrated circuit performance estimation device according to a second embodiment of the present invention.

FIG. 9 is a flowchart illustrating a performance estimation method in an integrated circuit performance estimation device according to a third embodiment of the present invention.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 logic macro library 2 performance request file 3 connection information conversion means 4 activation probability setting means 5 macro allocation means 51 allocation candidate list creation section (performance estimation element calculation section) 52 macro selection section 53 performance estimation section 6 allocation information output means 10 RTL design information 11 Name 12 Function 13 Gate number calculation function (Gate number calculation formula) 14 Delay calculation function (Delay calculation formula) 15 Mobile charge amount per bit 16 Setup time 17 Clock mobile charge amount ST1 Design information conversion step ST2 Activation probability setting step ST3 Performance estimation and assignment step (macro assignment step) ST4 Assignment information output step ST31 Assignment candidate list creation step ST32 Performance evaluation function creation step ST33 Logical macro selection step ST34 Performance estimation step ST35 Judgment step ST36 Performance evaluation function adjustment Process S 37 error determination step 30 logic macro connection information 31 logic macro activation probability information 32 performance estimating means 321 circuit area calculating section 322 wiring estimating section (virtual wiring delay calculating means) 323 operating speed calculating section 324 power consumption calculating section ST11 circuit area calculating Step ST12 Virtual wiring length calculation step (virtual wiring delay calculation step) ST13 Resistance and capacitance calculation step (virtual wiring delay calculation step) ST14 Operation speed calculation step ST15 Power consumption calculation step ST21 Logical macro arrangement step

──────────────────────────────────────────────────の Continuing on the front page (72) Yoshiyuki Kawakami 1006 Kazuma Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Kaoru Okazaki 1006 Kazama Kadoma Kadoma, Osaka Matsushita Electric Industrial Co. (72) Inventor Hattori Dai 1006 Kadoma, Kadoma, Osaka Pref. Matsushita Electric Industrial Co., Ltd. (56) References JP-A-7-28877 (JP, A) JP-A 8-235228 (JP, A) (58) Field surveyed (Int. Cl. ⁶ , DB name) G06F 17/50

Claims (8)

(57) [Claims] A connection information conversion unit configured to receive design information at a register transfer level in an integrated circuit including a plurality of functional components and convert the design information into connection information for connecting the plurality of functional components; Activation probability setting means for determining the activation probability of each functional component and setting the determined activation probability for each of the functional components; and a plurality of functional components having the same function and different circuit configurations to realize the functional components. A logic macro library storing logic macros of the following: calculating an area, an operation speed, and power consumption for each of the functional components of the integrated circuit; and calculating the logic so as to satisfy a predetermined performance of the integrated circuit based on the calculation result. A macro allocating means for selecting a logical macro from a macro library and allocating the selected logical macro to each of the functional components; Contact and an allocation information output means for outputting the Tagged logic macro as allocation information
The macro allocating means is configured to generate, for each of the functional components, an allocation candidate list which is a list of allocatable logical macros among a plurality of logical macros stored in the logical macro library. A creating unit; a macro selecting unit that selects a logic macro that minimizes the value of the performance evaluation function from the allocation candidate list; and an area and an operation for each of the functional components of the integrated circuit based on the selected logic macro. A performance estimating element calculating unit for calculating a performance estimating element consisting of speed and power consumption; and a performance for calculating the performance evaluation function based on the performance estimating element calculated by the performance estimating element calculating unit and outputting the function to the macro selecting unit. integrated times, characterized in that it has a estimator
Road performance estimation device. 2. The logic macro includes: a gate number calculation formula for calculating the number of gates from a bit width of the logic macro; a delay calculation formula for calculating a delay time of the logic macro from the bit width; The device for estimating the performance of an integrated circuit according to claim 1, further comprising a moving charge amount. 3. A logic macro library for storing a plurality of logic macros having gates, connection information input means for inputting connection information of an integrated circuit configured using the logic macros, and a logic macro library for each of the logic macros Activation probability information inputting means for inputting activation probability information representing the activation probability of the logic macro, and circuit area calculating means for calculating the area of the integrated circuit from the sum of the gate numbers of the logic macros. A virtual wiring that connects the logic macros to each other based on the area of the integrated circuit, and calculates a delay time of the virtual wiring from a wiring length, a wiring resistance, and a wiring capacitance of the virtual wiring. Means for calculating an operation speed of the integrated circuit from a delay time of each of the logic macros and a delay time of the virtual wiring; A performance estimating device for an integrated circuit, comprising: power consumption calculating means for calculating power consumption from the activation probability of a logic macro, the amount of mobile charge per bit of the logic macro, and the wiring capacitance. 4. A method for estimating the performance of an integrated circuit comprising a plurality of functional components and having a register transfer level, wherein the plurality of logic macros having the same function but different circuit configurations and realizing the respective functional components are stored. A logic macro library preparing step of preparing a logic macro library to be connected, and connection information conversion for inputting register transfer level design information of the integrated circuit and converting the design information into connection information for connecting the plurality of functional components. An activation probability setting step of determining an activation probability of each of the functional components, and setting the determined activation probability for each of the functional components; and an area, an operating speed, and a consumption of each of the functional components of the integrated circuit. After calculating the power, a logic macro is selected from the logic macro library so as to satisfy a predetermined performance of the integrated circuit, and the selected logic macro is And macro allocation step of allocating to each functional component, wherein includes an allocation information output step of outputting the logic macro assigned to each functional component as allocation information, the macro allocation step, they said to each functional component, An assignment candidate list creating step of creating an assignment candidate list, which is a list of assignable logic macros among a plurality of logic macros stored in the logic macro library, and creating a performance evaluation function for each functional component A performance evaluation function creating step; a logic macro selection step of selecting a logic macro that minimizes the value of the performance evaluation function from the assignment candidate list for each of the functional components; an area, an operation speed, and consumption of the integrated circuit Calculating the power to estimate the performance of the integrated circuit; and the estimated performance satisfies a predetermined performance. A performance determining step of determining whether or not to perform; a performance evaluation function adjusting step of adjusting the performance evaluation function if the estimated performance does not satisfy the predetermined performance; and A method for estimating the performance of an integrated circuit, comprising: an iterative step of repeating the logic macro selecting step, the performance estimating step, the performance determining step, and the performance evaluation function adjusting step until the performance is satisfied . 5. The performance evaluation function in the performance evaluation function creation step, wherein a weighting parameter is added to each of the performance evaluation functions, and the performance evaluation function has a weighted capacitance that is a product of the number of gates, delay time, activation probability, and capacitance, The performance evaluation function adjusting step, when the predetermined performance is not satisfied with respect to any of the area, operation speed, and power consumption of the integrated circuit including the functional components realized by the selected logic macro, A delay time adjusting step of adjusting the performance evaluation function by changing a weighting parameter of a delay time of the performance evaluation function in a functional component existing on the critical path; and an activation probability existing on a path other than the critical path and having an activation probability The performance evaluation function by changing the weighting parameter of the weighted capacity of the performance evaluation function in the functional component having high performance A capacity adjustment step of adjusting a claim, characterized in that it comprises a number of gates adjustment step of adjusting the performance evaluation function by changing the weighting parameter of the number of gates in the performance evaluation function in the remaining functional components 4 performance estimation method for an integrated circuit according to. 6. A connection information inputting step of inputting connection information of an integrated circuit constituted by using a plurality of logic macros having gates, and activation probability information indicating respective activation probabilities for the respective logic macros. An activation probability information inputting step; a circuit area calculating step of calculating an area of the integrated circuit from a sum of the gate numbers of the respective logic macros; and a virtual connection between the logic macros based on the circuit area. Calculating a wiring and calculating a delay time of the virtual wiring from a wiring length, a wiring resistance, and a wiring capacitance in the virtual wiring; and a delay time of each of the logic macros and a delay time of the virtual wiring. An operation speed calculation step of calculating an operation speed of the integrated circuit from: an activation probability of each logic macro and a moving charge per bit of the logic macro The performance estimation method for an integrated circuit, characterized in that it comprises a power calculating step of calculating power consumption from the wiring capacitance. 7. A square area having a circuit area calculated in the circuit area calculation step is set between the circuit area calculation step and the virtual wiring delay calculation step, and the logic macro is set in the square area. 7. The method for estimating the performance of an integrated circuit according to claim 6, further comprising a logic macro placement step of placing. 8. The power consumption calculating step includes calculating a moving charge amount per bit of the logic macro and an activation probability of activating each bit of an input signal or an output signal of the logic macro in the integrated circuit. Calculating the average amount of mobile charge of the logic macro per unit time; calculating the power consumption of the logic macro from the average amount of mobile charge, the power supply voltage during operation of the integrated circuit, and the operation speed of the circuit performance estimation method for an integrated circuit <br/> according to claim 6 or 7, characterized in that it comprises and.