JP2976724B2 - Semiconductor device having MOS capacitor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a MOS capacitor.

[0002]

2. Description of the Related Art A high surge voltage or power supply voltage is applied to a vehicle-mounted semiconductor device such as a microcomputer for controlling a vehicle engine. Therefore, MOS integrated in these semiconductor devices
It is desirable that the capacitor has a higher withstand voltage than a normal working voltage.

Conventionally in order to improve this problem, as shown in FIG. 8, MO high concentration semiconductor region surface by thermal oxidation
In the step of forming the gate electrode 91 of the S transistor 9, thermal oxidation is simultaneously performed to form an insulating film 92 for a MOS capacitor, and the insulating film 92 is formed to be thicker than the gate insulating film 93 of the MOS transistor 9. I have. If a higher dielectric strength is required, the gate insulating film 9 may be used.
The insulating film 92 was formed separately from the insulating film 92.

[0004]

However, in the method of FIG. 8 described above, there is a limit to the effect of improving the withstand voltage under the current situation where the gate insulating film 93 is becoming thinner. In addition, when both insulating films are manufactured in separate steps, the number of steps increases,
There was a problem such as a decrease in yield.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a semiconductor device having a MOS capacitor capable of improving withstand voltage while avoiding problems such as an increase in steps and a decrease in yield. And

[0006]

According to a first aspect of the present invention, there is provided a semiconductor device having a MOS capacitor, comprising an insulating layer on a semiconductor substrate.
Separated semiconductor layer formed by insulator with insulator
A semiconductor region which is, a plurality of MOS electrodes disposed respectively through said semiconductor region surface insulating film, and a contact electrode formed on each said half <br/> conductor region surface
MOS capacitor having the same and the MOS capacitor
Are formed in the semiconductor regions other than the respective semiconductor regions in which
In a semiconductor device having a MOS capacitor including a formed MOS transistor , the first semiconductor region
A connecting conductor of the second of the contact electrode of the second of said semiconductor region surface connected to the first of said MOS electrode on the first semiconductor region formed independently of said first semiconductor region surface wherein formed between the contact electrode and the second of said MOS electrode on the second semiconductor region first of
Provided and the series connection MOS capacitor, said semiconductor region
That is, a region adjacent to the insulating layer is sandwiched between the insulating films.
It is characterized by having a higher impurity concentration than a region facing the MOS electrode .

[0007]

[0008]

[0009]

In the first invention, the contact electrode of the first semiconductor region is used as the first electrode of the capacitor, and the MOS electrode of the second semiconductor region is used as the second electrode of the capacitor.
Then, the MOS electrode on the first semiconductor region and the contact electrode on the second semiconductor region are connected by a connection conductor.

In this case, both MOS capacitors are connected in series, and the withstand voltage can be doubled.
Of course, three or more MOS capacitors can be connected in series in the same connection form as described above, and the withstand voltage can be further improved.
In particular, in the connection type according to the present invention, the conduction type immediately below both MOS electrodes is the same (that is, when one is in the accumulation mode, the other is in the accumulation mode, and when one is in the inversion mode, the other is in the inversion mode. Therefore, both MOS capacitors can have the same structure, the resistance value does not increase, and the capacity design of both MOS capacitors becomes easy. Change
In the semiconductor region, the region adjacent to the insulating layer
Higher impurity than the region facing the MOS electrode across the film
Concentration, the semiconductor region is adjacent to the insulating layer.
The occurrence of crystal defects caused by heavy metals in the region
This crystal defect reduces the breakdown voltage of the insulating film adjacent to it.
It is possible to suppress the reduction.

As a result, since each MOS capacitor bears the breakdown voltage almost equally, a high breakdown voltage can be achieved as a whole, and a semiconductor device having a MOS capacitor without complicating the process can be realized. Can be .

However, when such MOS electrodes are connected to each other, the storage mode is set immediately below one MOS electrode.
Since the area immediately below the other MOS electrode is in the inversion mode, the structure of the other capacitor is different, and as a result, the burden on the dielectric strength is not equal between the two MOS electrodes, and the overall dielectric strength is reduced. . In the present invention, the MOS
Since the semiconductor region immediately below the electrode is a high-concentration region in which an inversion layer is unlikely to be generated, the above problem is solved. As a result, each MOS capacitor bears the breakdown voltage almost uniformly, so that the overall breakdown voltage is high. Can and
A semiconductor device having a MOS capacitor without complicating the process can be realized.

[0013]

(Embodiment 1) An embodiment of a semiconductor device according to the first invention is shown in FIG. This semiconductor device is a dielectric isolation BiCMOS integrated circuit device used for vehicles, where 1 is a P ^- silicon substrate (semiconductor substrate), A, B,
C is an island-shaped semiconductor region (semiconductor region in the present invention), 3 is a buried N ⁺ layer, 8 is a P ⁺ source region, 9 is a P ⁺ drain region, 51 and 52 are MOS electrodes, and 21 is a silicon oxide film ( 22 is a polycrystalline silicon film in which trenches for isolating island-shaped semiconductor regions are embedded, and 23 is LOCO
S oxide film (field insulating film), 24 is a gate insulating film,
25 is a side wall oxide film, 26 and 27 are MOS capacitance insulating films,
0, 41, and 42 are N ^- regions.

An island-shaped semiconductor region (referred to as a first semiconductor region)
A has a first MOS capacitor, and an island-shaped semiconductor region (second semiconductor region) B has a second MOS capacitor. Further, a PMOS transistor is formed in the island-shaped semiconductor region (referred to as a third semiconductor region) C. Illustration of an interlayer insulating film, a passivation film, and the like is omitted.

In this device, the MOS electrode 51, the insulating film 2
6, the N ⁻ semiconductor region 41 constitutes a first MOS capacitance,
The MOS electrode 52, the insulating film 27, and the N ⁻ semiconductor region constitute a second MOS capacitor. The N ⁻ semiconductor region 41 is connected to the MOS electrode 52 of the second MOS capacitor through the N ⁺ contact region 61 and the connection conductor 53,
Both MOS capacitors are connected in series.

Therefore, in this series-connected MOS capacitor, MOS electrode 51 and N ⁺ contact region 62 form both terminals. In the serially connected MOS capacitor of this embodiment, the MOS electrode 51 is set to the + side, and the N ⁺
2 is used as the negative side. In this way, MOS
This is because the surfaces of the semiconductor regions 41 and 42 immediately below the electrodes 51 and 52 can be used not in the inversion mode but in the accumulation mode. If the surfaces of the semiconductor regions 41 and 42 immediately below the MOS electrodes 51 and 52 are in the inversion mode, the P-type inversion layer is in a pseudo floating state or a depletion state, and is unusable due to indefinite capacitance and increased resistance. Will be appropriate.

However, if the above structure and operating conditions are satisfied, both MOS capacitors can be used in the accumulation mode. If the areas of both MOS electrodes 51 and 52 are made equal, the capacity of both MOS electrodes becomes equal. Both MOS capacitors can bear the applied voltage by half, and as a result, the breakdown voltage can be reduced by 2 without complicating the manufacturing process.
Can be doubled.

Of course, with the same connection method as in FIG.
If more than two MOS capacitors are connected in series, a higher withstand voltage can be obtained. In this embodiment, the withstand voltage 2
Although 6 and 27 were manufactured in the same process as the gate insulating film 24, they can be manufactured in separate steps. Hereinafter, the manufacturing process of the above device will be described in detail with reference to FIGS.

First, as shown in FIG. 1, a 1.0-1.6 × 10 ¹⁵ atoms / cm ³ N ⁻ type (100) single crystal silicon substrate 4 on which an N ⁺ diffusion layer 3 is formed is prepared. The P ^-
On the surface of the substrate 1, a thermally oxidized silicon oxide film 2 was formed to a thickness of 1.0 μm. The silicon substrate 1 and the silicon substrate 4 are heated in a mixed solution of H ₂ O ₂ -H ₂ SO ₄ to perform a hydrophilic treatment, and the substrates 4 and 1 are combined at room temperature.
Heat treatment was performed in an N ₂ atmosphere at 100 ° C. for 2 hours to join.

Subsequently, as shown in FIG. 2, the substrate 4 is mirror-polished to a predetermined thickness to produce an SOI substrate.
A mask oxide film (not shown) for trench etching was formed on the surface of the substrate. Next, as shown in FIG. 3, a predetermined oxide film mask pattern 95 was formed by a normal photolithography process, and a trench region T reaching the silicon oxide film 2 was formed by dry etching. The trenches form single crystal island-shaped semiconductor regions A, B, and C spatially separated from each other.

Subsequently, as shown in FIG. 4, a silicon oxide film (not shown) is formed to a thickness of 0.5 to 1 μm by thermal oxidation.
The upper and side surfaces of each of the island-shaped semiconductor regions A, B, and C are insulated and protected. Subsequently, polysilicon is deposited to bury the trench region. Next, the surface of the island-shaped semiconductor regions A, B, and C was polished until the silicon on the surface was exposed, the surface was smoothed, and an insulating isolation region 22 for separating the island-shaped semiconductor regions was formed.

Next, as shown in FIG. 5, a LOCOS process is performed. First, a pad silicon oxide film 81 is formed, a Si ₃ N ₄ film 82 is formed thereon, and the Si ₃ N ₄ film 82 is patterned. I do. Next, as shown in FIG.
Oxidation is performed at 1050 ° C. in a wet HCl atmosphere for about 5 hours to form a field insulating film 23 having a thickness of about 1 μm. After that, the Si ₃ N ₄ film 82 and the pad silicon oxide film 81 are removed.

Next, as shown in FIG.
Oxide films 24, 26, and 27 having a thickness of about 600 angstroms are formed on the surface of P.42 by thermal oxidation.
Non-doped polysilicon of 4 μm is deposited, and high concentration polysilicon is formed by phosphorus deposition. It is patterned to form MOS gate electrodes 50-52, which are then oxidized to form an oxide film (not shown) on the surface.

Next, as shown in FIG. 1, the regions other than the regions to be the P ⁺ regions 8 and 9 are covered with a resist, and boron ions are implanted at about 8.0 × 10 ¹⁴ dose / cm ² at 30 keV. Next, the area other than the area expected to be the N ⁺ areas 60 to 62 is covered with a resist, and phosphorus is added to about 7.0 × 10 ^15.
Ion implantation at 130 keV at dose / cm ² , then, after removing the resist, heat-treating to a depth of about 0.8 μm.
m ⁺ P ⁺ regions 8, 9 and N ⁺ regions 60-62 are formed. Next, the interlayer insulating film on the N ⁺ regions 61 and 62 and the MO
The interlayer insulating film on the surface of the S electrodes 51 and 52 is opened in a predetermined shape to form a contact. Next, aluminum is deposited on the entire surface and then patterned to form a connection conductor 53, a positive electrode terminal 57,
-Form electrode terminals 58 and complete major steps .

[0025]

[0026]

[0027]

[0028]

[0029]

[0030]

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a first embodiment.

FIG. 2 is a cross-sectional view showing a process of Example 1.

FIG. 3 is a cross-sectional view showing a process of the first embodiment.

FIG. 4 is a cross-sectional view showing a process in the first embodiment.

FIG. 5 is a cross-sectional view showing a process of the first embodiment.

FIG. 6 is a cross-sectional view showing a process of the first embodiment.

FIG. 7 is a cross-sectional view illustrating a process of the first embodiment.

FIG. 8 is a sectional view of a conventional device.

[Explanation of symbols]

1 is a silicon substrate (semiconductor substrate ) 3 is a buried N ⁺ layer (a region having a high impurity concentration in a semiconductor region) 21 is a silicon oxide film (insulating layer) 41 and 42 is an N ⁻ region (semiconductor region) 51 and 52 Is a MOS electrode 61, 62 is a contact electrode 53 is a connection conductor

Continuation of the front page (56) References JP-A-4-283958 (JP, A) JP-A-4-323860 (JP, A) JP-A-1-283861 (JP, A) JP-A-1-283863 (JP) JP-A-3-83319 (JP, A) JP-A-3-46267 (JP, A) JP-A-54-54588 (JP, A) JP-A-57-54360 (JP, A) 4-196583 (JP, A) JP-A-4-134844 (JP, A) JP-A-61-51841 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H01L 27/04 H01L 21/822

Claims (1)

(57) [Claims] 1. A semiconductor device having an insulating layer formed on a semiconductor substrate .
A semiconductor region formed by separating the semiconductor layer insulator, a plurality of MOS electrodes disposed respectively through an insulating film on the semiconductor region surface, its each said semi conductor region surface
MOS Con <br/> capacitor having a respectively formed contact electrodes, and, wherein the semiconductor regions than said MOS capacitor is formed
In a semiconductor device having a MOS capacitor having a MOS transistor, formed in said semiconductor region of the outer, the second of the contact electrode of the second of said semiconductor region surface formed independently of the first of said semiconductor region a connection conductor connected to the first of said MOS electrode on the first semiconductor region, a first of said con <br/> tact electrode and the second semiconductor region of the first semiconductor region surface 2 of the above M
And a series connection MOS capacitor formed between the OS electrodes, among the semiconductor regions, a region adjacent to the insulating layer,
From the region facing the MOS electrode with the insulating film interposed
A semiconductor device having a MOS capacitor characterized by having a high impurity concentration .