JP2971661B2 - Digital data transmission method between backplanes - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for transmitting digital data through a backplane.

[0002]

2. Description of the Related Art An exchange will be described as an example of a conventional apparatus for transmitting and receiving digital data between backplanes.

FIG. 6 is a block diagram showing a conventional example of a digital data transmission method between backplanes in an exchange.

The exchange operation between the interface units 601 to 616 for accommodating external devices such as telephones and data terminals and performing conversion or inverse conversion into digital signals is performed by a bus switch using a data bus 600 wired on a backplane. That is, digitized data is sequentially transmitted from the interface unit 601 to the data bus 600, and any of the interface units 601 to 616 is transmitted.
Receives data on the data bus 600 and transmits the data to an external device, thereby achieving data exchange.

Next, transmission and reception of digital data between backplanes in the apparatus shown in FIG. 6 will be described. FIG.
FIG. 3 is a configuration block diagram of a bus access unit of the interface unit.

First, after input data from an external device is converted into digital data, it is temporarily stored in a memory (not shown) until it is transmitted to a data bus. When the data is stored in the memory, a data transmission request signal S71 is sent to the transmission control unit 701 to make a transmission request. Next, the transmission control unit 701 returns a transmission permission signal S72 at the timing of transmitting its own data based on a signal S75 including a frame synchronization signal and a data string synchronization signal output from the clock generation unit. Upon receiving the transmission permission signal S72, the data stored in the memory is sequentially transmitted to the transmission-side data bus 705.
And in the flip-flop circuit 707 in the backplane data bus driver, the data is output to the data bus 600 of FIG. 6 wired on the backplane in synchronization with the bit timing S76 output from the clock generator.

Conversely, the reception of data from the data bus 600 of FIG. 6 is taken into the flip-flop circuit 708 in the data receiver at the falling edge of the bit timing S76, and is not shown via the reception-side data bus 706. It is delivered to the reception buffer, and reception is completed.

FIG. 8 is a time chart showing data timing on the back plane. Signal S in FIG.
FIG. 8 shows 75 frame synchronization signals and data string synchronization signals. The value of the address counter that counts the address is reset to “0” by the falling edge of the frame synchronization signal, and the address is sequentially counted at every rising edge of the data string synchronization signal. Thereby, the address number of the data bus can be known.

The transmission method of digital data on the backplane has been described above. Next, the delay relationship between data and clock will be described.

FIG. 9 is a diagram showing a propagation delay of data transmission in the configuration of FIG. The vertical axis in FIG. 9 is time,
τ is the time of one cycle of the clock. In the case where the interface units are arranged as shown in FIG. 6, when data is transmitted from the interface unit 601 to the other interface units 602 to 616, for example, as shown in FIG.
01 to the interface unit 616, the data D91 to D93 and the clock CK9
Since the propagation paths of 1 to CK92 are almost the same, the delay time of the clock and the data becomes the time DT regardless of the position of the interface unit on the receiving side, and can be said to be constant.

However, as shown in FIG. 9B, when data is transmitted from the interface unit 616 mounted farthest from the clock source to the interface unit 601 mounted closest to the clock source. , Data D95 to D97 and clock CK97
, The delay time between data and clock becomes a problem. In addition, since it is necessary to take in the data at the falling edge of the clock into the flip-flop circuit 708 in the data receiver in FIG. 7, the data is at least added to the time T90 at which the falling edge of the clock arrives and the setup of the flip-flop circuit 708. It must have reached the input of the flip-flop circuit before the time Tsu.

Actually, it is necessary to design a delay including the propagation delay on the back plane, the propagation delay of the bus driver / receiver and the flip-flop circuit, and the maximum frequency of the bit timing clock obtained from these values is limited. The maximum frequency fm of the bit timing clock is given by equation (1).

Fm = 1 / (2 (2 (D + Tp2) + Tp1 + Tsu)) (1) where D is the propagation delay of the backplane, Tp1 is the propagation delay of the driver-side flip-flop circuit, and Tp2 is the driver delay.
The propagation delay of the receiver, Tsu, is the setup time of the flip-flop circuit on the receiver side.

Here, as an appropriate value for the above constant, TT
Assuming a high-speed element among the L gates, a maximum frequency is obtained by substituting a value. That is, D = 2.4 ns, Tp1
= 10 ns, Tp2 = 6.5 ns, and Tsu = 3 ns, the maximum frequency fm is about 16 MHz. Therefore,
In the conventional configuration, the maximum clock frequency is 16 MHz when a high-speed device such as an ECL gate is not used.
It cannot be greater than z.

That is, in the conventional configuration, the maximum clock frequency used for transmitting and receiving digital data between the backplanes has a limit of about 16 MHz, and a higher-speed device is used for further increasing the speed. There was a problem that it was necessary.

As described above, according to the present invention, in the conventional digital data transmission method between backplanes, since the transmission delay at the time of data transmission between units is not constant, the highest clock frequency to be used is used. Is 16MH
There is a limit about z, and when trying to speed up further,
It was necessary to use a high-speed device.

Therefore, the present invention eliminates this problem,
It is an object of the present invention to provide a digital data transmission method between backplanes capable of high-speed digital data transmission without using a high-speed device.

[0017]

SUMMARY OF THE INVENTION The present invention relates to a digital data transmission system between backplanes for transmitting and receiving digital data between a plurality of units connected to a backplane having a first common clock supply line. A clock generation unit that has a second clock supply line different from the first common clock supply line, and wherein the unit generates a second clock for data transmission timing from the clock of the first clock supply line Output means for outputting a clock generated by the clock generation means to the second clock supply line; and delaying data transmission until the second clock generated by the clock generation means is stabilized. And delay means.

Further, in the digital data transmission method between the backplanes, each unit outputs the clock supplied from the first common clock supply line to the second clock supply line as it is.

[0019]

According to the present invention, in a digital data transmission system between backplanes for transmitting and receiving digital data between a plurality of units connected to a backplane having a first common clock supply line, a first common clock supply system is provided. A second clock supply line different from the first clock supply line, wherein the unit generates a second clock for data transmission timing from a clock of the first clock supply line; Output means for outputting the clock generated by the second clock supply line to the second clock supply line, and delay means for delaying data transmission until the second clock generated by the clock generation means is stabilized. Data and the bit synchronization clock are the same for any unit mounted on the backplane. The transmitted with a same delay,
Transmission delays between units are eliminated.

In the digital data transmission method between the backplanes, each unit outputs the clock supplied from the first common clock supply line to the second clock supply line as it is, as described above. ,
For any unit mounted on the backplane,
The data and the bit synchronization clock are transmitted on the same path with the same delay, and the influence of the transmission delay between the units is eliminated.

[0021]

FIG. 1 is a schematic block diagram showing an embodiment of the present invention. FIG. 1 assumes an exchange as a device for transmitting and receiving digital data between backplanes. The apparatus includes a common clock generation source 100 and an interface unit 101 for transmitting and receiving digital data.
And the backplane 120 on which the clock generation source 100 and the interface units 101 to 116 are mounted. The backplane 120 includes a source clock line 121 for transmitting a source clock, a frame synchronization signal, and a data string synchronization signal, a data bus 123 for performing data transmission, and a reverse clock for transmitting a clock used as a bit synchronization clock during data transmission. There are three kinds of wirings 130 of the line 122.

Next, a method of transmitting digital data between backplanes according to the present invention will be described with reference to the details of the bus access unit of the interface unit. FIG.
FIG. 4 is a detailed block diagram of a bus access unit of the interface unit according to one embodiment of the present invention.
The data flow until the digitized data reaches the backplane data bus drivers 211 to 214 is the same as in the conventional example. First, input data from an external device is temporarily stored in a memory (not shown) after being converted into digital data and then transmitted to a data bus. When data is stored in the memory, the transmission control unit 201
, A data transmission request signal S21 is sent out, and a data transmission request is made. Next, the transmission control unit 201 returns the transmission permission signal S22 at the timing of transmitting its own data based on the two signals S25 of the frame synchronization signal and the data string synchronization signal output from the clock generation unit. Upon receiving the transmission permission signal S22, the data stored in the memory is sequentially output to the transmission data bus 220.

The data output to the transmission-side data bus 220 is transmitted to the flip-flop circuit 211 in the backplane data bus driver on the backplane in synchronization with the bit timing S26 generated by using the phase synchronization circuit (PLL circuit) 230. Data bus 25 wired to
3 is output. Here, the phase synchronization circuit 230 is used to generate a bit timing clock synchronized with the common timing clock based on the common timing clock output to the source clock line 251 by the common clock generation source. At the same time, the clock used as the bit synchronization clock during data transmission is output to the reverse clock line 252.

The reception from the data bus 253 is taken into the flip-flop circuit 240 in the data receiver at the rising edge of the bit timing output on the reverse clock line 252, and is shown via the reception side data bus 253. Not passed to the receive buffer and the reception is completed.

The method of transmitting digital data on the backplane according to the present invention has been described above. Next, the delay relationship between the data and the bit synchronization clock will be considered. FIG. 3 is a diagram showing a propagation delay of data transmission in the configuration of FIG. In FIG. 3, the vertical axis represents time, and τ
Is the time of one cycle of the clock. The horizontal axis represents the positional relationship of data transmission, and the data and clock are
The transmission is transmitted from the transmission unit 301 to the reception unit 302 via the data bus transmission path 303.

According to the present invention, data D31 to D33 and bit synchronization clocks RC31 to RC3 are supplied to any interface unit mounted on the backplane.
3 is transmitted along the same route. Therefore, when considering the delay relationship between data and clock, it is not necessary to consider the case where the data and clock propagation paths are different as in the conventional case, but only the case where the data and clock propagation paths are the same. In other words, the propagation delay D
And the propagation delay Tp2 of the driver / receiver act in the same direction as each other, so that the elements related to the delay are the propagation delay Tp1 of the flip-flop circuit in the backplane data bus driver used for data transmission and the setup of the flip-flop circuit in the data receiver. Only time Tsu. Therefore, the maximum frequency fm of the bit timing obtained from these values is given by equation (2).

Fm = 1 / (2 (Tp2 + Tsu)) (2) Here, assuming that the same device as that of the related art is used, substituting the values of Tp1 = 10 ns and Tsu = 3 ns into the equation (2) fm is about 38 MHz.

FIG. 4 is a diagram showing the timing of digital data transmission between backplanes according to the present invention. According to the present invention, a source clock used as a bit synchronization clock at the time of data transmission is output to a reverse clock line as a reverse clock. Since the reverse clock line is commonly driven by all the interface units similarly to the data bus, a three-state driver or an open collector driver is used for the driver hardware. Accessing one signal line by a plurality of interface units by switching may cause disturbance of the clock on the reverse clock line during the switching. Therefore, as a countermeasure, an appropriate guard time Tg is provided at intervals at which each interface unit drives the reverse clock line, and clock output and data transmission are performed so that data is output after the output clock is stabilized. By providing a clock stabilization time Ts between them, digital data can be transmitted and received between stable backplanes.

FIG. 5 is a block diagram showing the detailed configuration of the phase synchronization circuit 230 shown in FIG. The source clock signal CK50 is input as an input signal of the phase synchronization circuit, and the source clock signal CK50 is input to the phase comparison circuit 502 via the 1 / N circuit 501. The difference signal voltage output from the phase comparison circuit 502 via the low-pass filter 503 is input to the voltage control transmission circuit 505, and the frequency is controlled. A reverse clock signal / standby signal generation circuit 506 generates a reverse clock signal RC50 and a standby signal SB50 from the frequency output through the 1 / 4N circuit 504.

In the above embodiment, the PLL is used to generate a bit timing clock synchronized with the common timing clock based on the common timing clock output from the clock generation source to the source clock line, but it is used for data transmission. As the clock, a clock obtained by simply turning back the source clock may be used.

[0031]

As described above, the present invention relates to a digital data transmission method between backplanes for transmitting and receiving digital data between a plurality of units connected to a backplane having a first common clock supply line. , First
Clock generating means for generating a second clock for data transmission timing from a clock of the first clock supply line, the second clock supply line being different from the common clock supply line of Output means for outputting the clock generated by the clock generation means to the second clock supply line; delay means for delaying data transmission until the second clock generated by the clock generation means is stabilized Therefore, the data and the bit synchronization clock are transmitted to the arbitrary units mounted on the backplane on the same path with the same delay, and the transmission delay between the units is eliminated.

Thus, high-speed data transmission between arbitrary units can be realized.

Also, in the digital data transmission method between the backplanes, each unit outputs the clock supplied from the first common clock supply line to the second clock supply line as it is, as described above. ,
For any unit mounted on the backplane,
The data and the bit synchronization clock are transmitted on the same path with the same delay, and the influence of the transmission delay between the units is eliminated.

In this case as well, high-speed data transmission can be realized between arbitrary units as described above.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram showing an embodiment according to the present invention.

FIG. 2 is a detailed configuration block diagram of a bus access unit of the interface unit in the embodiment.

FIG. 3 is a diagram showing a delay relationship between data and a clock in the embodiment.

FIG. 4 is a timing chart of digital data transmission between backplanes in the embodiment.

FIG. 5 is a detailed configuration block diagram of a clock recovery unit using a phase synchronization circuit in the embodiment.

FIG. 6 is a schematic block diagram showing a conventional digital data transmission method between backplanes.

FIG. 7 is a detailed block diagram of a bus access unit of the interface unit in the conventional example.

FIG. 8 is a timing chart of digital data transmission between backplanes in the conventional example.

FIG. 9 is a diagram showing a delay relationship between data and a clock in the conventional example.

[Explanation of symbols]

REFERENCE SIGNS LIST 100 clock generation source 101 to 116 interface unit 120 backplane 121 source clock line 122 reverse clock line 123 data bus 201 transmission control unit 211 to 214 backplane data bus driver 220 transmission data bus 230 phase synchronization circuit (PLL circuit) 240 flip-flop Circuit 250 Receive data bus 251 Source clock line 252 Reverse clock line 253 Data bus 301 Transmission unit 302 Receiving unit 303 Data bus transmission line 501 1 / N circuit 502 Phase comparison circuit 503 Low-pass filter 504 1 / 4N circuit 505 Voltage controlled oscillation Circuit (VCO) 506 Reverse clock signal / standby signal generation circuit 600 Data bus 601 to 616 Interface unit 7 01 Transmission control unit 705 Transmission data bus 706 Reception data bus 707, 708 Flip-flop circuit 901 Unit shortest to clock generation source 902 Data bus transmission line 903 Unit far from clock generation source CK50 Source clock signal CK91, CK92, CK95-CK98 Clock D31 to D33, D91 to D93, D95 to D97 Data RC31 to RC33 Reverse clock RC50 Reverse clock signal S21, S71 Transmission request signal S22, S72 Transmission permission signal S25, S75 Two signals of frame synchronization signal and data string synchronization signal S26 Phase synchronization Circuit output signal S76 Clock SB50 Standby signal T90 Time when falling edge of clock arrives

Claims (2)

(57) [Claims] 1. A digital data transmission system between backplanes for transmitting and receiving digital data between a plurality of units connected to a backplane having a first common clock supply line, comprising: a first common clock supply line; Has a different second clock supply line, wherein the unit generates a second clock for data transmission timing from a clock of the first clock supply line; Output means for outputting the generated clock to the second clock supply line, and delay means for delaying data transmission until the second clock generated by the clock generation means is stabilized. A digital data transmission method between backplanes. 2. The digital data transmission system between backplanes according to claim 1, wherein each unit outputs the clock supplied from the first common clock supply line to the second clock supply line as it is. .