JP2969996B2 - IC tester - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC (semiconductor integrated circuit) such as a memory IC, and more particularly to an IC tester for measuring digital functions.

[0002]

2. Description of the Related Art Conventional general IC testers use input data to be supplied to terminal pins of an IC to be measured and data of expected values of signals output from the terminal pins when a signal is input to the IC to be measured by the input data. Has a pattern memory stored therein, and inputs an input signal read from this memory to the IC under test, whereby an output actually obtained from the IC under test is similarly read out from the pattern memory described above. The quality of this IC is determined by comparing it with the expected value.

Therefore, in this case, the capability of the tester is determined by the prepared memory length. That is, it is not possible to perform an IC test that requires reading and writing a pattern exceeding the pattern memory of the IC tester.

For example, when the IC to be measured is a large-capacity memory, for example, an SRAM having an extremely large number of flip-flops, an IC tester having an enormous memory length is required as a tester for determining the quality of the IC.

More specifically, for example, a 1 Mbit SRAM
IC testers require a tester having an enormous pattern memory capable of storing data of the order of 100 Mbits, which is two orders of magnitude higher. IC testers satisfying this requirement are of a very large size and an extremely high price. Will lead to higher prices.

Since this IC test is performed for all products, the occupation time of the tester in one IC test has a great effect on productivity.

[0007]

The problem to be solved by the present invention is to increase the memory length of an IC tester when the IC to be measured is a large-capacity memory IC, etc.
Higher prices.

[0008]

According to the present invention, one or more write pointers 1, a read pointer 2, and a pointer position corresponding to the highest address are set as shown in FIG. Pattern memory 3 having a loop-like address configuration that becomes the lowest address when incremented
And

From the starting point of the write pointer 1, data to be given to the IC to be measured and expected value data are written into the pattern memory 3 in the sequence according to the program, and data is read from the read pointer 2 to the write address for the write address. The IC is given the above data to be given to it. On the other hand, by comparing the output signal from the IC to be measured with the data of the expected value,
The quality of the characteristics of the IC to be measured is determined.

[0010]

The IC tester according to the present invention provides data to be supplied to the measured IC, for example, a control signal for its operation,
Data such as an input signal for the function test and data of an expected value of an output signal when the input signal is input to the IC to be measured are temporarily stored in the pattern memory 3 and are stored. Read data and measure I
The data is input to C, and the read expected value is compared with the output of the IC under test by the data input to determine the quality of the IC.

When the address of the pattern memory is incremented by the pointer position corresponding to the highest address, the address becomes the lowest address. That is, since the pattern memory is formed in a loop, the address of the data stored as described above is obtained. The read address stores the next data again according to the designation of the write pointer. Subsequently, the same read is performed by the read pointer, and the input to the IC to be measured is compared with the expected value of the output. Can be performed indefinitely regardless of the length of the pattern memory.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An example of an IC tester according to the present invention will be described with reference to FIG. The pattern memory 3 stores addresses A ₁ ,
A ₂ , A ₃ ‥‥ A _{1 + n−2} , A _{1 + n−1} , A _{1 + n} , as shown schematically in an array, the highest address,
For example, when the pointer position corresponding to A _{1 + n} is incremented, the address becomes a loop address configuration that becomes the lowest address A ₁ .

In FIG. 1, reference numeral 4 denotes a pattern generation unit, which is a pattern obtained from the pattern generation unit, that is, an SRA of an IC to be measured, for example, a memory IC according to a sequence according to a predetermined program.
A pattern to be stored in the pattern memory 3 such as data input to M and expected output data thereof is supplied to one or more write pointers 1.

The data stored in this manner is read by the read pointer 2 and supplied to, for example, an SRAM of the IC 5 to be measured.
To enter.

On the other hand, the output generated by the data input to the SRAM of the IC under test 5 is input to the comparator 6, which compares the output with the expected value from the read pointer 2.

The result of this comparison is stored in the system controller 7
Is sent to the server to make a pass / fail decision.

The pattern generating section 4 has a CPU (Central Processing Unit) 7. The pattern generating program from the program generator 8 causes the CPU 7 to store the address of the pattern memory, the data given to the IC 5 to be measured, and the expected value data. Output.

Then, this output is input to the address decoder 9 to set the write pointer 1 and store each data at the address of the pointer 1.

Reference numeral 10 denotes a clock generator, which introduces a clock signal as a clock signal to the CPU 7 and inputs the clock signal to a counter 11, which controls the system controller 7 and counts the read pointer. As described above, data is read from a predetermined address of the pattern memory 3 and the read data is input to the measured IC 5 or the comparator 6.

The system controller 7 monitors the pattern generation unit 4 and the read pointer together with the above-described pass / fail judgment, and the read pointer sets the write pointer to
Further, time control, for example, "waiting" control is performed so that the write pointer does not pass the read pointer.

On the other hand, a plurality of write pointers 1 are provided according to the access speed of the pattern memory and the pattern generation speed. In this case, the pattern generation unit 4 includes, for example, as shown in FIG.
1m, the program generators 81, 82, 83 # 8m, CP as in the pattern generator 4 of FIG.
U71, 72, 73 ‥‥ 7m, decoders 91, 92, 9
3 ‥‥ 9 m is provided.

According to the IC tester of the present invention as described above, the pattern memory 3 temporarily stores data as a so-called buffer memory, and reads a large number of data by, for example, a large number of read pointers to read the data to be measured.
C5, and also obtains expected value data to be obtained from the IC under test 5 at this time, and compares it with the actual output from the IC under test to judge pass / fail. 3 has a loop-like address configuration, so that it can be predicted or predicted when the pattern to be stored is determined in advance, that is, the program generator 8 (81, 8).
2,83 ‥‥ 8m)
In the case of the C test pattern, a test equivalent to an infinite memory length can be performed by controlling the write pointer and the read pointer so as not to overtake each other.

It is needless to say that the present invention is not limited to the examples shown in FIGS.

[0024]

As described above, according to the present invention, the pattern memory is formed into a loop, and the pass / fail test of the IC under test can be performed by continuously writing and reading data using the buffer memory. Because it was
In particular, as in a memory IC such as an SRAM, when a signal to be handled is a digital signal and a data pattern to be input to its terminal pin and an expected value pattern are determined or can be predicted, the same address can be used repeatedly. Infinite memory length can be achieved.

Therefore, as in the conventional IC tester, for example, as described above, the measured IC
In the case of a monotonous test pattern such as in the AM, the number of memories in the tester can be greatly reduced.
In particular, it can be manufactured extremely small and inexpensively by using it as a tester for judging the quality of a large capacity memory IC.

Further, even in the case where the generated pattern or the test pattern has no monotonicity, in some cases,
In the pattern generation unit 4, the number of memories in the tester can be significantly reduced by expanding the logically compressed pattern by the processor.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an example of an IC tester according to the present invention.

FIG. 2 is a configuration diagram of an example of a pattern generator of an IC tester according to the present invention.

[Explanation of symbols]

 1 Write pointer 2 Read pointer 3 Pattern memory 4 Pattern generator

Claims (1)

(57) [Claims] 1. A pattern memory having one or more write pointers, a read pointer, and a loop-shaped address configuration that becomes a lowest address when a pointer position corresponding to the highest address is incremented. From the start point of the pointer, data to be given to the IC under test or data of an expected value is written in the pattern memory in the sequence according to the program, and the data is read out from the write address by the predetermined read pointer signal, and the read data is written to the IC under test. An IC tester for comparing the output signal from the measured IC with the expected value data to determine whether the characteristics of the measured IC are good or not.