JP2969184B2 - Thin film transistor memory - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a thin film transistor memory.

[Conventional technology]

Recently, E ² PROM that can be electrically written, erased, and read
For example, a thin film transistor memory in which a memory transistor and a selection transistor are formed of thin film transistors has been considered.

Conventionally, as this thin film transistor memory, a thin film transistor for memory (hereinafter, referred to as a memory transistor) and a thin film transistor for selection (hereinafter, referred to as a selection transistor) are formed adjacently on an insulating substrate made of glass or the like. It is known that a transistor and a selection transistor are connected in series via a connection line connecting one source electrode and the other drain electrode to form a transistor memory. Note that each of the memory transistor and the selection transistor includes a gate electrode, a gate insulating film, an i-type semiconductor layer, a source,
The gate insulating film of the memory transistor is formed of an insulating film having a charge storing function, and the gate insulating film of the select transistor is formed of an insulating film having no charge storing function.

FIG. 9 is an equivalent circuit diagram of the conventional thin film transistor memory. Here, an equivalent circuit of a thin film transistor memory having two selection transistors for one memory transistor is shown.

The In FIG. 9, T ₁ is the memory transistor, T ₂ are two selection transistors arranged on opposite sides of the memory transistors T _1, the source electrode S ₁ of the memory transistors T ₁ is one of the drain electrode of the selection transistor T ₂ is connected to the D _2, the drain electrode D ₁ of the memory transistors T ₁ is connected to the source electrode S ₂ of the other selection transistor T _2. Then, the source electrode S ₂ of the one selection transistor T ₂ are set to the source electrode S ₀ of the transistor memory, the drain electrode D ₂ of the other selection transistor T ₂ are are a drain electrode D ₀ of the transistor memory; The source electrode S ₀ is connected to a source line (not shown), and the drain electrode D ₀
Are connected to a drain line (not shown). The gate electrode G ₁ of the memory transistor T ₁ is connected to a first gate line (not shown), the gate electrode G ₂ of the two select transistors T ₂ is commonly connected to the second gate line (not shown). Incidentally, the first and second gate lines are present parallel line number, source lines and drain lines are large number wiring are perpendicular to the gate line, constituted by a memory transistors T ₁ and the selection transistor T ₂ The thin film transistor memory to be used is composed of the first and second
It is formed at the intersection of the gate line and the source and drain lines.

Writing, erasing, and reading of this thin film transistor memory are performed as follows.

In FIG. 9, (a) shows a voltage applied state at the time of writing, (b) shows an erased state, and (c) shows a voltage applied state at the time of reading.

First, the writing will be described, upon writing, as shown in FIG. 9 (a), the source electrode S ₀ and the drain electrode
While grounded D ₀ (GND), by applying a ON voltage V _ON to the gate electrode G ₂ of the select transistor T _2, applying a write voltage + V _P to the gate electrode G ₁ of the memory transistor T _1. The application of such a voltage, the selection transistor T ₂ is turned on, the gate electrode G ₁ and the source of the memory transistor T _1, takes the write voltage + V _P between the drain electrode S _1, D _1,
Memory transistor T ₁ becomes the write state (OFF state).

At the time of erasing, as shown in FIG. 9B, the source electrode S ₀ and the drain electrode D ₀ are grounded (GND), and the ON voltage V _ON is applied to the gate electrode G ₂ of the selection transistor T _2. , the gate electrode G ₁ of the memory transistor T _1, and the write voltage + V _P applies an erase voltage -V _P opposite potential. The application of such a voltage, the selection transistor T ₂ is turned on, the potential difference between the write pole + V _P and reverse potential between the memory transistor gate electrode G ₁ and the source of T _1, the drain electrode S _1, D ₁ (- V _P) is generated, the memory transistors T ₁ is erased state (ON state).

On the other hand, during reading, as shown in FIG. 9 (c), with grounding the gate electrode G ₁ and the source electrode S ₀ of the memory transistor T ₁ (GND), ON to the gate electrode G ₂ of the select transistor T ₂ A voltage V _ON is applied, and a read voltage V _D is applied to the drain electrode D ₀ . The application of such a voltage, if the memory transistor T ₁ is erased state (ON state) current flows from the drain electrode D ₀ to the source electrode S _0, if the memory transistor T ₁ is in the write state (OFF state) since the current does not flow, read data corresponding to the presence or absence of a current flowing from the source electrode S ₀ in the source line is output.

Here, it has been described a thin film transistor memory comprising two selection transistors T ₂ for one memory transistor T _1, a thin film transistor memory, which has a single select transistor for one memory transistor There is.

[Problems to be solved by the invention]

However, in the conventional thin film transistor memory, a memory thin film transistor and a selection thin film transistor are formed adjacent to each other on a substrate, and the memory transistor and the selection transistor are connected in series by a connection wiring. There is a problem that the element area (planar area) of one transistor memory is large, so that it is difficult to increase the degree of integration of a memory matrix configured by arranging transistor memories vertically and horizontally. Moreover, in the conventional thin film transistor memory, the gate insulating film of the memory thin film transistor is an insulating film having a charge storage function, and the gate insulating film of the selecting thin film transistor is an insulating film having no charge storing function. And the thin film transistor for selection must be manufactured in separate steps, and therefore, there is also a problem that a large number of steps are required for manufacturing the thin film transistor memory.

The present invention has been made in view of the above circumstances, and has as its object to increase the degree of integration by reducing the element area of a transistor memory including a memory thin film transistor and a selection thin film transistor. It is another object of the present invention to provide a thin film transistor memory which can be manufactured easily with a small number of steps.

[Means for solving the problem]

The thin film transistor memory of the present invention is formed over a semiconductor layer, a memory gate insulating film formed on one surface side of the semiconductor layer, and a portion corresponding to the memory gate insulating film on one surface side of the semiconductor layer. A memory gate electrode,
A source and drain electrode formed on the other surface of the semiconductor layer, and a portion formed over the other surface of the semiconductor layer and the source and drain electrodes and corresponding to the memory gate electrode region is formed from another portion. The semiconductor device includes a thickened gate insulating film, and a select transistor gate electrode formed on the gate insulating film so as to include a region corresponding to almost the entire surface of the semiconductor layer region.

As described above, a memory gate insulating film and a memory gate electrode are formed on one surface of a semiconductor layer, and a source, a drain electrode, a gate insulating film, and a gate electrode for a selection transistor are formed on the other surface of the semiconductor layer. In addition, the memory gate electrode and the selection transistor gate electrode are stacked, and the area can be reduced as compared with the case where they are formed side by side on the same plane.

〔Example〕

 Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1 to 5 show a first embodiment of the present invention. FIGS. 1 and 2 are a sectional view and a plan view of a thin film transistor memory.

The structure of this thin film transistor memory will be described. In the figure, reference numeral 11 denotes an insulating substrate made of glass or the like.
Lower gate electrode G ₁₀ is formed on the top. The lower gate electrode G ₁₀ is locally protruded on the lower gate line GL ₁₀ formed on the substrate 11, the lower gate electrode G ₁₀ is the same width as the lower gate line GL _10, 300
It is formed to a thickness of 0 °. Further, on the substrate 11, the lower gate line GL ₁₀ and the lower gate electrode G
_A flattening insulating film 12 covering ₁₀ is formed. This flattening insulating film 12 is made of an insulating film having no charge storage function.
The planarizing insulating film 12 covers thick lower gate line GL _10, and is formed to a thickness covering thin lower gate electrode G _10. Note that the lower gate line GL ₁₀
The film thickness in the upper part is 4000 Å, and the film thickness in the part on the lower gate electrode G ₁₀ is 1000 Å. On the planarizing insulating film 12, a lower gate insulating film 13 is formed over substantially the entire surface of the substrate 11. The lower gate insulating film 13 has a charge storage function over the entire upper layer portion. The lower gate insulating film 13 is formed on a lower insulating film 13a made of SiN (silicon nitride) having no charge storage function. , A two-layer film in which a memory insulating film 13b made of SiN having a charge storage function by increasing the composition ratio of Si (silicon) is stacked. The thickness of the lower insulating film 13a is 900 mm, and the thickness of the memory insulating film 13b is 100 mm. This lower gate insulating film
An i-type semiconductor layer 14 made of amorphous silicon or polysilicon is formed on the upper surface 13 (on the memory insulating film 13b).
Are formed in a pattern corresponding to the element shape of the transistor memory, and n
A source electrode S and a drain electrode D are formed via an ohmic contact layer 15 made of a type semiconductor (amorphous silicon or polysilicon doped with an n-type impurity). The respective source electrodes S and the drain electrode D is connected to the source line SL and the drain line DL and wiring are perpendicular to the lower gate line GL ₁₀ on the lower gate insulating film 13. And the semiconductor layer
An upper gate insulating film 16 made of silicon nitride having no charge storage function is formed over substantially the entire surface of the substrate 11 on the source electrode 14 and the source and drain electrodes S and D. On the upper gate insulating film 16, an upper gate line GL ₂₀ is wired in parallel with the lower gate line GL ₁₀ , and a portion of the upper gate line GL ₂₀ on the semiconductor layer 14 is an upper gate electrode G _{It is 20} .

Then, with the lower gate electrode G _10, a planarization insulating film 12
And a lower gate insulating film 13 having a charge accumulation function, the semiconductor layer 14 and the source, the drain electrode S, is as D, inverse stagger type memory thin film transistor (hereinafter, referred to as the memory transistor) constituting the T _10. The lower gate electrode G ₁₀ is the gate electrode of the memory transistor T ₁₀
Is the center of the semiconductor layer 14 in the channel length direction (source,
The semiconductor layer 1 is opposed to the central portion between the drain electrodes S and D).
4 is formed to have a width of about 1/3 of the width in the channel length direction, and thus the lower gate insulating film 13 is
Only the central portion facing the G ₁₀ is a memory area.

Meanwhile, the upper gate electrode G ₂₀ is an electrode opposed to the entire semiconductor layer 14, the upper gate electrode G ₂₀
Upper gate insulating film 16 between the semiconductor layer 14 and has a top portion of the memory region of the lower gate insulating film 13 (the opposite portion of the lower gate electrode G _10), a source, a drain electrode S, substantially at the center of the D An insulating film is formed in which the thickness of the portion outside the opposing position is increased and the thickness of the portion between the memory region and the source electrode S and between the memory region and the drain electrode D is reduced. . That is, this upper gate insulating film
Reference numeral 16 denotes a lower insulating film 16a covering the entire semiconductor layer 13, an etching stopper insulating film 16b formed on the entire surface of the lower insulating film 16a, and an etching stopper insulating film 1b.
6b, the memory region and the source and drain electrodes S,
D is an inter-laminate consisting of the upper insulating film 16c formed corresponding to the outer portion from the center.
The lower insulating film 16a and the upper insulating film 16c are formed of, for example, SiN having no charge storage function, and the etching stopper insulating film 1 is formed.
6b is formed of, for example, Al ₂ O ₃ (alumina). The thickness of the lower insulating film 16a is 1900 mm, the thickness of the etching stopper insulating film 16b is 100 mm, and the thickness of the upper insulating film 16c is 3 mm.
The thickness of the thick film portion of the upper gate insulating film 16 (a three-layer film portion including the lower insulating film 16a, the etching stopper insulating film 16b, and the upper insulating film 16c) is sufficient thickness to prevent the memory area corresponding portion from the upper gate electrode G ₂₀ of the gate voltage is applied (5000
Is a Å), the thickness of the thin film portion of the upper gate electrode G ₂₀ (two-layer film portion composed of the lower insulating film 16a and the etching stopper insulating film 16b) is sufficient to semiconductor layer 14 from the upper gate electrode G ₂₀ The film thickness (2000 °) to which a gate voltage can be applied is set. The thickness of the upper gate insulating film 16 is
The source and drain lines SL and DL are formed over the entire length of the insulating film in the length direction.

Then, over the memory transistor T _10, the semiconductor layer 14 and the source, drain electrodes S, 2 one selected thin film transistor to be shared with the memory transistor T ₁₀ a D (hereinafter, referred to as the selection transistor) is T _20, T ₂₀ Is formed. The two select transistors T ₂₀ and T ₂₀ are composed of the semiconductor layer 14 and the source and drain electrodes S and D, an upper gate insulating film 16 having no charge storage function, and an upper gate electrode
G ₂₀ is a coplanar thin film transistor. One select transistor T ₂₀ includes a semiconductor layer 14, source and drain electrodes S and D, one thin film portion of an upper gate insulating film 16, and an upper gate electrode G _The other select transistor T ₂₀ includes the semiconductor layer 14 and the source and drain electrodes S and D, the other thin film portion of the upper gate insulating film 16, and the upper gate electrode G _20. I have.

The two select transistors T ₂₀ and T ₂₀ are commonly connected on the gate side by using their gate electrodes (upper gate electrodes) G ₂₀ as electrodes facing the entire semiconductor layer 14. T ₂₀ and T ₂₀ are connected in series with the memory transistor T ₁₀ by sharing the source and drain electrodes S and D with the memory transistor T ₁₀ .

Further, the selection transistor of the upper gate insulating film 16
In each of the two thin film portions constituting T ₂₀ and T ₂₀ , the width in the channel length direction of the film thickness portion corresponding to the memory region of the lower gate insulating film 13 is smaller than the width of the lower gate electrode G _{10 in} the channel length direction. The lower gate electrode G
₁₀ wrapped on both sides. Is What this way, both selection and memory transistors T ₁₀ transistors T _20, T
And to secure the electrical connection _20, if a thin portion constituting the selection transistor T _20, T ₂₀ of the upper gate insulating film 16 by the lap beneath the gate electrode G _10, the memory of the semiconductor layer 14 Transistor T ₁₀ region and select transistor T
The gates of the select transistors T ₂₀ and T ₂₀ are also provided from the gate electrode (lower gate electrode) G ₁₀ of the memory transistor T ₁₀ at the boundary with the ₂₀ region (both sides of the portion corresponding to the memory region of the lower gate insulating film 13). since it is possible to apply the gate voltage from the electrodes (the upper gate electrode) G _20, when brought into oN both the memory transistors T ₁₀ and the selection transistor T _20, T _20, the drain electrode through the semiconductor layer 14 A current flows from D to the source electrode S. In this embodiment, the width of the thickness portion of the memory area of the upper gate insulating film 16, although approximately half the width of the lower gate electrode G _10, the width of the film thickness portion, the lower gate if the width of the electrode G ₁₀ or less may be any width, short, thin portion of the upper gate insulating film 16 has only to be opposed to at least a side edge of the lower gate electrode G _10.

FIG. 3 shows a method of manufacturing the thin film transistor memory. The thin film transistor memory is manufactured by the following steps.

First, as shown in FIG. 3A, a metal film 30 serving as a gate line GL ₁₀ is deposited on the substrate 11 to a thickness of 500.degree.
Depositing a metal film 31 serving as a lower gate electrode G ₁₀ thereon to a thickness of 3000 Å. Incidentally, the upper layer of the metal film 31 serving as a lower gate electrode G ₁₀ is formed by Ta (tantalum) or the like, underlying metal film 30 serving as the gate line GL ₁₀ is different metal of said layer of metal film 31 and the etching rate, For example, it is formed of Cr (chromium) or the like.

Next, as shown in FIG. 3 (b), the upper metal film
Forming a lower gate electrode G ₁₀ is patterned by 31 photolithography method, followed by forming a gate line GL ₁₀ by patterning the lower metal film 30 by photolithography.

Next, as shown in FIG. 3 (c), a silanol-based inorganic insulator called SOG (spin-on-glass) is applied on the entire surface of the substrate 11 by a spin coat method, and this is applied at about 300 ° C. Heating is performed for about 1 hour to form a planarization insulating film 12 having a thickness of 4000 の on the lower gate line GL ₁₀ , a thickness of 1000 の on the lower gate electrode G ₁₀ , and a flat upper surface.

Next, as shown in FIG.
On top of the lower gate insulating film 13, a lower insulating film (SiN film without a charge storage function) 13a and a memory insulating film with a charge storage function (SiN film with a higher Si composition ratio) 13b, 900Å,
The two-layered lower gate insulating film 13 composed of the lower insulating film 13a and the memory insulating film 13b is formed by successively depositing the film successively to a thickness of 100 °, and i-type amorphous silicon or i-type A semiconductor layer 14 made of polysilicon and an ohmic contact layer 15 made of an n-type semiconductor (n-type amorphous silicon or n-type polysilicon) are
And a metal film 40 for source and drain electrodes made of Cr or the like is further deposited thereon.
Deposit to a thickness of 0 mm.

Next, the source / drain electrode metal film 40 is patterned by a photolithography method, as shown in FIG.
As shown in FIG. 2, source and drain electrodes S and D and source and drain lines SL and DL composed of source and drain electrode metal films 40 are formed, and then the ohmic contact layer 15 is formed.
Are patterned into the shapes of source and drain electrodes S and D and source and drain lines SL and DL.

Next, as shown in FIG. 3 (f), by patterning the element shape of the transistor memory semiconductor layer 14 by photolithography to form the memory transistor T _10. The semiconductor layer 14 remains over the entire length below the source line SL and the drain line DL.

Next, as shown in FIG. 3 (g), a lower insulating film 16a, an etching stopper insulating film 16b, and an upper insulating film 16c are formed on the entire surface of the substrate 11 at 1900 °, 1
Deposit to a thickness of 00Å, 3000Å.

Next, as shown in FIG. 3 (h), the upper insulating film 16 is formed.
Of c, removing etched by partial photolithography between and between the memory region and the drain electrode D and the source electrode S (the opposing portion of the lower gate electrode G ₁₀₎ memory areas of the lower gate insulating film 13 An upper portion of the memory region and an outer portion from a position facing the center of the source and drain electrodes S and D are formed by a lower insulating film 16a, an etching stopper insulating film 16b, and an upper insulating film 16c. A two-layer film consisting of a lower insulating film 16a and an etching stopper insulating film 16b is provided between the memory region and the source / drain electrodes S and D. The upper gate insulating film 16 is formed as a thin film portion (thickness: 2000 mm) of the structure. In this case, even if the removed portion of the upper insulating film 16c is etched, the progress of the etching is stopped by the etching stopper insulating film 16b, so that the lower insulating film 16a is damaged during the etching for patterning the upper insulating film 16c. Therefore, the upper gate insulating film 16 can be formed with a high yield.

Next, as shown in FIG. 3 (i), a metal film such as Al (aluminum) is deposited to a thickness of 4000 ° on the upper gate insulating film 16 and the metal film is patterned by photolithography. To form an upper gate electrode G ₂₀ and an upper gate line GL ₂₀ to form two select transistors T
Configure the _20, T _20, to complete the thin film transistor memory.

In this manufacturing method, are formed by the steps shown a planarization insulating film 12 and the lower gate electrode G ₁₀ in FIG. 3 (a) ~ (c), the planarization insulating this lower gate electrode G ₁₀ Membrane 12
Can be formed by other methods.

That is, FIG. 4 shows another method of forming the planarizing insulating film 12 and the lower gate electrode G _10.

This method, after forming as shown in FIG. 4 in the manner described above the lower gate electrode G ₁₀ and the lower gate line GL ₁₀ (a), as shown in FIG. 4 (b), the whole surface of the substrate 11 Then, an insulating film 12A made of PSG (phosphorus glass) is deposited to a thickness of about 4000 mm by a low pressure CVD method, and thereafter, 850 ° C to 1000 ° C.
The insulating film 12A by a reflow process of heating for 30 minutes or more in a steam atmosphere and flattening of, as shown in FIG. 4 (c), the film thickness of the lower gate line GL ₁₀ is about 4000 Å, the lower gate electrode G _This is a method of forming a flattening insulating film 12 having a thickness of about 1000 ° on the top surface ₁₀ .

Even in the case of forming the planarizing insulating film 12 and the lower gate electrode G ₁₀ in the Figure 4 method, the Hereafter, producing a thin film transistor memory in the process shown in the FIG. 3 (d) ~ (i) I do.

FIG. 5 is an equivalent circuit diagram of the thin film transistor memory, the thin film transistor memory, in one of the thin film transistor, a structure formed by laminating a memory transistor T ₁₀ and two select transistors T _20, T ₂₀ ing. In the FIG. 5 shows an equivalent circuit of one thin film transistor memory, but the thin film transistor memory, lower gate lines G ₁₀ and the upper gate line G
They are formed at the intersections of ₂₀ and the source and drain lines SL and DL, respectively.

Writing, erasing, and reading of this thin film transistor memory are performed as follows.

In FIG. 5, (a) shows a voltage application state at the time of writing, (b) shows an erasing time, and (c) shows a voltage applying state at the time of reading.

First, writing will be described. At the time of writing, as shown in FIG. 5A, the source electrode S and the drain electrode D are grounded (GND) and the selection transistors T ₂₀ and T _20
20 by applying a ON voltage V _ON to the gate electrode G ₂₀ of, applying a write voltage + V _P to the gate electrode G ₁₀ of the memory transistor T _10. When such a voltage is applied, the two select transistors T ₂₀ and T ₂₀ are turned on, and a write voltage + _VP is applied between the gate electrode G ₁₀ and the source and drain electrodes S and D of the memory transistor T ₁₀ , and the lower part is turned on. charge in the memory region of the gate insulating film 13 (the gate electrode G ₁₀ facing portion of the memory insulation film 13b) is trapped, the memory transistor T ₁₀ is a write state (OFF state).

The erasing, as shown in FIG. 5 (b), while grounding the source electrode S and the drain electrode D (GND), ON voltage V _ON to the gate electrode G ₂₀ of the select transistor T ₂₀
Was applied to the gate electrode G ₁₀ of the memory transistor T _10,
The write voltage + V _P applies an erase repression -V _P of reverse potential.
When such a voltage is applied, the selection transistors T ₂₀ and T _20
20 is turned on, the memory of the gate electrode G ₁₀ of the memory transistor T ₁₀ source, drain electrodes S, the potential difference between the write voltage + V _P and reverse potential between D (-V _P) bottom occurs gate insulating film 13 charge that is trapped in the area is released, the memory transistor T ₁₀ is the erased state (oN state).

On the other hand, during reading, as shown in FIG. 5 (c), with grounding the gate electrode G ₁₀ and the source electrode S of the memory transistor T ₁₀ (GND), the gate electrode G ₂₀ of the selection transistors T _20, T ₂₀ to apply the oN voltage V _oN, and applies the read voltage V _D to a drain electrode D. When such a voltage is applied,
Since current flows from the drain electrode D to the source electrode S if erased memory transistor T ₁₀ state (ON state), the current if the memory transistor T ₁₀ is a write state (OFF state) does not flow, the source electrode S Read data corresponding to the presence or absence of a current flowing through the source line.

That is, the thin film transistor memory includes a lower gate insulating film 13 and the semiconductor layer 14 and the source having a charge accumulation function and the lower gate electrode G _10, the drain electrode S, on the memory transistor T ₁₀ which is formed by laminating and D, by laminating the upper gate insulating film 16 upper gate electrode G ₂₀ without the charge storage capabilities, the semiconductor layer 14 and the source, drain electrodes S,
In this example, two select transistors T ₂₀ and T ₂₀ sharing D with the memory transistor T ₁₀ are configured.

This thin film transistor memory is a memory transistor
A selection thin film transistor T _20, T ₂₀ because is constructed by laminating a T _10, reduced to the integrated device area of the transistor memory composed of the memory transistor T ₁₀ and the selection transistor T _20, T ₂₀ You can increase the degree.
Further, in this thin film transistor memory, the semiconductor layer 14
And the source and drain electrodes S and D are connected to the memory transistor T
Because it is shared by ₁₀ and select transistors T ₂₀ and T ₂₀ ,
It can be easily manufactured with a small number of steps as described above.

Then, in the thin film transistor memory, a lower gate electrode G _10, and protrudes to face the portion of the semiconductor layer 14 on the lower gate line GL ₁₀ formed on the substrate 11, the lower portion of the lower gate insulating film 13 the gate electrode G ₁₀ and the portion facing the memory area, further on the lower gate line GL ₁₀ and the lower gate electrode G _10, covered thick lower gate line GL _10, lower gate electrode G ₁₀ is a planarization insulating covering thin A film 12 is formed, and a lower gate insulating film 13 is formed on the planarizing insulating film 12, so that a semiconductor layer 14 is formed.
Parts other than the corresponding parts of the memory area and the lower gate line GL
Insulating film between ₁₀ (planarizing insulating film 12 and lower gate insulating film
A layer thickness of 13) was thick, further, an upper gate insulating film 16 between the semiconductor layer 14 and the upper gate electrode G _20, was formed on the entire whole lower insulating film 16a to cover its surface of the semiconductor layer 14 etched By forming a laminated film including the stopper insulating film 16b and the upper insulating film 16c formed thereon corresponding to the memory region, the thickness of the upper gate insulating film 16 is reduced by the thickness of the semiconductor layer 14 corresponding to the memory region. due to the thicker in top of, (between the lower gate line GL ₁₀₎ between the lower gate electrode G ₁₀ is the gate electrode of the select transistor T ₂₀ region and the memory transistor T ₁₀ of the semiconductor layer 14, and the semiconductor layer be reliably insulated from each between 14 memory transistor T ₁₀ area top gate electrode G ₂₀ is the gate electrode of the selection and (portion corresponding to a memory region of the lower gate insulating film 13) transistors T _20, T ₂₀ of But Kill. Therefore, according to the thin film transistor memory, not the selecting transistor T ₁₀ malfunctions due to the influence of the gate voltage applied to the gate electrode (the lower gate electrode) G ₁₀ of the memory transistor T _10, also the memory transistor T ₁₀ is selected since it is no malfunction under the influence of the gate voltage applied to transistor T _20, the gate electrode of T ₂₀ (upper gate electrode) G _20, the semiconductor layer 14 and the source, drain electrodes S,
Selected memory transistor T ₁₀ that share the D transistor
Even though T ₂₀ and T ₂₀ are stacked, the memory transistor T ₁₀ and the select transistors T ₂₀ and T ₂₀ can operate normally to perform stable writing, erasing, and reading.

Moreover, in this thin film transistor memory, the upper gate insulating film 16 is formed on the entire surface of the lower insulating film 16a, and an insulating film 16b for etching stopper is formed thereon.
Since the lower insulating film 16a is not damaged during etching for patterning the upper insulating film 16 into a shape corresponding to the memory region,
Therefore, the upper gate insulating film 16 whose thickness is increased on the portion corresponding to the memory region of the semiconductor layer 14 is formed with good yield, and the reliability of the thin film transistor memory can be improved.

Further, in the thin film transistor memory, the source of the upper gate insulating film 16, the drain electrode S, since the thicker the film thickness of the outer portion from the almost center opposite to the position and D, the upper gate electrode G ₂₀ and the source, drain The withstand voltage between the electrodes S and D is also sufficient.

Incidentally, the thin film transistor memory of the embodiment has for one memory transistor T ₁₀ is obtained with two select transistors T _20, the present invention is provided with one selection transistor for one memory transistor It can also be applied to a thin film transistor memory.

6 to 8 show a second embodiment of the present invention. TFT memory of this embodiment, one of the selection transistors T for one memory transistor T ₁₀
Which was equipped with a _20, FIGS. 6 and 7 is a cross-sectional view and a plan view of the thin film transistor memory, FIG. 8 is an equivalent circuit diagram of the thin film transistor memory.

TFT memory of this embodiment, the lower gate electrode G ₁₀ is the gate electrode of the memory transistor T _10,
The lower gate line GL ₁₀ formed on the substrate 11 is formed so as to protrude so as to face a part of the semiconductor layer 14, and a portion of the lower gate insulating film 13 facing the lower gate electrode G ₁₀ is used as a memory region, on the gate line GL ₁₀ and the lower gate electrode G _10, lower gate electrode G ₁₀ covers thickened lower gate line GL ₁₀ is to form a planarization insulating film 12 covering thin, bottom on top of the planarization insulating film 12 Forming a gate insulating film 13;
And the upper gate electrode G ₂₀ is the gate electrode of the select transistor T ₂₀ is thereby formed to face the entire semiconductor layer 14, the upper gate insulating film 16, the lower insulating film 16a and the surface covering the entire semiconductor layer 14 By forming a laminated film including an etching stopper insulating film 16b formed over the entirety and an upper insulating film 16c formed thereon corresponding to the memory region, the thickness of the upper gate insulating film 16 is reduced to the memory region. which was thicker at top of a portion corresponding to the memory transistor T ₁₀ has a lower gate electrode G _10, a planarizing insulating film 12 and the lower gate insulating film 13, semiconductor layer 14 and the source, drain electrodes S, and D is constituted by the selection transistor T _10, the semiconductor layer 14 and the source, drain electrodes S, and D, a thin portion of the upper gate insulating film 16,
It is constituted by an upper gate electrode G _20.

Incidentally, the thin film transistor memory of this embodiment, only by one of the selection transistors T _20, since the basic structure is not the same as the first embodiment, detailed description of the structure are denoted by the same reference numerals in FIG. Omitted. Writing, erasing, and reading of the thin film transistor memory of this embodiment are performed in the first mode.
This can be performed in the same manner as in the thin film transistor memory of the embodiment.

〔The invention's effect〕

According to the thin film transistor memory of the present invention, a memory gate insulating film and a memory gate electrode are formed on one surface of a semiconductor layer, and a source and drain electrode, a gate insulating film, and a gate electrode for a select transistor are formed on the other surface of the semiconductor layer. Is formed, the memory gate electrode and the select transistor gate electrode are laminated, and the area can be reduced as compared with the case where they are formed side by side on the same plane.

[Brief description of the drawings]

1 to 5 show a first embodiment of the present invention. FIGS. 1 and 2 are sectional views and plan views of a thin film transistor memory, FIG. FIG. 4 is a process diagram showing another method for forming the lower gate electrode and the planarizing insulating film, and FIG. 5 is an equivalent circuit diagram of the thin film transistor memory. 6 to 8 show a second embodiment of the present invention. FIGS. 6 and 7 are sectional views and plan views of a thin film transistor memory, and FIG. 8 is an equivalent circuit diagram of the thin film transistor memory. is there. FIG. 9 is an equivalent circuit diagram of a conventional thin film transistor memory. 11 ...... substrate, T ₁₀ ...... memory for thin film transistor, T ₂₀ ...
… Selection thin film transistor, GL ₁₀ …… Lower gate line, G ₁₀ …… Lower gate electrode, 12 …… Planarization insulating film, 13
... lower gate insulating film, 14 ... semiconductor layer, 15 ... ohmic contact layer, S ... source electrode, D ... drain electrode, 16 ... upper gate insulating film, 16a ... lower insulating film, 1
6b ...... etching stopper insulating film, 16c ...... upper insulating film, G ₂₀ ...... upper gate electrode.

Claims (1)

(57) [Claims] 1. A semiconductor layer, a memory gate insulating film formed on one surface of the semiconductor layer, and a memory gate electrode formed on the memory gate insulating film on one surface of the semiconductor layer. A source / drain electrode formed on the other surface side of the semiconductor layer, and a portion formed over the other surface of the semiconductor layer and the source / drain electrode and corresponding to the memory gate electrode region is another portion. A thin film transistor memory comprising: a gate insulating film having a greater thickness; and a gate electrode for a select transistor formed on the gate insulating film so as to include a region corresponding to substantially the entire surface of the semiconductor layer region.