JP2964635B2 - Method for manufacturing semiconductor memory device - Google Patents
Method for manufacturing semiconductor memory deviceInfo
- Publication number
- JP2964635B2 JP2964635B2 JP2340913A JP34091390A JP2964635B2 JP 2964635 B2 JP2964635 B2 JP 2964635B2 JP 2340913 A JP2340913 A JP 2340913A JP 34091390 A JP34091390 A JP 34091390A JP 2964635 B2 JP2964635 B2 JP 2964635B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- forming
- polycrystalline silicon
- film
- entire surface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Landscapes
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、MOS型不揮発性半導体記憶装置の製造方法
に関し、特に、浮遊ゲート電極を有するMOS型不揮発性
半導体記憶装置の製造方法に関する。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a MOS nonvolatile semiconductor memory device, and more particularly, to a method for manufacturing a MOS nonvolatile semiconductor memory device having a floating gate electrode.
従来、この種のMOS型不揮発性半導体装置の製造方法
は第2図に示す様に、まず半導体基板1上に絶縁膜2と
して例えば300Å〜1000Åの厚さの熱酸化膜を形成し
(第2図(a))、公知のフォトリソグラフィー技術を
用いて所定の領域の絶縁膜2及び半導体基板1の一部を
順次除去して溝を形成し(第2図(b))、フォトレジ
スタ4を除去した後に埋込み絶縁膜5として例えば化学
気相成長法により酸化膜を10000Å〜20000Å形成し、80
0℃〜1000℃程度の熱処理を行なって埋込み絶縁膜5を
リフローして平坦化し(第2図(c))、全面を半導体
基板1が露出する迄エッチバックし、ゲート絶縁膜7と
して例えば100Å〜500Åの熱酸化膜を形成し(第2図
(d))、全面に不純物、例えば燐を含有した第1の多
結晶シリコン膜8を形成し(第2図(e))、公知のフ
ォトリソグラフィー技術により所定の領域の第1の多結
晶シリコン膜8を除去し(第2図(f))、フォトレジ
スト9を除去した後に第1の多結晶シリコン膜上に第2
の絶縁膜10として例えば200Å〜1000Åの熱酸化膜を形
成し、不純物、例えば燐を含有した第2の多結晶シリコ
ン膜11を形成する工程を有していた(第2図(g))。2. Description of the Related Art Conventionally, in this type of manufacturing method of a MOS type nonvolatile semiconductor device, as shown in FIG. 2, a thermal oxide film having a thickness of, for example, 300 to 1000 mm is formed as an insulating film 2 on a semiconductor substrate 1 (see FIG. (FIG. 2 (a)), a part of the insulating film 2 and a part of the semiconductor substrate 1 in a predetermined region are sequentially removed by using a known photolithography technique to form a groove (FIG. 2 (b)), and the photoresist 4 is formed. After the removal, an oxide film is formed as a buried insulating film 5 by, for example, a chemical vapor deposition method in an amount of 10,000 to 20,000, and
The embedded insulating film 5 is reflowed and flattened by performing a heat treatment at about 0 ° C. to 1000 ° C. (FIG. 2C), and the entire surface is etched back until the semiconductor substrate 1 is exposed. A thermal oxide film of about 500 ° is formed (FIG. 2 (d)), and a first polycrystalline silicon film 8 containing impurities, for example, phosphorus is formed on the entire surface (FIG. 2 (e)). The first polycrystalline silicon film 8 in a predetermined region is removed by a lithography technique (FIG. 2F), and after removing the photoresist 9, a second polycrystalline silicon film is formed on the first polycrystalline silicon film.
A thermal oxide film of, for example, 200.degree. To 1000.degree. Is formed as the insulating film 10, and a step of forming a second polycrystalline silicon film 11 containing impurities, for example, phosphorus (FIG. 2 (g)).
上述した従来のMOS型不揮発性半導体記憶装置の製造
方法は、第2図(f)に示す様に、第1の多結晶シリコ
ン膜8をパターニングする際にフォトリソグラフィー技
術を用いている為に以下の2つの問題点がある。The conventional method of manufacturing a MOS nonvolatile semiconductor memory device described above uses a photolithography technique when patterning the first polycrystalline silicon film 8 as shown in FIG. There are two problems.
第1の多結晶シリコン膜の分離幅L1はフォトリソグ
ラフィー技術によって決まる為、フォトリソグラフィー
技術での最小分離幅以下には出来ない。Since the separation width L1 of the first polycrystalline silicon film is determined by the photolithography technology, it cannot be smaller than the minimum separation width by the photolithography technology.
第1の多結晶シリコン膜の分離をフォトリソグラフ
ィー技術によって行なっている為、位置合せずれが生じ
る。この為、位置合せずれに対する余裕を持たせなけれ
ばならず、L2を大きくしなければならない。Since the separation of the first polycrystalline silicon film is performed by the photolithography technique, misalignment occurs. For this reason, a margin must be provided for misalignment, and L2 must be increased.
結局、以上の2つの問題点から素子分離幅L3は大きく
なってしまい、MOS型不揮発性半導体記憶装置が大きく
なってしまう。As a result, the element isolation width L3 becomes large due to the above two problems, and the MOS nonvolatile semiconductor memory device becomes large.
本発明のMOS型不揮発性半導体記憶装置の製造方法
は、半導体基板上に絶縁膜及び多結晶シリコン膜を順次
形成する工程と、公知のフォトリソグラフィー技術を用
いて所定の領域の多結晶シリコン膜及び絶縁膜及び半導
体基板の一部を除去して前記半導体基板に溝を形成する
工程と、全面に溝が全て埋まらない膜厚の第1の埋込み
絶縁膜を形成する工程と、全面に溝を全て埋める膜厚の
第2の絶縁膜を形成する工程と、第1の埋込み絶縁膜の
表面が露出する迄全面をエッチバックする工程と、多結
晶シリコン膜の表面が露出する迄第1の埋込み絶縁膜を
選択的にエッチバックする工程と、全面の多結晶シリコ
ン膜及び絶縁膜を順次除去しゲート絶縁膜を形成する工
程と、全面に不純物を含有した第1の多結晶シリコン膜
を形成する工程と、全面に平坦化物質を形成して表面を
平坦化した後に、第2の埋込み絶縁膜が露出する迄全面
をエッチバックする工程と、平坦化物質を除去した後に
第1の多結晶シリコン膜上に第2の絶縁膜を形成し全面
に不順物を含有した第2の多結晶シリコン膜を形成する
工程とを有していること、若しくは、 半導体基板上に絶縁膜及び多結晶シリコン膜を順次形
成した後に、第1の絶縁膜を形成する工程と、公知のフ
ォトリソグラフィー技術を用いて所定の領域の第1の絶
縁膜及び多結晶シリコン膜及び絶縁膜及び半導体基板の
一部を除去して半導体基板に溝を形成する工程と、全面
に溝が全て埋まらない膜厚の第1の埋込み絶縁膜を形成
する工程と、全面に溝を全て埋める膜厚の第2の絶縁膜
を形成する工程と、第1の埋込み絶縁膜の表面が露出す
る迄全面をエッチバックする工程と、多結晶シリコン膜
の表面が露出する迄第1の埋込み絶縁膜及び第1の絶縁
膜を選択的にエッチバックする工程と、全面の多結晶シ
リコン膜及び絶縁膜を順次除去しゲート絶縁膜を形成す
る工程と、全面に不純物を含有した第1の多結晶シリコ
ン膜を形成する工程と、全面に平坦化物質を形成して表
面を平坦化した後に、第2の埋込み絶縁膜が露出する迄
全面をエッチバックする工程と、平坦化物質を除去した
後に第1の多結晶シリコン膜上に第2の絶縁膜を形成し
全面に不純物を含有した第2の多結晶シリコン膜を形成
する工程とを有している事、若しくは、 半導体基板上にゲート絶縁膜及び不純物を含有した多
結晶シリコン膜を順次形成する工程と、公知のフォトリ
ソグラフィー技術を用いて所定の領域の多結晶シリコン
膜及び絶縁膜及び半導体基板の一部を除去して半導体基
板に溝を形成する工程と、全面に溝が全て埋まらない膜
厚の第1の埋込み絶縁膜を形成する工程と、全面に溝を
全て埋める膜厚の第2の絶縁膜を形成する工程と、第1
の埋込み絶縁膜の表面が露出する迄全面をエッチバック
する工程と、多結晶シリコン膜の表面が露出する迄第1
の埋込み絶縁膜を選択的にエッチバックする工程と、全
面に不純物を含有した第1の多結晶シリコン膜を形成す
る工程と、全面に平坦化物質を形成して表面を平坦化し
た後に、第2の埋込み絶縁膜が露出する迄全面をエッチ
バックする工程と、平坦化物質を除去した後に第1の多
結晶シリコン膜上に第2の絶縁膜を形成し全面に不純物
を含有した第2の多結晶シリコン膜を形成する工程とを
有していること、若しくは、 半導体基板上にゲート絶縁膜及び不純物を含有した多
結晶シリコン膜を順次形成した後に、第1の絶縁膜を形
成する工程と、公知のフォトリソグラフィー技術を用い
て所定の領域の第1の絶縁膜及び多結晶シリコン膜及び
ゲート絶縁膜及び半導体基板の一部を除去して半導体基
板に溝を形成する工程と、全面に溝が全て埋まらない膜
厚の第1の埋込み絶縁膜を形成する工程と、全面に溝を
全て埋める膜厚の第2の絶縁膜を形成する工程と、第1
の埋込み絶縁膜の表面が露出する迄全面をエッチバック
する工程と、多結晶シリコン膜の表面が露出する迄第1
の埋込み絶縁膜及び第1の絶縁膜を選択的にエッチバッ
クする工程と、全面に不純物を含有した第1の多結晶シ
リコン膜を形成する工程と、全面に平坦化物質を形成し
て表面を平坦化した後に、第2の埋込み絶縁膜が露出す
る迄全面をエッチバックする工程と、平坦化物質を除去
した後に第1の多結晶シリコン膜上に第2の絶縁膜を形
成し全面に不純物を含有した第2の多結晶シリコン膜を
形成する工程とを有している。A method of manufacturing a MOS nonvolatile semiconductor memory device according to the present invention includes the steps of sequentially forming an insulating film and a polycrystalline silicon film on a semiconductor substrate; and forming a polycrystalline silicon film in a predetermined region using a known photolithography technique. Forming a groove in the semiconductor substrate by removing the insulating film and part of the semiconductor substrate, forming a first buried insulating film having a film thickness that does not completely fill the entire surface of the semiconductor substrate, A step of forming a second insulating film having a thickness to be buried, a step of etching back the entire surface until the surface of the first buried insulating film is exposed, and a step of forming the first buried insulating film until the surface of the polycrystalline silicon film is exposed. A step of selectively etching back the film, a step of sequentially removing the polycrystalline silicon film and the insulating film on the entire surface to form a gate insulating film, and a step of forming a first polycrystalline silicon film containing impurities on the entire surface And the whole A step of forming a planarizing material to planarize the surface and then etching back the entire surface until the second buried insulating film is exposed; and a step of removing a planarizing material to remove a second planarizing material on the first polycrystalline silicon film. Forming a second polycrystalline silicon film containing an undesired substance on the entire surface, or after sequentially forming the insulating film and the polycrystalline silicon film on the semiconductor substrate. Forming a first insulating film, and removing a part of the first insulating film, the polycrystalline silicon film, the insulating film, and the semiconductor substrate in a predetermined region using a known photolithography technique to form a semiconductor substrate. A step of forming a groove, a step of forming a first buried insulating film having a film thickness that does not entirely fill the groove, a step of forming a second insulating film having a film thickness that completely fills the groove over the entire surface, 1 until the surface of the buried insulating film is exposed. Etch-back, selectively etching back the first buried insulating film and the first insulating film until the surface of the polycrystalline silicon film is exposed, and sequentially removing the entire surface of the polycrystalline silicon film and the insulating film. Removing, forming a gate insulating film, forming a first polycrystalline silicon film containing impurities on the entire surface, forming a planarizing material on the entire surface, planarizing the surface, and then forming a second buried layer. A step of etching back the entire surface until the insulating film is exposed; and a step of forming a second insulating film on the first polycrystalline silicon film after removing the planarizing material and then including a second polycrystalline silicon containing impurities on the entire surface. A step of forming a film, or a step of sequentially forming a gate insulating film and a polycrystalline silicon film containing impurities on a semiconductor substrate, and a step of forming a predetermined region using a known photolithography technique. Many Forming a groove in the semiconductor substrate by removing a portion of the crystalline silicon film, the insulating film, and the semiconductor substrate; forming a first buried insulating film having a film thickness that does not completely fill the groove on the entire surface; Forming a second insulating film having a thickness that fills all the grooves;
Etching back the entire surface until the surface of the buried insulating film is exposed, and the first step until the surface of the polycrystalline silicon film is exposed.
Selectively etching back the buried insulating film, forming a first polycrystalline silicon film containing impurities on the entire surface, forming a planarizing material on the entire surface, and planarizing the surface. A step of etching back the entire surface until the buried insulating film 2 is exposed, and forming a second insulating film on the first polycrystalline silicon film after removing the planarizing material, and a second step including impurities on the entire surface. Having a step of forming a polycrystalline silicon film, or forming a first insulating film after sequentially forming a gate insulating film and a polycrystalline silicon film containing impurities on a semiconductor substrate; Forming a groove in the semiconductor substrate by removing a part of the first insulating film, the polycrystalline silicon film, the gate insulating film and the semiconductor substrate in a predetermined region by using a known photolithography technique; Is all buried Forming a first buried insulating film having a thickness not exceeding the thickness of the first insulating film;
Etching back the entire surface until the surface of the buried insulating film is exposed, and the first step until the surface of the polycrystalline silicon film is exposed.
Selectively etching back the buried insulating film and the first insulating film, forming a first polycrystalline silicon film containing impurities on the entire surface, and forming a planarizing material on the entire surface to form a surface. After planarization, a step of etching back the entire surface until the second buried insulating film is exposed, and after removing the planarizing material, forming a second insulating film on the first polycrystalline silicon film and forming an impurity on the entire surface. Forming a second polycrystalline silicon film containing
次に、本発明について図面を参照して説明する。第1
図は本発明の一実施例の縦断面図である。まず、半導体
基板1上に絶縁膜2を例えば熱酸化法により200〜1000
Å形成し、その上に多結晶シリコン膜3を例えば化学気
相成長法により1000〜4000Å形成し(第1図(a))、
公知のフォトリソグラフィー技術を用いて所定の領域の
多結晶シリコン膜3,絶縁膜2及び半導体基板1の一部を
順次エッチング除去して溝を形成し(第1図(b))、
全面に第1の埋込み絶縁膜5を例えば化学気相成長法に
より酸化膜を1000Å〜10000Å形成し、続いて全面に第
2の埋込み絶縁膜6を例えば化学気相成長法により窒化
膜を1000Å〜10000Å形成し(第1図(c))、全面の
第2の埋込み絶縁膜6を第1の埋込み絶縁膜5の表面が
露出する迄エッチバックし、続いて、第1の埋込み絶縁
膜5を選択的に例えば弗酸で多結晶シリコン膜3の表面
が露出する迄エッチングし(第1図(d))、多結晶シ
リコン膜3及び絶縁膜2を順次除去してゲート酸化膜7
を例えば熱酸化法により100〜1000Å形成し(第1図
(e))、全面に、不純物例えば燐を含有した第1の多
結晶シリコン膜を例えば化学気相成長法により1000〜60
00Å形成し、全面に平坦化物質としてフォトレジスト9
を形成して表面を平坦化し(第1図(f))、全面を第
2の埋込み絶縁膜6の表面が露出する迄エッチバックし
て、第1の多結晶シリコン膜8を第2の埋込み絶縁膜6
の幅L1で分離し(第1図(g))、フォトレジスト9を
除去した後に第1の多結晶シリコン膜8上に第2の絶縁
膜10を例えば熱酸化法により100〜1000Å形成し、不純
物例えば燐を含有した第2の多結晶シリコン膜11を例え
ば化学気相成長法により1000〜6000Å形成する(第1図
(h))。Next, the present invention will be described with reference to the drawings. First
The figure is a longitudinal sectional view of one embodiment of the present invention. First, the insulating film 2 is formed on the semiconductor substrate 1 by, for example, thermal oxidation to form a film 200 to 1000.
Is formed, and a polycrystalline silicon film 3 is formed thereon by, for example, a chemical vapor deposition method to a thickness of 1000 to 4000 (FIG. 1A).
Using a known photolithography technique, a part of the polycrystalline silicon film 3, the insulating film 2, and a part of the semiconductor substrate 1 in a predetermined region is sequentially etched and removed to form a groove (FIG. 1B).
A first buried insulating film 5 is formed on the entire surface by, for example, an oxide film having a thickness of 1000Å10000Å by a chemical vapor deposition method. Then, the second buried insulating film 6 is etched back until the surface of the first buried insulating film 5 is exposed, and then the first buried insulating film 5 is removed. The polycrystalline silicon film 3 is selectively etched with, for example, hydrofluoric acid until the surface of the polycrystalline silicon film 3 is exposed (FIG. 1 (d)).
Is formed by, for example, a thermal oxidation method (FIG. 1 (e)), and a first polycrystalline silicon film containing impurities, for example, phosphorus is formed on the entire surface by, for example, a chemical vapor deposition method to have a thickness of 1000 to 60 °.
Then, a photoresist 9 is formed on the entire surface as a planarizing material.
Is formed and the surface is flattened (FIG. 1 (f)), the entire surface is etched back until the surface of the second buried insulating film 6 is exposed, and the first polycrystalline silicon film 8 is buried in the second buried insulating film 6. Insulating film 6
(FIG. 1 (g)), and after removing the photoresist 9, a second insulating film 10 is formed on the first polycrystalline silicon film 8 by, for example, a thermal oxidation method at 100 to 1000 °. A second polycrystalline silicon film 11 containing an impurity, for example, phosphorus is formed by, for example, a chemical vapor deposition method at 1000 to 6000.degree. (FIG. 1 (h)).
又、上記MOS型不揮発性半導体記憶装置を製造する際
の他の一方法に於いては、 第3図に示す様に、まず半導体基板1上に絶縁膜2を
例えば熱酸化法により200〜1000Å形成し、その上に多
結晶シリコン膜3を例えば化学気相成長法により1000〜
4000Å形成し、その上に第1の絶縁膜12として例えば化
学気相成長法による酸化膜を膜厚d2形成し(第3図
(a))、公知のフォトリソグラフィー技術を用いて所
定の領域の第1の絶縁膜12,多結晶シリコン膜3,絶縁膜
2及び半導体基板1の一部を順次エッチング除去して溝
を形成し(第3図(b))、全面に第1の埋込み絶縁膜
5を例えば化学気相成長法により酸化膜を1000〜10000
Å形成し、続いて全面に第2の埋込み絶縁膜6を例えば
化学気相成長法により窒化膜を1000〜10000Å形成し
(第3図(c))、全面の第2の埋込み絶縁膜6を第1
の埋込み絶縁膜5の表面が露出する迄エッチバックし、
続いて、第1の埋込み絶縁膜5及び第1の絶縁膜12を選
択的に、例えば弗酸で多結晶シリコン膜3の表面が露出
する迄エッチングする(第3図(d))。この事によ
り、第2の埋込み絶縁膜6の突出部分の高さはd1+d2と
なり、膜厚がL3の半分未満と云う制限のあったd1よりも
d2の分だけ高く出来、またd2には基本的に制限は無い。
続いて以降の工程は第1図(e)〜第1図(h)と全く
同じである為省略する。In another method of manufacturing the above-mentioned MOS type nonvolatile semiconductor memory device, as shown in FIG. 3, first, an insulating film 2 is formed on a semiconductor substrate 1 by a thermal oxidation method for 200 to 1000 Å. Is formed, and a polycrystalline silicon film 3 is formed thereon by, for example, a chemical vapor deposition method.
And 4000Å is formed, the oxide film of the first insulating film 12 and to, for example, chemical vapor deposition on the film thickness d 2 is formed (FIG. 3 (a)), a predetermined region using a known photolithography technique The first insulating film 12, the polycrystalline silicon film 3, the insulating film 2, and a part of the semiconductor substrate 1 are sequentially etched to form a groove (FIG. 3B), and a first buried insulating film is formed on the entire surface. The oxide film is formed in a thickness of 1000 to 10000 by a chemical vapor deposition method, for example.
Then, a second buried insulating film 6 is formed on the entire surface by, for example, a chemical vapor deposition method to form a nitride film of 1,000 to 10,000 Å (FIG. 3C), and the second buried insulating film 6 is formed on the entire surface. First
Etch back until the surface of the buried insulating film 5 is exposed,
Subsequently, the first buried insulating film 5 and the first insulating film 12 are selectively etched with, for example, hydrofluoric acid until the surface of the polycrystalline silicon film 3 is exposed (FIG. 3D). As a result, the height of the protruding portion of the second buried insulating film 6 is d 1 + d 2 , which is smaller than d 1 , which has a limitation that the film thickness is less than half of L 3.
of the amount corresponding to d 2 can be high, also not fundamentally limited to the d 2.
Subsequently, the subsequent steps are exactly the same as those shown in FIGS. 1 (e) to 1 (h), and will not be described.
又、上記MOS型不揮発性半導体記憶装置を製造する際
の他の一方法に於いては、第4図に示す様に、まず、半
導体基板1上にゲート絶縁膜7を例えば熱酸化法により
100〜1000Å形成し、その上に不純物例えば燐を含有し
た多結晶シリコン膜3を例えば化学気相成長法により10
00〜4000Å形成し(第4図(a))、公知のフォトリソ
グラフィー技術を用いて所定の領域の多結晶シリコン膜
3,ゲート絶縁膜7及び半導体基板1の一部を順次エッチ
ング除去して溝を形成し(第4図(b))、全面に第1
の埋込み絶縁膜5を例えば化学気相成長法により酸化膜
を1000Å〜10000Å形成し、続いて全面に第2の埋込み
絶縁膜6を例えば化学気相成長法により窒化膜を1000Å
〜10000Å形成し(第4図(c))、全面の第2の埋込
み絶縁膜6を第1の埋込み絶縁膜5の表面が露出する迄
エッチバックし、続いて、第1の埋込み絶縁膜5を選択
的に、例えば弗酸で多結晶シリコン膜3の表面が露出す
る迄エッチングし(第4図(d))、全面に、不純物例
えば燐を含有した第1の多結晶シリコン膜を例えば化学
気相成長法により1000〜6000Å形成し、全面に平坦化物
質としてフォトレジスト9を形成して表面を平坦化し
(第4図(e))、全面を第2の埋込み絶縁膜6の表面
が露出する迄エッチバックして、第1の多結晶シリコン
膜8を第2の埋込み絶縁膜6の幅L1で分離し(第4図
(f))、フォトレジスト9を除去した後に第1の多結
晶シリコン膜8上に第2の絶縁膜10を例えば熱酸化法に
より100〜1000Å形成し、不純物例えば燐を含有した第
2の多結晶シリコン膜11を例えば化学気相成長法により
1000〜6000Å形成する(第4図(g))。In another method for manufacturing the above-mentioned MOS type nonvolatile semiconductor memory device, as shown in FIG. 4, first, a gate insulating film 7 is formed on a semiconductor substrate 1 by, for example, a thermal oxidation method.
A polycrystalline silicon film 3 having a thickness of 100 to 1000 ° and containing impurities such as phosphorus is formed thereon by, for example, chemical vapor deposition.
The polycrystalline silicon film is formed in a predetermined area by using a known photolithography technique.
3. A groove is formed by sequentially etching and removing a part of the gate insulating film 7 and the semiconductor substrate 1 (FIG. 4 (b)), and the first
The buried insulating film 5 is formed, for example, by an oxide film of 1000-10000 ° by the chemical vapor deposition method, and then the second buried insulating film 6 is formed on the entire surface by the nitride film of 1000 例 え ば by the chemical vapor deposition method.
.About.10000.degree. (FIG. 4 (c)), the second buried insulating film 6 on the entire surface is etched back until the surface of the first buried insulating film 5 is exposed, and then the first buried insulating film 5 is formed. Is selectively etched with, eg, hydrofluoric acid until the surface of the polycrystalline silicon film 3 is exposed (FIG. 4 (d)), and a first polycrystalline silicon film containing impurities, eg, phosphorus, is chemically The surface is planarized by forming a photoresist 9 as a planarizing material on the entire surface (FIG. 4E), and the surface of the second buried insulating film 6 is exposed on the entire surface. Then, the first polycrystalline silicon film 8 is separated by the width L1 of the second buried insulating film 6 (FIG. 4F), and after removing the photoresist 9, the first polycrystalline silicon film 8 is removed. A second insulating film 10 is formed on the silicon film 8 by, for example, a thermal oxidation method to a thickness of 100 to 1000. By the second polycrystalline silicon film 11 containing phosphorus if example, for example, chemical vapor deposition
A thickness of 1000 to 6000 is formed (FIG. 4 (g)).
又、その他の一方法として、第3図に於いて、絶縁膜
2をゲート絶縁膜7と置き換えて第3図(a)〜第3図
(d)を行なった後に、第4図(e)〜第4図(g)を
行なう事も出来る。As another method, after replacing the insulating film 2 with the gate insulating film 7 in FIG. 3 and performing FIGS. 3 (a) to 3 (d), FIG. 4 (g) can also be performed.
以上説明した様に本発明は、第1の多結晶シリコン膜
の分離をフォトリソグラフィー技術によらず、溝に埋込
まれた溝の幅よりも小さい幅の第2の埋込み絶縁膜を利
用したエッチバックにより行なっている為に以下の効果
がある。As described above, according to the present invention, the first polycrystalline silicon film is separated by using the second buried insulating film having a width smaller than the width of the groove buried in the groove, without using the photolithography technique. The following effects are obtained because the backing is performed.
第1の多結晶シリコン膜の分離幅をフォトリソグラ
フィー技術の分離限界より小さく出来る。The separation width of the first polycrystalline silicon film can be made smaller than the separation limit of the photolithography technique.
第1の多結晶シリコン膜の分離が素子分離の溝に対
して自己整合的に形成出来る。The isolation of the first polycrystalline silicon film can be formed in a self-aligned manner with respect to the element isolation groove.
即ち、第1図(g)に示す素子分離の溝の幅L3=L1+
2×L2をフォトリソグラフィー技術の最小分離幅と同一
になる迄小さく出来る。That is, the width L3 of the element isolation groove shown in FIG.
2 × L2 can be reduced until it becomes the same as the minimum separation width of the photolithography technology.
また、第1の多結晶シリコン膜の分離後の断面形状が
凹状になっており、従来より第2の多結晶シリコン膜と
の対向面積が増大し、容量値を増加させる事が出来るの
で、情報の書込み及び消去スピードを従来より速く出来
る(第5図)。In addition, since the cross-sectional shape of the first polycrystalline silicon film after separation is concave, the area facing the second polycrystalline silicon film is increased, and the capacitance value can be increased. Can be written and erased faster than before (FIG. 5).
第1図(a)〜第1図(h)は本発明の一実施例の縦断
面図。 第2図(a)〜第2図(g)は従来例の縦断面図。 第3図(a)〜第3図(d)は本発明の第2の実施例の
縦断面図。 第4図(a)〜第4図(g)は本発明の第3の実施例の
縦断面図。 第5図は本発明の特性改善効果を示す図。 1……半導体基板、2……絶縁膜、3……多結晶シリコ
ン膜、4,9……フォトレジスト、5……第1の埋込み絶
縁膜、6……第2の埋込み絶縁膜、7……ゲート絶縁
膜、8……第1の多結晶シリコン膜、10……第2の絶縁
膜、11……第2の多結晶シリコン膜、12……第1の絶縁
膜。1 (a) to 1 (h) are longitudinal sectional views of one embodiment of the present invention. 2 (a) to 2 (g) are longitudinal sectional views of a conventional example. 3 (a) to 3 (d) are longitudinal sectional views of a second embodiment of the present invention. 4 (a) to 4 (g) are longitudinal sectional views of a third embodiment of the present invention. FIG. 5 is a view showing the characteristic improvement effect of the present invention. DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Insulating film, 3 ... Polycrystalline silicon film, 4,9 ... Photoresist, 5 ... First buried insulating film, 6 ... Second buried insulating film, 7 ... ... Gate insulating film, 8 first polycrystalline silicon film, 10 second insulating film, 11 second polycrystalline silicon film, 12 first insulating film.
フロントページの続き (58)調査した分野(Int.Cl.6,DB名) H01L 21/8247 H01L 27/115 H01L 29/788 H01L 29/792 Continuation of the front page (58) Field surveyed (Int.Cl. 6 , DB name) H01L 21/8247 H01L 27/115 H01L 29/788 H01L 29/792
Claims (4)
導体記憶装置に於いて、半導体基板上に絶縁膜及び多結
晶シリコン膜を順次形成する工程と、公知のフォトリソ
グラフィー技術を用いて所定の領域の前記多結晶シリコ
ン膜及び前記絶縁膜及び前記半導体基板の一部を除去し
て前記半導体基板に溝を形成する工程と、全面に前記溝
が全て埋まらない膜厚の第1の埋込み絶縁膜を形成する
工程と、全面に前記溝を全て埋める膜厚の第2の絶縁膜
を形成する工程と、前記第1の埋込み絶縁膜の表面が露
出する迄全面をエッチバックする工程と、前記多結晶シ
リコン膜の表面が露出する迄前記第1の埋込み絶縁膜を
選択的にエッチバックする工程と、全面の前記多結晶シ
リコン膜及び前記絶縁膜を順次除去しゲート絶縁膜を形
成する工程と、全面に不純物を含有した第1の多結晶シ
リコン膜を形成する工程と、全面に平坦化物質を形成し
て表面を平坦化した後に、前記第2の埋込み絶縁膜が露
出する迄全面をエッチバックする工程と、前記平坦化物
質を除去した後に前記第1の多結晶シリコン膜上に第2
の絶縁膜を形成し全面に不純物を含有した第2の多結晶
シリコン膜を形成する工程とを有する事を特徴とするMO
S型不揮発性半導体記憶装置の製造方法。In a MOS nonvolatile semiconductor memory device having a floating gate electrode, a step of sequentially forming an insulating film and a polycrystalline silicon film on a semiconductor substrate, and a step of forming a predetermined region using a known photolithography technique. Forming a groove in the semiconductor substrate by removing a part of the polycrystalline silicon film, the insulating film and the semiconductor substrate, and forming a first buried insulating film having a film thickness that does not completely fill the groove on the entire surface. Forming, forming a second insulating film on the entire surface to a thickness that fills the entire groove, etching back the entire surface until the surface of the first buried insulating film is exposed, Selectively etching back the first buried insulating film until the surface of the silicon film is exposed; forming a gate insulating film by sequentially removing the polycrystalline silicon film and the insulating film from the entire surface; A step of forming a first polycrystalline silicon film containing impurities and a step of forming a planarizing material on the entire surface to planarize the surface and then etching back the entire surface until the second buried insulating film is exposed; Removing the planarizing material, forming a second layer on the first polycrystalline silicon film.
Forming an insulating film and forming a second polycrystalline silicon film containing impurities on the entire surface.
A method for manufacturing an S-type nonvolatile semiconductor memory device.
膜を順次形成した後に、第1の絶縁膜を形成する工程
と、公知のフォトリソグラフィー技術を用いて所定の領
域の前記第1の絶縁膜及び前記多結晶シリコン膜及び前
記絶縁膜及び前記半導体基板の一部を除去して前記半導
体基板に溝を形成する工程と、全面に前記溝が全て埋ま
らない膜厚の第1の埋込み絶縁膜を形成する工程と、全
面に溝を全て埋める膜厚の第2の絶縁膜を形成する工程
と、前記第1の埋込み絶縁膜の表面が露出する迄全面を
エッチバックする工程と、前記多結晶シリコン膜の表面
が露出する迄前記第1の埋込み絶縁膜及び第1の絶縁膜
を選択的にエッチバックする工程を有する事を特徴とす
る第1項記載のMOS型不揮発性半導体記憶装置の製造方
法。A step of forming a first insulating film after forming an insulating film and a polycrystalline silicon film on the semiconductor substrate in sequence, and a step of forming the first insulating film in a predetermined region using a known photolithography technique. Forming a groove in the semiconductor substrate by removing the film, the polycrystalline silicon film, the insulating film, and a part of the semiconductor substrate, and a first buried insulating film having a thickness that does not completely fill the groove on the entire surface. Forming a second insulating film having a thickness that completely fills the groove on the entire surface; etching back the entire surface until the surface of the first buried insulating film is exposed; 2. The manufacturing method of a MOS nonvolatile semiconductor memory device according to claim 1, further comprising a step of selectively etching back the first buried insulating film and the first insulating film until the surface of the silicon film is exposed. Method.
導体記憶装置に於いて、特に、半導体基板上にゲート絶
縁膜及び不純物を含有した多結晶シリコン膜を順次形成
する工程と、公知のフォトリソグラフィー技術を用いて
所定の領域の前記多結晶シリコン膜及び前記絶縁膜及び
前記半導体基板の一部を除去して前記半導体基板に溝を
形成する工程と、全面に前記溝が全て埋まらない膜厚の
第1の埋込み絶縁膜を形成する工程と、全面に前記溝を
全て埋める膜厚の第2の絶縁膜を形成する工程と、前記
第1の埋込み絶縁膜の表面が露出する迄全面をエッチバ
ックする工程と、前記多結晶シリコン膜の表面が露出す
る迄前記第1の埋込み絶縁膜を選択的にエッチバックす
る工程と、全面に不純物を含有した第1の多結晶シリコ
ン膜を形成する工程と、全面に平坦化物質を形成して表
面を平坦化した後に、前記第2の埋込み絶縁膜が露出す
る迄全面をエッチバックする工程と、前記平坦化物質を
除去した後に前記第1の多結晶シリコン膜上に第2の絶
縁膜を形成し全面に不純物を含有した第2の多結晶シリ
コン膜を形成する工程とを有する事を特徴とするMOS型
不揮発性半導体記憶装置の製造方法。3. In a MOS nonvolatile semiconductor memory device having a floating gate electrode, in particular, a step of sequentially forming a gate insulating film and a polycrystalline silicon film containing impurities on a semiconductor substrate; Forming a groove in the semiconductor substrate by removing a part of the polycrystalline silicon film and the insulating film and the semiconductor substrate in a predetermined region by using a technique; A step of forming a first buried insulating film, a step of forming a second insulating film having a thickness that completely fills the trenches on the entire surface, and etching back the entire surface until the surface of the first buried insulating film is exposed Performing a step of selectively etching back the first buried insulating film until the surface of the polycrystalline silicon film is exposed; and forming a first polycrystalline silicon film containing impurities on the entire surface. Forming a planarizing material on the entire surface and planarizing the surface, and then etching back the entire surface until the second buried insulating film is exposed; and removing the planarizing material and removing the first polycrystalline material. Forming a second insulating film on the silicon film and forming a second polycrystalline silicon film containing impurities on the entire surface thereof.
含有した多結晶シリコン膜を順次形成した後に、第1の
絶縁膜を形成する工程と、公知のフォトリソグラフィー
技術を用いて所定の領域の前記第1の絶縁膜及び前記多
結晶シリコン膜及び前記絶縁膜及び前記半導体基板の一
部を除去して前記半導体基板に溝を形成する工程と、全
面に前記溝が全て埋まらない膜厚の第1の埋込み絶縁膜
を形成する工程と、全面に溝を全て埋める膜厚の第2の
絶縁膜を形成する工程と、前記第1の埋込み絶縁膜の表
面が露出する迄全面をエッチバックする工程と、前記多
結晶シリコン膜の表面が露出する迄前記第1の埋込み絶
縁膜及び前記第1の絶縁膜を選択的にエッチバックする
工程を有する事を特徴とする第3項記載のMOS型不揮発
性半導体記憶装置の製造方法。4. A step of forming a first insulating film after sequentially forming a gate insulating film and a polycrystalline silicon film containing impurities on a semiconductor substrate, and forming a first insulating film in a predetermined region by using a known photolithography technique. Forming a groove in the semiconductor substrate by removing the first insulating film, the polycrystalline silicon film, the insulating film, and a part of the semiconductor substrate; A step of forming a buried insulating film, a step of forming a second insulating film having a thickness that completely fills the entire groove, and a step of etching back the entire surface until the surface of the first buried insulating film is exposed 4. The MOS nonvolatile semiconductor device according to claim 3, further comprising a step of selectively etching back the first buried insulating film and the first insulating film until the surface of the polycrystalline silicon film is exposed. Semiconductor memory device Production method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2340913A JP2964635B2 (en) | 1990-11-30 | 1990-11-30 | Method for manufacturing semiconductor memory device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2340913A JP2964635B2 (en) | 1990-11-30 | 1990-11-30 | Method for manufacturing semiconductor memory device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH04208572A JPH04208572A (en) | 1992-07-30 |
JP2964635B2 true JP2964635B2 (en) | 1999-10-18 |
Family
ID=18341458
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2340913A Expired - Lifetime JP2964635B2 (en) | 1990-11-30 | 1990-11-30 | Method for manufacturing semiconductor memory device |
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Country | Link |
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JP (1) | JP2964635B2 (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6576949B1 (en) | 1999-08-30 | 2003-06-10 | Advanced Micro Devices, Inc. | Integrated circuit having optimized gate coupling capacitance |
US6682978B1 (en) | 1999-08-30 | 2004-01-27 | Advanced Micro Devices, Inc. | Integrated circuit having increased gate coupling capacitance |
US6232635B1 (en) * | 2000-04-06 | 2001-05-15 | Advanced Micro Devices, Inc. | Method to fabricate a high coupling flash cell with less silicide seam problem |
KR100520681B1 (en) * | 2002-12-23 | 2005-10-11 | 주식회사 하이닉스반도체 | Method for forming floating gate in flash memory device |
-
1990
- 1990-11-30 JP JP2340913A patent/JP2964635B2/en not_active Expired - Lifetime
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JPH04208572A (en) | 1992-07-30 |
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