JP2959896B2 - Write compensation method for information storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a write compensation method for an information storage device for correcting the write timing of write data represented by a 1-7 run length code or a 2-7 run length code, and more particularly to a read compensation method. The present invention relates to a write compensation method for an information recording device that corrects and writes a write timing so that a correct peak timing is obtained by a peak shift in cosine equalization of a signal.

In magnetic recording of write data on a disk medium of a magnetic disk drive, the write data is
-7 run length code (1by7RLL) or 2-7
It is converted to a run length code (2 by 7 RLL). For example, in NRZ recording, bit 1 of the first write data
The write operation is repeated in which the write current is supplied to the head at the rising edge of the bit and the write current is stopped at the rising edge of the next bit 1.

On the other hand, a signal read from a head is subjected to cosine equalization in order to correct a peak shift due to waveform interference, and a signal waveform having a peak synchronized with the magnetic reversal is generated, and then obtained from a disk servo signal. The data bits are detected in synchronization with the data clock, and then decoded by a 1-7 or 2-7 decoder to obtain read data. It is known that a signal waveform obtained by cosine equalization undergoes a peak shift on the time axis due to waveform components located before and after the cosine equalization, so that a result of the peak shift becomes a correct peak timing. It is necessary to perform write compensation to advance or delay the timing of the data bit on the writing side in advance.

In particular, write compensation is desired for 2T patterns affected by this. The currently performed write compensation aims at suppressing a peak shift due to waveform interference, and has no effect of suppressing a peak shift caused by cosine equalization. That is, (4/3) of the 1-7 run-length code
The peak shift occurring at (3/2) T of the T, 2-7 run-length code is completely different from the peak shift occurring at 2T.

[0005]

2. Description of the Related Art FIG. 25 is a block diagram showing an example of a conventional write compensation system. In FIG. 25, reference numeral 10 denotes a write compensation circuit to which a 1-7 code or a 2-7 code based on write data is input. The write data subjected to write compensation by the write compensation circuit 10 is, for example, NRZ
The current signal is converted to a current signal of a system, supplied to the head 16 via the switching circuit 14, and magnetically recorded on a disk medium.

At the time of reading, the switching circuit 14 connects the head 16 to the cosine equalizing circuit 18. The signal read by the head 16 is subjected to cosine equalization for correcting a peak shift due to waveform interference by a cosine equalization circuit 18 and is converted into a signal having a peak portion in a magnetic reversal portion. Cosine equalization circuit 1
8 includes a delay line 20, an attenuator 22, and a differential amplifier 24. The output signal of the cosine equalization circuit 18 is supplied to a data detection circuit 25, which detects a data bit synchronized with a data clock demodulated from a servo signal of the servo head, and finally converts a 1-7 code or a 2-7 code. The decrypted data is read.

FIG. 26 shows a conventional write compensation for the 1-7 code.
When the cycle of the write current determined by the rising interval of the write current is (4/3) T with respect to the data bit cycle T, the cycle of the data bit 1 immediately before and after the rising and falling of the write current is one cycle. (4/3) At times other than T, a compensating write current whose timing has been corrected so as to narrow the front and back is passed.

FIG. 27 shows a conventional write compensation for the 2-7 code.
Is equal to (3/2) T with respect to the data bit cycle T, the cycle of the data bit 1 immediately before and after the rising and falling of the write current is 1/3. (3/2) At times other than T, a compensating write current whose timing has been similarly corrected so as to narrow the front and rear sides is supplied.

The conditions for such write compensation are determined as shown in FIG. 28 for the 1-7 code, and as shown in FIG. 29 for the 2-7 code. For example, looking at the 1-7 code in FIG. 28, by looking at the relationship of the second bit before and after the current bit n, n ± 2, there is no compensation (None) and advance compensation (Early). , And delay compensation (Late) modes A, B, C, and D are determined.

For example, when the current bit n = 1 (1 is a significant bit, 0 is an invalid bit), the mode is set when the bit n−2 after 2 is a significant bit and the bit n + 2 before 2 is an invalid bit. Early compensation of C is selected. FIG.
30 is a timing chart showing write data compensation in modes A to D of the 1-7 code in FIG.

In FIG. 28, in modes A and B, write compensation is not performed, and write data is directly output as compensated write data. In mode C, advance write compensation data for shifting the current bit n forward on the time axis is generated. Further, in the mode D, compensated write data to which delay compensation for shifting the current bit later on the time axis is performed is generated.

By performing writing with write data to which such advance compensation or delay compensation has been performed, FIG.
As shown in FIG. 5, when the cosine equalization circuit 18 applies cosine equalization to the readout signal from the head 16, the peak waveform generated at the magnetic reversal portion is reduced on the time axis by the peak waveforms before and after the cosine equalization. , The result of the peak shift becomes the correct timing, and the correct bit data can be demodulated by the data detector 26.

[0013]

However, in such a conventional write compensation system, when the write current is 2T, which is twice the period of the data bit, the head read signal is subjected to cosine equalization. As a result, a newly generated peak shift could not be suppressed. FIG.
0001001000... When reading the recording result by the write data including the bit period 2T.
3 shows signal waveforms at various parts in the cosine equalization circuit 18 of FIG.

In FIG. 25, an input signal vi receives a delay τ in a delay line 20 and is applied to a non-inverting input terminal of a differential amplifier 24. Since the input impedance of the non-inverting input terminal of the differential amplifier 24 is very high, the input signal vi
Is reflected back to the input terminal via the delay line 20, and a signal v2 synthesized with the input waveform at that time is obtained.

The signal v2 is attenuated K times by the attenuator 22 and supplied to the inverting input terminal of the differential amplifier 24 as a signal v3. The differential amplifier 24 calculates the difference (v
Let 1-v3) be the output signal vo. Input signal vi is 2T
31, the output signal vo of the cosine equalization circuit 18 is such that the previous peak shifts later and the latter peak shifts forward with respect to the original peak waveform shown by the broken line. There has been a problem that a peak shift occurs and a correct peak timing corresponding to the write data cannot be obtained.

The present invention has been made in view of such a conventional problem, and provides a write compensation method for an information storage device in which correct peak timing can be obtained by cosine equalization even for 2T write data. The purpose is to provide.

[0017]

FIG. 1 is a diagram illustrating the principle of the present invention. First, according to the present invention, the write data
6, the write compensating means 10 performs write compensation for advance or delay of the write timing and magnetically records the data on the medium by the head 16, while the read signal read from the medium by the head 16 is cosine or the like. After performing cosine equalization by the conversion means 18, the data bits are reproduced by the data detection means 25,
Finally, the present invention is directed to a write compensation method of a magnetic storage device which outputs decoded data by decoding by a decoding means 30.

The present invention is also directed to a write compensation method for a magnetic storage device using an electric filter which realizes the same waveform processing function instead of the cosine equalizing means 18. In the present invention, as a write compensation method for such a magnetic recording apparatus, the cycle of the write current based on two consecutive significant bits (bit 1) in the encoded write data is a predetermined data bit cycle T. If it is twice (2T),
When the cycle with the preceding and following significant bits is other than 2T, the write timing is corrected by the write compensating means 10 so as to extend the write current generation interval back and forth.

Looking at this at the level of the write data bit, the write compensating means 10 finds that the cycle between the encoded data bit that is currently processed and the immediately preceding data bit is 2T, The period between the encoded data bit currently processed and the next data bit is 2T.
In other cases, the timing of the data bit currently being processed is advanced by a predetermined time.

The write compensating means 10 determines that the cycle of the currently processed encoded data bit and the next data bit is 2T, and that the currently processed encoded data bit is When the cycle of the immediately preceding data bit is other than 2T, the timing of the data bit currently being processed is delayed by a predetermined time. In the case of the NRZ method, the write compensator 10 repeats a write operation in which a write current starts flowing in synchronization with a significant bit that first appears and stops the write current in synchronization with a second significant bit obtained. .

As a specific configuration of the write compensating means 10, a shift register for shifting write data output as serial data from the encoding means 26 at a predetermined period, and a center shift bit n of the shift register are described. The current bit n to be processed is set as the current bit n, and the bits before and after are n ±
1, n ± 2, n ± 3, n ± 4,..., The advanced bit (E) Early, the current bit n is input and advanced by a predetermined timing, the bit (N) Nominal with the timing unchanged, and A timing control circuit for outputting a delay bit (L) Late delayed by a predetermined timing, and inputting shift bits n ± 3, n ± 4... And a timing correction circuit for correcting the bit timing when the period of the preceding and succeeding bits is 2T.

More specifically, the encoding means 26
Is the 1-7 run-length encoding means, the write compensating means 10 performs the following processing in modes A to D. Here, the current bit to be processed is n, and the preceding and succeeding bits are n ±
1, n ± 2 and n ± 3. (A) When both the third and preceding bits (n ± 3) are significant bits, the timing of the current bit (n) is not corrected.

(B) When both the third and preceding bits (n ± 3) are invalid bits, the timing of the current bit (n) is not corrected. (C) The third bit (n + 3) before is a significant bit and the third bit is
When the bit (n-3) is an invalid bit, a correction is made to advance the current bit (n) by a predetermined timing. (D) The previous third bit (n + 3) is an invalid bit and the third
When the bit (n−3) is a significant bit, the current bit (n) is corrected to be delayed by a predetermined timing. When the coding unit 26 is a 2-7 run-length coding unit, the write compensating unit 10 performs the following processing in modes A to D. (A) When both the fourth and preceding bits (n ± 4) are significant bits, the timing of the current bit (n) is not corrected.

(B) When the fourth and preceding bits (n ± 4) are both invalid bits, the timing of the current bit (n) is not corrected. (C) The 4th bit (n + 4) before is significant bit and the 4th bit after
When the bit (n-4) is an invalid bit, a correction is made to advance the current bit (n) by a predetermined timing. (D) The previous fourth bit (n + 4) is an invalid bit and the fourth
When the bit (n−4) is a significant bit, the current bit (n) is corrected to be delayed by a predetermined timing. Further, in the case of 2T, the conventional write compensation according to the present invention is 1-7.
When the write compensation for the code is added, the write compensation unit 10 performs the following modes A to G. (A) When both the preceding and succeeding second bits (n ± 2) are significant bits, the timing of the current bit (n) is not corrected.

(B) When the third and preceding bits (n ± 3) are both significant bits, the timing of the current bit (n) is not corrected. (C) When both the third and preceding bits (n ± 3) are invalid bits, the timing of the current bit (n) is not corrected. (D) The previous second bit (n + 2) is an invalid bit and the second
When the bit (n-2) is a significant bit, a correction is made to advance the current bit (n) by a predetermined timing.

(E) When the previous third bit (n + 3) is a significant bit and the subsequent third bit (n-3) is an invalid bit, correction is made to advance the current bit (n) by a predetermined timing. (F) The second bit (n + 2) before is a significant bit and the second bit is
When the bit (n−2) is an invalid bit, the current bit (n) is corrected to be delayed by a predetermined timing. (G) The previous third bit (n + 3) is an invalid bit and the third
When the bit (n−3) is a significant bit, the current bit (n) is corrected to be delayed by a predetermined timing. Furthermore, the write compensation according to the present invention in the case of 2T is the same as the conventional 2T.
When the write compensation for the −7 code is added, the write compensating means 10 performs the following modes A to G. (A) When both the third and preceding bits (n ± 3) are significant bits, the timing of the current bit (n) is not corrected.

(B) When both the fourth and preceding bits (n ± 4) are significant bits, the timing of the current bit (n) is not corrected. (C) When both the fourth and preceding bits (n ± 4) are invalid bits, the timing of the current bit (n) is not corrected. (D) The previous third bit (n + 3) is an invalid bit and the third
When the bit (n-3) is a significant bit, a correction is made to advance the current bit (n) by a predetermined timing.

(E) When the preceding fourth bit (n + 4) is a significant bit and the subsequent fourth bit (n-4) is an invalid bit, a correction is made to advance the current bit (n) by a predetermined timing. (F) The third bit (n + 3) before is a significant bit and the third bit after
When the bit (n-3) is an invalid bit, the current bit (n) is corrected to be delayed by a predetermined timing. (G) The previous fourth bit (n + 4) is an invalid bit and the fourth
When the bit (n−4) is a significant bit, the current bit (n) is corrected to be delayed by a predetermined timing.

[0029]

According to the write compensation method of the information writing apparatus according to the present invention having such a configuration, when writing 2T write data, the width of the write current is set on the time axis in reverse to the normal write compensation. In the write compensation for 2T, the peak shift caused by the cosine equalization of the read signal causes the peak position to make the peak position the original correct timing of the write data. A signal having a correct peak position with suppressed peak shift due to the above can be reproduced, the demodulation of the peak position data bit of the cosine-equalized signal can be compensated, and the reliability of information storage can be further improved.

[0030]

FIG. 2 is a block diagram showing an embodiment of the present invention. In FIG. 2, reference numeral 26 denotes an encoder. A conversion rule for a 1-7 run-length code or a 2-7 run-length code is set in the encoder 26, and write data is converted to a 1-7 RLL code or a 2-7 RLL code. Convert to

The write data encoded by the encoder 26 is supplied to the write compensation circuit 10. The write compensation circuit 10 performs a write compensation process for correcting a write timing so as to remove a peak shift due to waveform interference in the cosine equalization circuit 18 provided on the reading / reproducing side. In particular, when the data bit period of the write data obtained from the encoder 26 is 2T, the write compensation circuit 10 of the present invention provides two data bits under the condition that the data bit period before and after the data bit is other than 2T. Write compensation is performed so as to extend the period of the write current determined by the rising interval of the current on the time axis. Details of the write compensation circuit 10 according to the present invention will be clarified later.

The write data that has undergone write compensation in the write compensation circuit 10 is supplied to a driver 12, and the driver 12 converts the write data into, for example, a write current according to NRZ and outputs the write current. That is, the driver 12 starts to supply the write current at the first data bit 1 obtained from the write compensation circuit 10, stops the write current at the next data bit 1, and thereafter,
The output of the write current by NRZ is repeated every time data bit 1 is obtained. The output of the driver 12 is provided to the head 16 via the switching circuit 14.

The switching circuit 14 connects the output of the driver 12 to the head 16 during the write operation, and connects the output of the head 16 to the cosine equalization circuit 18 during the read operation.
The head 16 is provided so as to be movable in the disk radial direction by a VCM or the like in the vicinity of a magnetic disk medium rotated by a spindle motor. A seek operation for moving the head to a target track by a known servo mechanism, and after a seek operation is completed. Position control is performed to cause the head to follow the target track.

A read signal from the magnetic disk medium read by the head 16 at the time of reading is supplied to the cosine equalizing circuit 18 via the switching circuit 14. The cosine equalization circuit 18 performs cosine equalization on the input signal Vi in order to suppress a peak shift due to waveform interference of the reproduction signal from the head 16. That is, the cosine equalization circuit 18 includes a delay line 20 having a delay time τ, an attenuator 22, and a differential amplifier 24. The output signal vo of the cosine equalizer is provided to the data detector 25. The data detector 25 reproduces data bits corresponding to the peak portion of the output signal of the cosine equalization circuit 18.

The data detector 25 includes a synchronization signal generator 28
Are reproduced, and data bits synchronized with the data clock output from the synchronization signal generator 28 are reproduced. The synchronization signal generator 28 controls the PLL by using a synchronization signal component included in the read signal from the head 16 to generate a data clock. The data bits reproduced by the data detector 25 are supplied to a decoder 30, which decodes the read data according to the 1-7 code inverse conversion rule for the 1-7 run length code, and 2-7 for the 2-7 code.
The read data is restored according to the reverse conversion rule.

Of course, the encoder 26 and the decoder 30 are provided with a disk controller for transferring data to and from a higher-level device, and control transfer of write data and read data. FIG. 3 is a configuration diagram showing a specific embodiment of the write compensation circuit 10 of FIG. 2 using a 1-7 run-length code as an example.

In FIG. 3, reference numeral 32 denotes a shift register having seven shift stages. A clock and write data serially transferred in synchronization with the clock are input to the shift register 32, and the write data sequentially repeats loading and shifting in seven shift stages. The outputs of the seven shift stages of the shift register 32 are n + 3, n
+2, n + 1, n, n-1, n-2, n-3. Of the seven shift stages, the data bit currently subjected to the write compensation processing is defined as n, the current bit n is one data bit period T1d, and the previous data bit is n.
+1 and 2 before are n + 2, 3 before is n + 3, one data bit period T1d, the next is n−1, and 2 is n-2,
After three, it is set to n-3.

The bit n output from the shift register 32 is output to a timing control circuit 34, and a nominal output N and a bit n which output the timing of the bit n as they are.
Output E which is time-shifted toward bit n-1 on the time axis, that is, early output E whose timing is advanced in time, and late output L which time-shifts bit n toward bit n + 1, that is, bit n Is generated.

The shift amount on the time axis of the early output E and the late output L with respect to the nominal output N maintaining the timing of the bit n is set, for example, to 15% to 20% of the rising period of the data clock. Is optimally adjusted according to the amount of peak shift actually caused by cosine equalization. A timing correction circuit 36 receives the bit outputs n + 3, n-3 of the shift register 32 and the three outputs E, N, L of the timing control circuit 34. The timing correction circuit 36 outputs an early output E and a nominal output N from the timing correction circuit 34 based on a 2-bit pattern of bits n + 3 and n-3 from the shift register 32.
And the late output L are selected and output as compensation write data.

The embodiment 1 shown in FIG.
The rule of the write compensation for the 7 codes is as shown in FIG. As shown in the write compensation of the principle diagram (b) of FIG. 1, the rule of FIG. 5 is that when the cycle of two consecutive data bits 1 of the write data before compensation is 2T, the preceding and succeeding data bits When the period of 1 is other than 2T, compensated write data is generated so that the rise of the two write data is expanded on the time axis, and a period in which the write current flows in time with respect to the write current by the write data before compensation is set. It will expand.

The timing correction circuit 36 shown in FIG. 3 has a specific circuit configuration shown in FIG. FIG. 4 shows a circuit for selecting an early output E, a nominal output N and a late output L according to a 2-bit pattern of bit n-3 and bit n + 3 shown in the write compensation rule of FIG. That is, the timing correction circuit 36 shown in FIG.
AND circuit 38 for selecting the nominal output N at "1", FIG.
Nominal output N with mode B bit pattern "00"
, An AND circuit 44 for selecting the early output E with the mode C bit pattern “01” in FIG. 5, and an AND circuit for selecting the late output L with the mode D bit pattern “10” in FIG. 46 is provided.

AND circuit 3 for selecting the nominal output N
The outputs of 8 and 40 are combined by an OR circuit 42,
The signal is output to the circuit 52. The outputs of the AND circuit 44 for selecting the early output E and the AND circuit 46 for selecting the late output L are supplied to the OR circuit 5 via drivers 48 and 50.
2 is input. The output of the OR circuit 52 outputs compensated write data that has been subjected to final write compensation.

FIG. 6 is a timing chart showing the write compensation operation performed in the embodiment of FIGS. 3 and 4 according to the write compensation rule of FIG. In FIG. 6, in the mode A in which the bits n−3 and n + 3 become 1, the nominal output N
, The timing of the bit n to be processed is not corrected, and is output as it is as compensation write data. This is the same for the mode B in which the bits n−3 and n + 3 are 0.

On the other hand, in the mode C where n + 3 is 1 and n-3 is 0, the bit n is corrected so as to be advanced toward the bit n-1 on the time axis. Further, in the mode D where the bit n-3 is 1 and n + 3 is 0,
On the other hand, the bit n receives a correction shifted to the (n + 1) side on the time axis, that is, a correction delayed in time.

By the write compensation in the modes A to D shown in FIG. 6, for the write data which becomes, for example, "... 0001001000 ...", the period of two data bits 1 is 2T, and the data bits before and after that are 2T. Since the cycle of 1 is not 2T, write compensation according to mode C and mode D is performed, and timing correction is performed so as to extend the rising timing of two data bits 1 back and forth on the time axis.

FIG. 7 is an explanatory diagram showing signal waveforms at various parts when 2T write current is read and cosine-equalized after write compensation in accordance with the present invention. In FIG.
The write current (a) is shown with reference to the write current generated by the data bits before performing the write compensation according to the present invention. By the write compensation of the present invention with respect to the write current of FIG. 7A, a compensated write current having a timing extended on the time axis as shown in FIG. 7B is obtained.
This compensation write current is passed to the head 16 to perform recording on the magnetic disk medium.

The read signal from the magnetic disk medium written with the compensation write current shown in FIG. 7B is input to the cosine equalization circuit 18 shown in FIG. The input signal v1 shown is applied to the non-inverting input terminal of the differential amplifier 24. On the other hand, with respect to the inverting input terminal of the differential amplifier 24, the input signal v1 of the non-inverting input terminal is reflected by the high impedance and returns to the delay line 20 in the reverse direction. And the signal v2 is multiplied by K (where K
<1) A signal v3 is obtained as a signal obtained by
Is as shown in FIG.

Finally, the output signal vo from the differential amplifier 24 is vo = v1 from the two input signals v1 and v3.
The signal shown in FIG. 7E is obtained as −v3, and the peak position of the output signal vo is determined by the compensating write current shown in FIG. 7B by the rise and fall of the write current before compensation in FIG. The waveform is equalized to a state having the correct original peak position that matches.

FIG. 8 is a block diagram showing a specific embodiment of the write compensation circuit 10 when the 2-7 run length code is applied to the embodiment of FIG. 8, reference numeral 54 denotes a shift register, which is a total of nine shift registers obtained by adding one shift stage before and after to the shift register 32 of FIG. 3, and the output of the shift register is newly added to a bit n + 4 and a bit n. -4 is added.

The timing control circuit 34 is the same as that in FIG. 3, and generates an early output E, a nominal output N, and a late output L for the bit n to be processed at present. The timing correction circuit 56 has a circuit configuration shown in FIG. The circuit configuration of FIG. 9 is determined according to the 2-7 run-length code write compensation rule shown in FIG. The write compensation rule of the 2-7 run-length code in FIG.
4, any one of the early output E, the nominal output N and the late output L is selected.

Mode A of bits n-4 and n + 4 in FIG.
The bit patterns in D.about.D are the same as those in the case of the write compensation rule of the 1-7 run-length code shown in FIG. 5, and therefore, the logic circuit in FIG. 9 has the same circuit configuration as that in FIG. The difference is that the bit inputs to the circuits 58, 60, 64, 66 are bits n + 4, n-4. Of course, the OR circuits 62, 72 and the drivers 68, 7
0 is the same as in FIG.

FIG. 11 shows the write compensation rule according to the present invention when the data bit shown in FIG. 5 is 2T for the 1-7 run length code and the data bit period shown in FIG. 28 is (4/3) T. FIG. 11 is a configuration diagram of an embodiment in a case where the write compensation rule at the time of (1) is combined. 11, the shift register 32 and the timing correction circuit 34 are the same as those in the embodiment of FIG.

The timing correction circuit 74 has a circuit configuration shown in FIG. The circuit configuration of FIG. 12 is configured according to the write compensation rule of 1-7 run-length code shown in FIG. The write compensation rule for the 1-7 run length code of FIG. 13 has seven modes A to G, and uses the 4-bit pattern of bit n ± 2 and bit n ± 3 to output the nominal output N, Early output E and late output L
Is selected. That is, AND circuits 76 and 7
In each of 8, 80, a two-bit pattern in any one of modes A, B, and C in FIG. 13 is determined, a nominal output N is selected, and output through OR circuits 82 and 96.

Further, the AND circuits 84 and 86 discriminate a 2-bit pattern of any of the modes D and E shown in FIG. 13 to select the early output E and output it through the OR circuits 88 and 96. Further, the AND circuits 90 and 92 discriminate a 2-bit pattern in any of the modes F and G shown in FIG. 13 to select the late output L and output it through the OR circuits 94 and 96.

FIG. 14 shows the selection of the nominal output N in the modes A to C in the write compensation rule of FIG. 13. In this case, the bit n to be processed for the write data is output as it is as the compensation write data. Is done. FIG.
5 is a timing chart showing write compensation of modes D and E in the write compensation rule of FIG. 13, in which the bit n to be processed has been advanced to the timing shifted to the (n-1) side on the time axis. It is output as compensation write data.

FIG. 16 is a timing chart for the modes F and G in the write compensation rule of FIG.
In this case, the bit n is output as compensated write data with a timing delay shifted on the time axis to the bit n + 1 side. FIG. 17 shows the write compensation rule according to the present invention when the data bit is 2T in the 2-7 run length code shown in FIG. 10 and the data bit period (3 /
2) It is a configuration diagram of an embodiment of a write compensation circuit in which a write compensation rule at T is combined.

In FIG. 17, the shift register 54 is the same as in FIG. 8, and the timing control circuit 34 is also the same as in FIG. The timing correction circuit 98 has a circuit configuration shown in FIG. The circuit configuration of FIG. 18 is configured in accordance with modes A to G showing the contents of compensation for bits n, n ± 1, n ± 2, n ± 3, and n ± 4 shown in FIG. In other words, FIG. 18 shows four bits determined by bits n ± 3 and n ± 4 in FIG.
Nominal output N, early output E according to bit pattern
And the late output L.

That is, in FIG. 18, the AND circuit 100,
Reference numerals 102 and 104 select the nominal outputs of the modes A, B and C in FIG. The AND circuits 108 and 110 select the early output E according to the modes D and E in FIG. AN
D circuits 114 and 116 output late output L in accordance with modes F and G of FIG. These outputs are supplied to the OR circuit 10
6, 112, 118 and 120 to output as compensation write data.

FIG. 20 is a configuration diagram showing another embodiment of the present invention. The embodiment of FIG. 20 is characterized in that an electric filter 122 is used instead of the cosine equalization circuit 18 of the embodiment of FIG. The configuration other than the electric filter 122 is the same as that of the embodiment of FIG. FIG. 21 shows the electric filter 122 of FIG.
FIG. 3 is a configuration diagram of an embodiment of FIG.

In FIG. 21, an electric filter 122 is a second-order low-pass filter (second-order LPF) 12.
4, a second-order high-pass filter (second-order HPF) 126, an attenuator 128, an adder 130, and a second-order low-pass filter 13
2,134 and primary low-pass filter (primary LPF) 1
36. That is, a combination of one HPF of the second order and four LPFs of the seventh order in total.

Here, the transfer function of each filter is as follows. Secondary LPF 124 = a ₀ / (S ² + a ₁ S + a ₀ ) Secondary HPF 126 = S ² / (S ² + a ₁ S + a ₀ ) Secondary LPF 132 = b ₀ / (S ² + b ₁ S + a ₀ ) Secondary LPF 134 = c ₀ / (S ² + c ₁ S + a ₀ ) Primary LPF 136 = d ₀ / (S + d ₀ ) where S = jΩ = jω / ω _c Therefore, the transfer function A of the electric filter 122
A = V _OUT / V _IN = {a ₀ b ₀ c ₀ d ₀ (1-GS)} / ｛(S ² + a ₁ S + a ₀ ) (S ² + b ₁ S + a ₀ ) (S ² + c ₁ S + a ₀₎ ) (S + d ₀ )｝, and has a high-frequency emphasized frequency characteristic as in the case of the cosine equalization circuit 18 in FIG. 2, thereby enabling pulse slimming and suppressing a peak shift due to waveform interference.

The electric filter 122 has the following advantages over the cosine equalization circuit. Does not require a delay line. Signal processing up to read data can be performed by a differential circuit. When performing optimal equalization with a cosine equalization circuit, a plurality of delay lines are required, but optimal equalization can be performed with one electric filter.

FIG. 22 shows an example of specific characteristics of the electric filter 122 used in the present invention, in comparison with characteristics of a cosine equalization circuit. In FIG. 22, the characteristic A is due to the cosine equalization circuit, and the delay time DL = 25 nS,
Attenuation rate K = 0.6, cutoff frequency Fc = 18.0M
Hz. The characteristic B is due to the electric filter 122 and has a cutoff frequency Fc
= 11.09 MHz and Boost = 10.75 dB. Incidentally, the characteristic B when Boost = 0 dB
₀ is shown for reference.

Here, the definition of Boost that determines the high-frequency emphasis characteristic of the electric filter 122 is, as shown in FIG. 23, a point a of the cutoff frequency fc where the gain is reduced by 3 dB in the characteristic B ₀ when Boost = 0 dB. This shows how much the gain at point b of the characteristic B has increased. FIG. 24 shows an example of another specific characteristic of the electric filter 122 used in the present invention in comparison with the characteristic of the cosine equalization circuit 18.

In FIG. 24, the characteristic A is based on a cosine equalization circuit, and has a delay time DL = 40 ns and an attenuation factor K =
0.4 and the cutoff frequency Fc = 12.6 MHz. The characteristic B is the electric filter 12
2, and the cut-off frequency Fc = 7.45
MHz, Boost = 7.45 dB.

As is clear from FIGS. 22 and 24, the high-frequency emphasis characteristic equivalent to that of the waveform equalizing circuit is obtained by the electric filter 122, and the write compensation circuit 20 of FIG. On the other hand, by applying the write compensation shown in FIGS. 3 to 19 as in the case of the embodiment of FIG. 2, even in the case of the data bit period 2T, the peak shift generated in the electric filter can be suppressed. In the above embodiment, the 1-7 run-length code and the 2-7 run-length code are taken as examples, but the present invention is not limited to this, and the present invention can be applied to any appropriate run-length code. it can.

[0067]

As described above, according to the present invention, even when the data bit period is 2T, the peak shift generated in the cosine equalization circuit or the electric filter introduced to suppress the peak shift due to the waveform interference is suppressed. Since the correction can be performed, the peak shift can be completely suppressed for the entire data bit period, and the reliability of data demodulation can be greatly improved.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a configuration diagram of an embodiment of the present invention.

FIG. 3 is a diagram showing an embodiment of the write compensation circuit of FIG. 2 for 1-7 run-length codes;

FIG. 4 is a configuration diagram of an embodiment of the timing correction circuit of FIG. 3;

FIG. 5 is an explanatory diagram of a write compensation rule applied to FIG. 3;

6 is a timing chart of write compensation in modes A to D according to the write compensation rule of FIG.

FIG. 7 is a signal waveform diagram of cosine equalization when reading written contents by write compensation of FIGS. 3 and 4;

8 is a configuration diagram of an embodiment of the write compensation circuit of FIG. 2 for 2-7 run-length codes;

9 is a configuration diagram of an embodiment of the timing correction circuit of FIG. 8;

FIG. 10 is an explanatory diagram of a write compensation rule applied to FIG. 9;

FIG. 11 is a configuration diagram of an embodiment of a write compensation circuit that combines the write compensation of the present invention and the conventional write compensation for 1-7 run-length codes.

FIG. 12 is a configuration diagram of an embodiment of the timing correction circuit of FIG. 11;

FIG. 13 is an explanatory diagram of a write compensation rule applied to FIG. 11;

14 is a timing chart showing write compensation (no compensation) in modes A to C in FIG. 13;

FIG. 15 shows write compensation of mode D and E in FIG.
Timing chart showing

16 is a timing chart showing write compensation (delay) of modes F and G in FIG. 13;

FIG. 17 is a configuration diagram of an embodiment of a write compensation circuit that combines the write compensation of the present invention and the conventional write compensation for a 2-7 run-length code.

18 is a configuration diagram of an embodiment of the timing correction circuit of FIG. 17;

19 is an explanatory diagram of a write compensation rule applied to FIG.

FIG. 20 is a configuration diagram showing another embodiment of the present invention.

21 is a configuration diagram of an embodiment of the electric filter of FIG. 20;

FIG. 22 is a characteristic diagram showing a frequency characteristic of an electric filter used in the present invention in comparison with a cosine equalization circuit;

FIG. 23 is an explanatory diagram of Boost in the characteristics of FIG. 22.

FIG. 24 is a characteristic diagram showing another frequency characteristic of the electric filter used in the present invention in comparison with a cosine equalization circuit;

FIG. 25 is a block diagram of a conventional write compensation method.

FIG. 26 is a timing chart showing conventional 1-7 run-length code write compensation.

FIG. 27 is a timing chart showing write compensation of a conventional 2-7 run-length code.

FIG. 28 is an explanatory diagram showing a write compensation rule at a data bit period (4/3) T in a conventional 1-7 run-length code.

FIG. 29 is an explanatory diagram showing a write compensation rule at a data bit period (3/2) T in a conventional 2-7 run-length code.

30 is a timing chart of the conventional write compensation in accordance with the write compensation rule modes A to D of FIG. 23;

FIG. 31 is a signal waveform diagram showing signal waveforms of various parts of cosine equalization in reading out a signal written in a conventional 1-7 run-length code bit period 2T.

[Explanation of symbols]

10: Write compensation means (write compensation circuit) 12: Driver 14: Switching circuit 16: Head 18: Cosine equalization means (Cosine equalization circuit) 20: Delay line 22: Attenuator 24: Differential amplifier 25: Data Detecting means 26: Encoding means (encoder) 28: Synchronous signal generator 30: Decoding means (decoder) 32, 54: Shift register 34: Timing control circuit 36, 56, 74, 98: Timing correction circuit 38, 40 , 44,46,58,60,64,66,7
6,78,80,84,86,90,92,100,1
02, 104, 108, 110, 114, 116: AND circuit 48, 50, 68, 70: Buffer (driver) 42, 52, 62, 72, 82, 88, 94, 96, 1
06, 112, 118, 120: OR circuit 122: Electric filter 124, 132, 134: Secondary low-pass filter (secondary LPF) 126: Secondary high-pass filter (secondary HPF) 128: Attenuator 130: Adder 136: Primary low-pass filter (Primary LPF)

Claims (10)

(57) [Claims] The write data is encoded by an encoding means (26), and write advance or delay of write timing is compensated by a write compensation means (10), and magnetic recording is performed on a medium by a head (16). On the other hand, a read signal read from the medium by the head (16) is subjected to cosine equalization by cosine equalization means (18), and then data bits are reproduced by data detection means (25).
Finally, in the information storage device which decodes and outputs read data by the decoding means (30), the cycle of the write current based on two consecutive significant bits in the encoded write data is a predetermined data bit cycle. When the period with the significant bits before and after is twice as large as (T), the write timing is corrected by the write compensating means (10) so as to extend the write current generation interval back and forth. A write compensation method for an information storage device, characterized in that: The write data is encoded by an encoding means (26), and write compensation of the write timing is performed by a write compensating means (10), and write compensation of a write timing is performed, and magnetic recording is performed on a medium by a head (16). On the other hand, after the read signal read from the medium by the head (16) is equalized by the electric filter (122), the data bits are reproduced by the data detecting means (25), and finally the decoding means (30) In the information storage device for decoding and outputting read data, the cycle of the write current based on two consecutive significant bits in the encoded write data is twice the predetermined data bit cycle (T). In this case, when the period between the preceding and succeeding significant bits is other than 2T, the write timing is corrected by the write compensating means (10) so as to extend the write current generation interval back and forth. Book of Compensation method. 3. The write compensation method for an information storage device according to claim 1, wherein said write compensation means (10) has already processed the coded data bits to be processed. The cycle with the immediately preceding data bit is twice as long as the predetermined data bit cycle (T), and the cycle of the data bit immediately after the currently processed encoded data bit is other than 2T. A write compensation method for an information storage device, wherein the timing of a data bit currently being processed is advanced by a predetermined time. 4. A write compensation method for an information storage device according to claim 1, wherein said write compensation means (10) is configured to store the encoded data bit currently processed and 1 When the period of the next data bit is twice as long as the predetermined data bit period (T), and the period of the data bit immediately before the currently processed encoded data bit is other than 2T. Wherein the timing of a data bit currently being processed is delayed by a predetermined time. 5. The write compensation method for an information storage device according to claim 3, wherein said write compensation means starts to supply a write current in synchronization with the first significant bit. A write compensation method for an information storage device, characterized by repeating a write operation for stopping a write current in synchronization with a significant bit obtained next. 6. A write compensation method for an information storage device according to claim 1, wherein said write compensation means (10) comprises: write data output as serial data from said encoding means (26). And a shift register that shifts the center shift bit of the shift register by a predetermined period. The current bit to be processed is (n), and the preceding and succeeding bits are (n ± 1, n
± 2, n ± 3, n ± 4,...), The advanced bit (E) Early inputting the current bit (n) and advancing the predetermined timing, the bit (N) Nominal with the timing unchanged, and A timing control circuit that outputs a delay bit (L) Late delayed by a predetermined timing; and a shift bit (n ± 3, n ± 4...) That is at least two cycles apart from the current bit (n) of the shift register. And a timing correction circuit for correcting the bit timing when the cycle of the current bit (n) and the preceding and succeeding bits is 2T. 7. A write compensation system for an information storage device according to claim 1, wherein said encoding means (26) is 1-7 run length encoding means, and said write compensation means (10 ) Indicates that the current bit to be processed is (n) and the preceding and succeeding bits are n ± 1, n ± 2, and n ± 3.
When (A) the 3rd bit (n ± 3) before and after are both significant bits, the timing of the current bit (n) is not corrected, and (B) the 3rd bit (n ± 3) before and after In the case of an invalid bit, the timing of the current bit (n) is not corrected. (C) The third bit (n + 3) before is a significant bit and the third bit (n + 3) is
When the bit (n−3) is an invalid bit, a correction is made to advance the current bit (n) by a predetermined timing. (D) The third bit (n + 3) before is invalid and the third bit (n + 3) is an invalid bit.
When the bit (n-3) is a significant bit, a correction for delaying the current bit (n) by a predetermined timing is performed. 8. A write compensation system for an information storage device according to claim 1, wherein said encoding means is a 2-7 run length encoding means, ) Indicates that the current bit to be processed is (n) and the preceding and succeeding bits are n ± 1, n ± 2, n ±
3, n ± 4, (A) when the 4th bit (n ± 4) before and after are both significant bits, the timing of the current bit (n) is not corrected, and (B) the 4th bit (n) before and after When both ± 4) are invalid bits, the timing of the current bit (n) is not corrected, and (C) the fourth bit (n + 4) before is a significant bit and 4
When the bit (n−4) is an invalid bit, a correction is made to advance the current bit (n) by a predetermined timing, and (D) the fourth bit (n + 4) before is an invalid bit and the fourth bit (n + 4) is an invalid bit.
When the bit (n-4) is a significant bit, the current bit (n) is corrected to be delayed by a predetermined timing. 9. A write compensation system for an information storage device according to claim 1, wherein said encoding means is a 1-7 run length encoding means, ) Indicates that the current bit to be processed is (n) and the preceding and succeeding bits are n ± 1, n ± 2, and n ± 3.
When (A) the second and preceding bits (n ± 2) are both significant bits, the timing of the current bit (n) is not corrected, and (B) the third and subsequent bits (n ± 3) are both When the bit is significant, the timing of the current bit (n) is not corrected. (C) When both the third and preceding bits (n ± 3) are invalid bits, the timing of the current bit (n) is not corrected. (D) The second previous bit (n + 2) is an invalid bit and the second
When the bit (n−2) is a significant bit, a correction is made to advance the current bit (n) by a predetermined timing, and (E) the third bit (n + 3) before is a significant bit and 3
When the bit (n−3) is an invalid bit, a correction is made to advance the current bit (n) by a predetermined timing, and (F) the second bit (n + 2) before is a significant bit and the second bit (n + 2) is significant.
When the bit (n−2) is an invalid bit, the current bit (n) is corrected to be delayed by a predetermined timing, and (G) the third bit (n + 3) before is invalid and the third bit (n + 3) is an invalid bit.
When the bit (n-3) is a significant bit, the current bit (n) is corrected by delaying it by a predetermined timing. 10. The write compensation method for an information storage device according to claim 1, wherein said encoding means (26) is 2-7 run length encoding means, and said write compensation means (10). ) Indicates that the current bit to be processed is (n) and the preceding and succeeding bits are n ± 1, n ± 2, n ±
When (A) and the third bit (n ± 3) before and after (A) are both significant bits, the timing of the current bit (n) is not corrected, and (B) the fourth bit (n ±) before and after When both 4) are significant bits, the timing of the current bit (n) is not corrected. When the 4th bit (n ± 4) before and after (C) are both invalid bits, the timing of the current bit (n) is not corrected. (D) The third bit (n + 3) before is invalid and the third bit (n + 3)
When the bit (n−3) is a significant bit, a correction is made to advance the current bit (n) by a predetermined timing, and (E) the fourth bit (n + 4) before is a significant bit and the fourth bit (n + 4) after
When the bit (n−4) is an invalid bit, a correction is made to advance the current bit (n) by a predetermined timing, and (F) the third bit (n + 3) before is a significant bit and the third bit (n + 3) is
When the bit (n−3) is an invalid bit, the current bit (n) is corrected to be delayed by a predetermined timing, and (G) the fourth bit (n + 4) before is an invalid bit and the fourth bit (n + 4) is an invalid bit.
When the bit (n-4) is a significant bit, the current bit (n) is corrected to be delayed by a predetermined timing.