JP2958970B2 - Image transmission apparatus and image transmission method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a still image transmitting apparatus that blocks a still image signal and transmits the signal.

[Summary of the Invention]

According to the present invention, a still image signal stored in a frame memory is divided by a microcomputer into block signals composed of a predetermined number of pixel signals, and the divided block signals are output for each block signal. The orthogonal transform is performed by the processing circuit, the orthogonally transformed block signal is compression-encoded, and the compression-encoded block signal is transmitted and controlled by the microcomputer. This reduces the load on the microcomputer for signal processing for orthogonal transformation and compression encoding, and increases the speed of the signal processing.

[Conventional technology]

Hereinafter, a conventional still image transmission device will be described with reference to FIG. (1) is a microcomputer, CP
U (central processing unit) (2), ROM (3) and RAM (4). (5) is a bus (consisting of a data bus, an address bus, a control bus, etc.) of the CPU (2). The microcomputer (1) controls each unit of the still image transmission device. (13) is a transmission line, which can be wireless or wired. In the case of a wired transmission line, ISDN (Integrated Services Digital Network), high-speed digital line, analog telephone line, DDX (Digital Data Exchange network (this includes DDXC,
DDXP) and dedicated lines.

(12) a communication processing circuit connected between the transmission line (13) and the bus (5) for performing signal processing according to the protocol and transmission speed of the still image signal of the transmission line (13); In the interface, the communication processing means transmission processing and reception processing such as encoding and modulation for transmission and decoding and demodulation for reception, respectively.

(6) is a frame memory (video memory) whose digital video signal input / output terminal and control signal input terminal are connected to the bus (5), and whose digital video signal input terminal is
The digital video signal output terminal is connected to the input terminal of the D / A converter (7) while the other control signal input terminal is connected to the output terminal of the A / D converter (10). Connected to output terminal of circuit (11). And
The writing and reading of the video memory (6) are controlled by the microcomputer (1). The video memory (6) includes a horizontal and vertical address counter, a memory controller, and the like.

(9) is an input terminal for an analog video signal. A video signal (video signal from a video camera, a VTR, etc.) from this input terminal (9) is supplied to an A / D converter (10) and converted into a digital video signal. After the conversion, it is supplied to the video memory (6) and written.

(14) is a communication memory, that is, a buffer memory for transmission and reception. The writing and reading of the communication memory (14) are also controlled by the microcomputer (1). The communication memory (14) includes horizontal and vertical address counters and the like.

(15) is a digital signal processing circuit (DSP) capable of high-speed signal processing, and has an external RAM (16) and an internal RAM (17)
Which is also controlled by the microcomputer (1).

The analog video signal supplied to the input terminal (9) is
After being supplied to a D converter (10) and converted into a digital video signal, it is supplied to a video memory (6) and written as still image data. The still image signal stored in the video memory (6) is subjected to block coding, that is, orthogonal transform such as discrete cosine transform and subsequent compression by the microcomputer (1) and the digital signal processing circuit (15). Encoding, that is, tunable encoding such as Huffman encoding), and after writing to and reading from the communication memory (14), is supplied to the communication processing circuit and the interface (12) and is subjected to transmission processing.
The data is transmitted to another still image transmitting device via the transmission line (13).

The transmission signal supplied from another still image transmission device to the communication processing circuit and the interface (12) through the transmission line (13) is received and processed here, and the obtained orthogonal transform and compression encoding are performed. The digital video signal is written into the communication memory (14), where the microcomputer (1) and the digital signal processing circuit (15) perform block decoding, that is, decompression decoding and subsequent orthogonal transformation. Thereafter, the obtained block signals are written into the video memory (6) to form a still image signal. And
The digital video signal read from the video memory (6) is supplied to a D / A converter (7), converted into an analog video signal, and then supplied to a monitor receiver (8) having a cathode ray tube. Then, the image is projected as a still image on the surface of the cathode ray tube.

Next, referring to FIG. 6, the IEEE TRANSACTIONS ON COM
MUNICATION (IEE Transaction on Communication), VOL.COM-32, NO.3, MA
A case will be described in which the encoding by the adaptive discrete cosine transform (ADCT) disclosed in P.225 to P.232 of RCH 1984 is applied to the still image transmission apparatus shown in FIG.

As shown in FIG. 6A, a video memory (a digital video signal for one frame stored in the frame memory (6) (here, the video signal is a monochrome video signal for simplicity of description), 768 rows Create a 480-column matrix76
As shown in FIG. 6B, a block signal composed of 8 × 8 adjacent pixel signals forming an 8 × 8 matrix as shown in FIG. 6B by the microcomputer (1) using 8 × 480 8-bit pixel signals. And read it out for each block signal, and read the external RAM of the digital signal processing circuit (15).
Write to (16).

Then, each block signal written in the external RAM (16) is converted by the digital signal processing circuit (15).
Performs two-dimensional discrete cosine transform (two-dimensional DCT). A generalized version of this is shown below by mathematical expressions.

j, k (where j, k is j, k = 0,1,2,3, ..., N-
The two-dimensional discrete cosine transform F (u, v) of the sequence f (j, k) of 1) is expressed by the following equation.

Thus, the 8 × 8 pixel signals forming the matrix of 8 rows and 8 columns stored in the external RAM (16) form the matrix of 8 rows and 8 columns obtained by two-dimensional discrete cosine transform. 8
As shown in FIG. 6C, a × 8 coefficient signal (each rounded to, for example, 12 bits) has a DC coefficient (DC) (an average value of 8 × 8 pixel signals) in the upper left corner. As the signal arrives and moves away from it in the horizontal and vertical directions, a low to high frequency coefficient signal will be distributed.

And, by the microcomputer (1),
The coefficients of the 8 × 8 coefficient signals forming the matrix of 8 rows and 8 columns stored in the RAM (16) correspond to the quantization divisors forming the quantization matrix of 8 rows and 8 columns selected in advance. Quantization is performed by dividing the quotient, and the quotient is rounded so as to be represented by 8 bits. The 8 × 8 quantized coefficient signals forming the matrix of 8 rows and 8 columns obtained by this are converted to the sixth
As shown in FIG. D, as the distance from the quantized DC coefficient signal (DC) at the upper left corner increases, coefficient signals having a coefficient of 0 appear frequently, and when there are many coefficients, the coefficient signal becomes 2/3 of the total quantized coefficient signal. Also reach.

Then, the microcomputer (1) removes (or may include) the DC coefficient signal at the upper left corner of the 8 × 8 quantized coefficient signals shown in FIG. 6D and zigzags as shown in FIG. 6E. After the scanning, the compression code is enabled, and the result is written into the communication memory (14) in FIG.

The AIDC of the digital video signal encoded by ADCT
Although a detailed description of T (adaptive / inverse discrete cosine transform) is omitted, in brief, a digital video signal encoded by the ADCT stored in the communication memory (14) is converted to a microcomputer ( According to 1), it is decompressed and decoded, and it is subjected to inverse zigzag scanning, and
It is inversely quantized, two-dimensional inverse cosine transformed by a digital signal processing circuit (15) to obtain a block signal, and the block signal is converted to a microcomputer (1).
Thus, a still image signal is formed by writing to the video memory (6) and repeating this.

[Problems to be solved by the invention]

In such a conventional still image transmission device, a microcomputer divides a still image signal stored in a frame memory into block signals and outputs each block signal, and a digital signal processing circuit converts the block signal into orthogonal signals. After the conversion, the microcomputer compresses and encodes the orthogonally transformed signal, and then transmits the signal. Therefore, the load on the microcomputer for signal processing for orthogonal transformation and compression encoding of each still image signal block signal is heavy. At the same time, the signal processing speed is reduced.

In view of the above, the present invention provides an image transmission apparatus and an image transmission method that transmit image data after performing orthogonal transformation and compression encoding using a microcomputer and a digital signal processing circuit. The load on the microcomputer for signal processing for orthogonal transform and compression encoding for each signal is reduced,
It is intended to propose one that increases the speed of the signal processing.

[Means for solving the problem]

An image transmission apparatus according to a first aspect of the present invention includes an image memory that stores at least one frame of image data, and divides the image data stored in the image memory into blocks each including a predetermined number of pixel data. And a storage area for storing quantization parameters and coding parameters.The pixel data supplied from the microcomputer is orthogonally transformed in block units, and the transformed pixel data is quantized. A digital signal processing circuit that performs quantization based on the parameter and performs coding based on the coding parameter, wherein the microcomputer is used for the quantization parameter used for quantization of the digital signal processing circuit and for coding. Set the encoding parameters and obtain by the digital signal processing circuit. The compressed data is obtained so as to sending control.

In the image transmission method according to the second aspect of the present invention, the image data stored in the image memory storing at least one frame of image data is divided into blocks each including a predetermined number of pixel data by a microcomputer, and the pixel data is divided into blocks. The microcomputer sets a quantization parameter used for quantization and a coding parameter used for encoding of a digital signal processing circuit having a storage area for outputting and storing a parameter for quantization and a parameter for encoding. The pixel data supplied from the microcomputer is orthogonally transformed in block units by a digital signal processing circuit, and the digital signal processing circuit
The orthogonally transformed pixel data is quantized based on the quantization parameter, the quantized quantized data is encoded by the digital signal processing circuit based on the encoding parameter, and the compression obtained by the digital signal processing circuit is performed. The transmission of the encoded data is controlled by the microcomputer.

[Action]

According to the first aspect of the present invention, the microcomputer divides the image data stored in the image memory that stores at least one frame of image data into blocks each including a predetermined number of pixel data, and outputs pixel data for each block. The pixel signal supplied from the microcomputer is orthogonally transformed in block units by a digital signal processing circuit having a storage area for storing the quantization parameter and the encoding parameter, and the transformed pixel data is converted into the quantization parameter. Quantization is performed based on the parameters for coding, and the microcomputer sets quantization parameters used for quantization of the digital signal processing circuit and coding parameters used for coding, and sets Compressed encoded data obtained by the signal processing circuit It sends control.

According to the second aspect of the present invention, the microcomputer divides the image data stored in the image memory storing the image data of at least one frame into blocks each having a predetermined number of pixel data, and outputs the pixel data for each block. . A microcomputer sets quantization parameters used for quantization and coding parameters used for encoding in a digital signal processing circuit including a storage area for storing quantization parameters and encoding parameters. Pixel data supplied from the microcomputer is orthogonally transformed in block units by a digital signal processing circuit. The orthogonally transformed pixel data is quantized by the digital signal processing circuit based on the quantization parameter. The quantized data is encoded by the digital signal processing circuit based on the encoding parameters. The microcomputer controls the transmission of the compressed and coded data obtained by the digital signal processing circuit.

〔Example〕

Hereinafter, an embodiment of a still image transmission device according to the present invention will be described with reference to the drawings, but the overall configuration is the same as that of the conventional still image transmission device described with reference to FIG. Omitted.

The above-mentioned communication memory (14) is used for transmission and reception.
Since this is a memory for temporarily storing a header signal for each frame of a digital luminance signal and two digital chrominance signals, which will be described later, and a subsequent compression-encoded signal, the minimum value of the capacity depends on the communication speed. When the communication speed is low as in the communication using a normal telephone line, the capacity may be much smaller than one frame of the digital video signal. Further, it is a matter of course that the capacity of the communication memory (14) may be increased to, for example, one to several frames to store a large amount of digital video signals.

Next, encoding (compression) by the ADCT by the microcomputer (1) and the digital signal processing circuit (15) and AI
The decoding (expansion) by DCT will be described mainly with reference to FIG.

The microcomputer (1) [its CPU (2)]
At the beginning of each of the encoding process and the decoding process of the digital signal processing circuit (15), the digital signal processing circuit (15) is reset so that the external memory (16) of the digital signal processing circuit (15) is used for encoding and The decoding memory bank is loaded with encoding and decoding programs, quantization matrix for encoding and decoding, Huffman code table, zigzag scanning pointer data, and the like, respectively.

Also, under the control of the microcomputer (1), a digital luminance signal for one frame (each consisting of 768 × 480 pixel signals of 8 bits) stored in the video memory (6) and a digital luminance signal for one frame A red difference signal (each consisting of 384 × 480 pixel signals of 8 bits) and a digital blue difference signal of one frame (each of 384 × 384 pixel signals)
× 480 pixel signals), for each of the digital luminance signal, digital red difference signal and digital blue difference signal,
When divided into block signals and output for each block signal and written to the external RAM (15),
The digital signal processing circuit (15) is also used at the time of data exchange between the quantization matrix for encoding and decoding, the Huffman code table, and the zigzag scanning pointer on the way, and at the end of encoding and decoding for each block signal. ) Is reset.

First, encoding by ADCT will be mainly described with reference to FIG. Here, the encoding of the luminance signal will be described, and the description of the individual encoding of the two types of chrominance signals will be the same as that described above, so the description thereof will be omitted.

As shown in FIG. 2, the microcomputer (1) [its CPU (2)] generates a header signal indicating the number of blocks of a frame, the type of a luminance signal, the type of a color difference signal (or a color signal), and performs communication in advance. And write it to the digital memory (6) and transmit it to the digital signal processing circuit (15).
As shown in FIG. 1, a word pointer memory unit WP and a bit pointer memory unit BP provided in an encoding memory bank (hereinafter the same) of an internal memory (17) of a digital signal processing circuit (15) have The bit length of the header signal is determined by the number of words (word pointer) and the number of bits (bit pointer).
In addition to writing what is expressed in as an initial value,
Then, as shown in FIG. 2, the digital signal processing circuit (1
Each time an encoded signal is obtained in 5), the contents of the memory units WP and BP are added to each integrated value up to the previous time, and the memory units WP and BP are updated with the integrated value (word pointer). To The relationship between the word and the bit in this case is the relationship between the word and the bit of the pixel signal described later, that is, 1 word =
Irrespective of 8 bits, for example, 1 word = 16 bits may be used, but here, for simplicity, 1 word = 8 bits is set. In this case, the number of words changes to word 0, word 1, word 2,...
It changes to 2, ..., 7.

Then, as described later, the digital signal processing circuit (1
According to 5), the coded signal obtained by the two-dimensional discrete cosine transform or Huffman coding of the block signal is controlled by the microcomputer (1) so that the communication memory (14) can be successively connected to the header signal. Is written to.

In this case, the number of words (word pointer) of the bit length of the header signal stored in the memory unit WP and the bit BP, respectively.
And the number of bits (bit pointer) are stored, so that if they are, for example, word 5 and bit 3, they represent the number of words (word pointer) and the number of bits (bit pointer) at the end of the header signal. It becomes. Therefore, in the digital signal processing circuit (15), the beginnings of the first coded signal that follows are word 5 and bit 4 (the above-mentioned memory unit is used as a word pointer and a bit pointer, respectively).
WP and BP, and may be transmitted to the microcomputer (1)). If the end of the first coded signal (strictly, the end of the signal indicating the end of the block) is word 8 and bit 6, this is sent from the digital signal processing circuit (15) to the microcomputer. Similarly, in the digital signal processing circuit (15), the beginning of the coded signal that follows is the word 8 and bit 7 (the above-mentioned memory units WP and BP are used as a word pointer and a bit pointer, respectively). And may be transmitted to the microcomputer (1)). This will be repeated below.

As shown in FIG. 3, under the control of the microcomputer (1), a still picture digital luminance signal for one frame [768.times.480 pixels forming a matrix of 768 rows and 480 columns] is obtained from the video memory (6). Pixel (8 bits)]
An external RAM (16) of the digital processing circuit (15) divides the signal into block signals composed of 8 × 8 adjacent pixel signals forming an 8 × 8 matrix and outputs the block signals for each block signal.
To the memory section DSPFB. And this memory part DSP
The block signal written in the FB is subjected to signal processing by the digital signal processing circuit (15) as described below.

First, a block signal composed of 8 × 8 pixel signals constituting a matrix of 8 rows and 8 columns stored in a memory section DSPFB of the external RAM (16) is converted into a two-stage primary source discrete cosine as follows. By transform, two-dimensional discrete cosine transform (two-dimensional DC
T)

That is, the eight pixel signals in the first row of the memory unit DSPFB are
After moving to the memory unit FP of the internal RAM (17) and performing a one-dimensional discrete cosine transform [DCT (1)] on these eight pixel signals,
The obtained eight coefficient signals are transferred to the first row of the memory section QE of the internal memory (17). Similarly, the eight pixel signals in the second to eighth rows of the memory unit DSPFB are sequentially transferred to the memory unit FP and subjected to one-dimensional discrete cosine transform [DCT (1)].
The obtained eight coefficient signals are respectively transferred to the second to second memory units QE.
Move to line 8 in order.

Next, after replacing the rows and columns of the 8 × 8 coefficient signals (for example, rounded to 10 bits) constituting the matrix of 8 rows and 8 columns stored in the memory section GE, Similarly, the eight coefficient signals in the first to eighth rows are sequentially stored in the memory unit EP.
And perform one-dimensional discrete cosine transform [DCT (2)].

In this way, the 8 × 8 pixel signals stored in the memory unit DSPFB of the external RAM (16) are subjected to two-dimensional discrete cosine transform to obtain 8 × 8 coefficient signals (for example, 12 × 8).
As shown in FIG. 6C, a DC coefficient signal (signal of an average value of 8 × 8 coefficient signals) (DC) comes to the upper left corner in the same manner as shown in FIG. As the distance increases in the vertical direction, a signal having a coefficient of low to high frequency will be distributed.

Then, the second one-dimensional discrete cosine transform [DCT
In (2)], the eight coefficient signals for each row stored in the memory unit FP are stored in the memory unit QTABLE of the external RAM (16).
, By dividing by the quantization divisor of the corresponding column of each row of the 8-row, 8-column quantization matrix, and then dividing by the corresponding value of the 8-row, 8-column quantization matrix, Quantization is performed (here, the quotient is rounded so as to be represented by 8 bits), and is sequentially written to the memory unit QE for each row. The 8 × 8 quantized coefficient signals forming the matrix of 8 rows and 8 columns stored in the memory section QE have a quantized DC coefficient signal at the upper left corner, and a portion far from the upper left corner has , Many coefficient signals with coefficient 0 (for example, 2/3
Also) distributed.

The quantization matrix of the memory section QTABLE indicates whether the image content of the still image digital video signal for one frame stored in the video memory (6) is different from the luminance signal and the red and blue difference signals. The microcomputer (1) rewrites the image according to the content of the image of the extracted block signal.

Of the 8 × 8 two-dimensional discrete cosine transform and quantized coefficient signals stored in the memory unit QE, the quantized DC coefficient signal at the upper left corner thereof may be directly subjected to Huffman coding. In order to earn the PRED, the initial value is set as a coefficient signal with a coefficient of 0, for example, in the memory unit PRED of the external memory unit (16).
C, and the difference quantization coefficient signal obtained by subtracting the quantization coefficient signal of the immediately preceding block signal from the quantization coefficient signal of a certain block signal is stored in the memory unit DCHUFF of the external RAM (16). After Huffman coding according to the stored Huffman code table, the data is written to the memory section DSPHB of the external RAM (16).

Except for the quantized DC coefficient signal stored in the memory unit QE, since many 0s are distributed in the lower right part of the 8 × 8-1 AC quantized coefficient signals forming the matrix, The zigzag stored in the memory unit ZTABLE of the 8 × 8-1 quantized coefficient signal external RAM (16) forming the matrix is used to increase the compression ratio by increasing the run length of 0 to be described later. 8 × 8 forming a matrix based on the scanning pointer
A set of a run length of 0 of the coefficient signal obtained by zigzag scanning of one quantized coefficient signal and a subsequent non-zero coefficient is
After performing Huffman coding (entropy coding) based on an AC Huffman code table constituting an 8 × 8 matrix stored in the memory unit ACHUFF of the RAM (16), each of the coded signals is Following the normalized DC coefficient signal,
Write to the memory section DSPHB sequentially.

Thus, when a set of a run length of 0 and a non-zero coefficient of a coefficient signal obtained by zigzag scanning is Huffman-coded,
A run length of 0 and non-zero coefficients may be Huffman coded (two one-dimensional codings) based on separate Huffman code tables, or a run length of 0 and non-zero coefficients may be taken on the vertical and horizontal axes. A Huffman coding (two-dimensional coding) may be performed based on one Huffman code table.

The Huffman code table indicates whether the image content of the still image digital video signal for one frame stored in the video memory (6) is different from the luminance signal and the color difference signal, and the block signal extracted therefrom. Is rewritten by the data from the microcomputer (1) depending on the contents of the image.

At the end of the coded signal for each block signal written in the memory section DSPHB, a signal indicating the end is written to the memory section DSPHB.

The bit length of the coded signal for each block signal is represented by the number of words (one word is 8 bits) and the number of bits, and sequentially added to the length of the header signal, that is, the number of words and the number of bits. The encoding of the word integrated value (word pointer) and bit integrated value (bit pointer) for each coded signal for each signal, that is, the number of words and bits at the end of the coded signal for each block signal ends. Each time, it is updated and written in the memory units WP and BP, and transmitted to the microcomputer (1).

The microcomputer (1) controls the digital signal processing circuit (15) to continue the encoding process according to the number of words and the number of bits at the end of the encoded signal for each block signal, or performs the encoding process. After ending the process, it is determined whether to create a header signal for the next frame.

Then, each block signal is sequentially extracted from the 768 × 480 pixel signals constituting the digital luminance signal for one frame stored in the video memory (6), and for each block signal, 2 Obtained by performing dimensional discrete cosine transform, quantization, zigzag scanning and Huffman coding,
The coded signal for each block signal is transferred from the memory unit DSPHB to the communication memory (14) under the control of the microcomputer (1) so as to be sequentially packed and written following the header signal of FIG. I do.

Next, decoding by AIDCT will be described. Here, the decoding of the coded digital luminance signal will be described, and the description of the individual decoding of the two types of coded chrominance signals will be the same as this.

As shown in FIG. 3, under the control of the microcomputer (1), the compression-coded digital luminance signals stored in the communication memory (14) are sequentially transferred from the external RAM ( 16) Decoding memory bank (hereinafter referred to as
The same is written in the memory section DSPHB. This memory section DSPHB is a ring-shaped memory, and its capacity is, for example,
The capacity is set to a predetermined integer multiple of the maximum bit length of the coded signal for each block signal, and the capacity is determined in consideration of the communication speed in the transmission line (13), the expansion decoding time, and the like.

In connection with this ring-shaped memory unit DSPHB, a memory unit WP for word pointer and a memory unit BP for bit pointer are
Provided in the external RAM (16).

The microcomputer (1) calculates the number of words (= 8 bits) and the number of bits of the bit length of the header signal for the compression-coded digital luminance signal signal for one frame, that is, the number of words and the number of bits at the end thereof. (Here, for example, word 5) and the number of words and bits at the end of the coded signal (here, for example, word 8) for each of the first block signals that follow, and the second,
Thirdly, the number of words and the number of bits at the end of the encoded signal for each block signal are stored.

Referring to FIG. 4, the end of the header signal is word 5
If this is the case, the microcomputer (1) calculates the start end of the encoded signal written in the ring-shaped memory unit DSPHB as:
Indicating that the word 6 in the pointer P ₁ (Fig. 4 A).

Assume that the capacity of the ring memory DSPHB is 8 words (= 64
Bit), the ring memory DSPHB has
Starting from word 6 at the beginning of the coded signal of the first block signal, the block coded signal up to word 13 is written, and the start of writing is word 6.
Together represented by the pointer P _2, then that beginning of a coded signal for each block signal decoding is the word 6, expressed as the pointer P _3, the contents of the pointer P _1, P ₂ each, the memory unit Here, of the WP and the memory unit BP, the data is written to the memory unit WP (FIG. 4B). At this time the pointer P ₁ is not changed (Fig. 4 C).

When the decoding of the block coded signal word 6-8 is completed, the next thing beginning of a coded signal for each block signal decoding is word 9 represents a pointer P _3, which is in the memory section WP Although written to be replaced with the contents of the pointer P _3, the pointer P ₂ is not changed (Fig. 4 D).
At this time, the microcomputer (1), the beginning of the coded signal to be written into the ring-shaped memory unit DSPHB represents the pointer P ₁ that the word 9 (Fig. 4 E).

Then, the microcomputer (1) reads the word 6 of the encoded signal written in the ring-shaped memory unit DSPHB.
Instead of ~ 8, word 14, from communication memory (14),
15 and 16 are added to the ring-shaped memory section DS so as to follow the word 13.
It is written in PHB, that the writing start is the word 9, together represented by the pointer P _2, but which is written to be replaced with the contents of the pointer P ₂ in the memory section WP,
Pointer P ₃ does not change (Fig. 4 F).

Returning to FIG. 3, the signal processing in the digital signal processing circuit (15) will be described.
The Huffman coded signal of the difference between the quantized DC coefficient signal of the coded signal for each block signal stored in DSPHB is
After Huffman decoding according to the DC Huffman code table (inverse code table of the DC Huffman code table at the time of encoding) stored in the memory unit DCHUFF of the RAM (16), the data is stored in the memory unit PREDC. In consideration of the coefficient signal of the initial value (0) of the quantized DC coefficient signal, a quantized DC coefficient signal of an encoded signal for each block signal is obtained, and this is stored in the memory section QTABLE of the external memory (16). After inverse quantization is performed by multiplying the quantization matrix (corresponding to the quantization matrix at the time of encoding) by the inverse quantization multiplier (same as the quantization divisor at the time of encoding), the internal memory (17) Write it to the upper left corner of the memory section QE.

The coded signal (excluding the Huffman coded signal of the difference between the quantized DC coefficient signals) for each block signal stored in the ring-shaped memory unit DSPHB is stored in the memory unit ACHUF of the external RAM (16).
Huffman code table for AC stored in F (A
Huffman decoding is performed according to the inverse conversion code table of the Huffman code table for C).

Further, each quantization multiplier constituting the quantization matrix stored in the memory section QTABLE of the external RAM (16) is stored in the external RAM (1).
6) Multiply each quantization multiplier obtained by zigzag scanning by the zigzag scanning pointer stored in the memory unit ZTABLE with the Huffman decoded signal of the coded signal for each block signal, and further multiply this by the external RAM. (16) Memory section ZTABL
After the zigzag scanning is performed by the zigzag scanning pointer stored in E, 8 is stored in the memory section QE of the internal RAM (17).
Writing is performed in the row direction so as to form a row example (excluding the upper left corner) of row 8 column.

Then, the 8 × 8 coefficient signals stored in the memory unit QE of the internal RAM (17) are subjected to two-dimensional inverse discrete cosine transform (two-dimensional ID
CT).

That is, the eight coefficient signals in the first row of the memory section QE are internally stored.
After moving to the memory unit FP of the RAM (17) and subjecting the eight coefficient signals to one-dimensional inverse discrete cosine transform [IDCT (1)],
The obtained eight coefficient signals are transferred to the first row of the memory section QE of the internal memory (17). Similarly, after performing eight-dimensional inverse discrete cosine transform [IDCT (1)] on each of the eight coefficient signals in the second to eighth rows of the memory unit QE, the obtained eight coefficient signals are
The process sequentially moves to the second to eighth rows of the memory unit QE.

Next, after replacing the rows and columns of the 8.times.8 coefficient signals (for example, rounded to 10 bits) stored in the memory section QE, the eight coefficients of each row are replaced in the same manner as described above. After the signals are transferred to the memory unit FP and subjected to one-dimensional inverse discrete cosine transform [IDCT (2)], the memory unit DS of the external memory (16) is used.
Move to each line of PFB.

Thus, a block signal composed of adjacent pixel signals forming a matrix of 8 rows and 8 columns is obtained in the memory section DSPFB of the external RAM (16).

According to such a still image transmission device, a still image transmission device that performs orthogonal transform and compression encoding using a microcomputer (1) and a digital signal processing circuit (15) and then transmits the image is used to transmit a still image signal. The load on the microcomputer (1) for signal processing for orthogonal transform and compression coding for each block signal is reduced, and the speed of the signal processing is increased.

According to such a still image transmission device, the microcomputer (1) generates a header signal, divides the still image signal stored in the frame memory (6) into block signals, and generates a block signal for each block signal. The digital signal processing circuit (15) performs block coding on the block signal, and then transmits the block signal. In the still image transmitting apparatus, the continuity between the header signal and each of the block coded signals is reliably ensured. At the same time, it is possible to obtain a block which can reliably and efficiently perform the block coding of the still image signal for each block signal in the digital signal processing circuit.

〔The invention's effect〕

According to the first aspect of the present invention, an image memory for storing at least one frame of image data, and the image data stored in the image memory are divided into blocks each including a predetermined number of pixel data, and pixel data is output for each block. And a storage area for storing quantization parameters and encoding parameters, orthogonally transforms pixel data supplied from the microcomputer in block units, and converts the converted pixel data based on the quantization parameters. A digital signal processing circuit for performing quantization and coding based on the coding parameter. The microcomputer includes a quantization parameter used for quantization of the digital signal processing circuit and a coding parameter used for coding. Set the parameters and compress / encode data obtained by the digital signal processing circuit. Since adapted to deliver control data, it is possible to obtain an image transmission apparatus capable of obtaining the effect described below.

That is, according to the first aspect of the present invention, the load of the microcomputer can be reduced and the speed of the signal processing can be reduced by performing the orthogonal transformation and the compression encoding processing, which require a lot of arithmetic processing, by the digital signal processing circuit. A high image transmission device can be obtained.

According to the first aspect of the present invention, a storage area is provided in the digital signal processing circuit, and a quantization parameter and an encoding parameter necessary for compression and encoding by the digital signal processing circuit are stored in the storage area. In addition, since the quantization parameter and the encoding parameter are set by the microcomputer, the digital signal processing circuit constitutes a general-purpose digital signal processing circuit, and the optimal quantization parameter and It is possible to set encoding parameters, thereby improving the image quality of the compressed image and improving the compression ratio,
It is possible to obtain an image transmission device that can freely control the compression ratio and can cope with various systems having different transmission path capacities and image qualities.

According to the second aspect of the present invention, the microcomputer divides the image data stored in the image memory storing at least one frame of image data into blocks each having a predetermined number of pixel data, and outputs pixel data for each block. In a digital signal processing circuit having a storage area for storing quantization parameters and coding parameters, a quantization parameter used for quantization and a coding parameter used for coding are set by a micro computer, and The pixel data supplied from the computer is orthogonally transformed in block units by a digital signal processing circuit, and the digital signal processing circuit quantizes the orthogonally transformed pixel data based on a quantization parameter.
The digital signal processing circuit encodes the quantized quantized data based on the encoding parameters, and the microcomputer controls the compressed and encoded data obtained by the digital signal processing circuit. It is possible to obtain an image transmission method capable of obtaining the effects described above.

That is, according to the second aspect of the present invention, the load of the microcomputer can be reduced and the speed of the signal processing can be reduced by performing the orthogonal transformation and compression encoding processing, which require a lot of arithmetic processing, by the digital signal processing circuit. A higher image transmission method can be obtained.

According to the second aspect of the present invention, a storage area is provided in the digital signal processing circuit, and a quantization parameter and an encoding parameter required for compression and encoding by the digital signal processing circuit are stored in the storage area. In addition, since the quantization parameter and the encoding parameter are set by the microcomputer, the digital signal processing circuit constitutes a general-purpose digital signal processing circuit, and the optimal quantization parameter and It is possible to set encoding parameters, thereby improving the image quality of the compressed image and improving the compression ratio,
It is possible to obtain an image transmission method that can freely control the compression ratio and can cope with various systems having different transmission path capacities and image qualities.

By the way, since the general-purpose CPU alone does not have enough processing capacity to execute the image compression / decompression processing, the dedicated digital signal processing circuit performs the orthogonal transformation and compression encoding processing, which are particularly computationally intensive. However, if processing is performed using fixed parameters by a dedicated digital signal processing circuit, it becomes impossible to set optimal quantization parameters and encoding parameters for each image data. However, the image quality of the compressed image cannot be improved, the compression ratio cannot be improved, the compression ratio cannot be freely controlled, and the transmission path capacity and image quality are different. It cannot support various systems.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of encoding in an embodiment of the present invention, FIG. 2 is an explanatory diagram of bit and word pointers at the time of encoding, FIG. 3 is an explanatory diagram of decoding in the embodiment, and FIG. FIG. 5 is a block diagram showing a conventional still image transmission apparatus, and FIG. 6 is an explanatory diagram of conventional encoding. (1) microcomputer, (2) CPU, (6)
Is video memory, (14) is communication memory, (15) is a digital signal processing circuit, (16) is external RAM, (17) is internal RAM
It is.

Continuation of front page (56) References JP-A-2-260989 (JP, A) JP-A-2-237370 (JP, A) JP-A-2-226987 (JP, A) JP-A-1-160193 (JP) JP-A-1-155792 (JP, A) JP-A-64-81587 (JP, A) JP-A-64-51784 (JP, A) JP-A-63-309083 (JP, A) JP-A-63-280594 (JP, A) JP-A-63-42587 (JP, A) JP-A-62-120181 (JP, A) JP-A-61-285870 (JP, A) (58) Fields investigated (Int. Cl ^6, DB name) H04N 7/14 -. 7/15 H04N 7/24 - 7/68

Claims (2)

(57) [Claims] An image memory for storing at least one frame of image data, and a microcomputer for dividing the image data stored in the image memory into blocks each having a predetermined number of pixel data and outputting pixel data for each block And a storage area for storing quantization parameters and encoding parameters, and orthogonally transforms pixel data supplied from the microcomputer in block units, and converts the converted pixel data based on the quantization parameters. A digital signal processing circuit that performs quantization based on the coding parameter, and the microcomputer uses the quantization parameter used for quantization of the digital signal processing circuit and coding. And the digital signal processing. Image transmission apparatus characterized by delivering a compression coded data obtained by the road. 2. The method according to claim 1, wherein the microcomputer divides the image data stored in the image memory for storing at least one frame of image data into blocks each having a predetermined number of pixel data and outputs pixel data for each block. A digital signal processing circuit having a storage area for storing parameters and coding parameters, wherein the microcomputer sets the quantization parameters used for quantization and the coding parameters used for coding by the microcomputer; The pixel data supplied from a computer is orthogonally transformed in block units by the digital signal processing circuit. The digital signal processing circuit quantizes the orthogonally transformed pixel data based on the quantization parameter, Quantized by the processing circuit An image transmission method comprising: encoding the quantized data obtained based on the encoding parameters; and controlling the transmission of the compressed encoded data obtained by the digital signal processing circuit by the microcomputer.