JP2951192B2 - CD-ROM decoder - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CD-ROM system using a compact disk or a laser disk as a read-only memory, and transferring CD-ROM data read from the disk in response to an instruction from a host computer. It relates to a ROM decoder.

[0002]

2. Description of the Related Art A compact disk (CD) conventionally used for digital audio is utilized as a read-only memory (ROM) for digital data.
In the OM system, C read from the disk
In order to improve the reliability of the D-ROM data, the read CD-ROM data is subjected to double code error correction processing. These correction processes are configured such that the first time is executed on the side of the reproduction unit that reads digital data from the disk, and the second time is executed by the CD-ROM decoder connected to this reproduction unit. In general, 1
Regarding the second correction process, the common correction process is performed with an audio CD player.

FIG. 5 is a block diagram showing a configuration of a CD-ROM system. The pickup unit 2 that receives the reflected light of the laser light applied to the compact disc 1 extracts the intensity of the reflected light as a change in the voltage value, and supplies it to the analog signal processing unit 3. The analog signal processing unit 3
From the signal input from the pickup unit 2, the optical disc 1
And reads out the digital data written in the device, and serially outputs digital data conforming to a predetermined format. The digital signal processing unit 4 performs signal processing according to the CD format on the digital data output from the analog signal processing unit 3 to generate CD-ROM data. In the signal processing in the digital signal processing unit 4, compatibility with a CD system for digital audio is maintained, and demodulation of digital data composed of 14 bits into 8 bits, and based on Reed-Solomon code Detection / correction of a code error is performed. The CD-ROM decoder 5 receives the CD-ROM input from the digital signal processor 4.
The ROM data is subjected to code error correction processing again, and is transferred to the host computer as error-free CD-ROM data. The buffer RAM 6 is a CD-RO
It is connected to the M decoder 5 and stores CD-ROM data taken into the CD-ROM decoder 5 from the digital signal processing circuit 4 for a predetermined period. And the control microcomputer 7
Controls the operations of the analog signal processing unit 3, the digital signal processing unit 4, and the CD-ROM decoder 5 in accordance with the operation program, so that the units can execute various processes at the correct timing.

[0004] CD output from digital signal processing section 4
As shown in FIG. 6, the ROM data is composed of 2352 bytes as one sector, and includes a synchronization signal (12 bytes),
Header (4 bytes), user data (2336 bytes)
Are assigned respectively. The synchronization signal indicates the head position of the sector and is attached to the beginning of each sector as a fixed pattern. The 4-byte header further includes absolute time information (minute / second / frame number: 1 byte each) corresponding to an address on the disk and a mode identification code (1 byte) for determining the format of data in a sector.
Assigned to. In the case of CD-ROM data, 2340 obtained by removing the synchronization signal 12 bytes from the data of one sector.
The bytes are scrambled so that the same pattern as the synchronization signal is unlikely to be generated. At the stage when the bytes are input to the CD-ROM decoder 5, the bytes are descrambled and returned to the original data.

FIG. 7 is a block diagram showing the configuration of the CD-ROM decoder 5. The descramble circuit 11
CD-RO input every 2352 bytes (1 sector)
A descrambling process is performed on 2340 bytes of the M data excluding a 12-byte synchronization signal, and data returned to a predetermined format is output. The write buffer 12 captures 2336 bytes of user data out of the data output from the descramble circuit 11 and writes the user data to the buffer RAM via the first data bus 16. The header register 13 takes in a 4-byte header from the data output from the descramble circuit 11 and transfers the header information from the second data bus 17 to the control microcomputer 7. The synchronizing signal detecting circuit 14 detects a 12-bit synchronizing signal added to the beginning of each sector of the input data, and detects the input CD-R.
A timing signal indicating the start of a sector of the OM data is supplied to an operation control circuit 24 described later. When no synchronization signal is detected, data indicating a detection error is transferred from the second data bus 17 to the control microcomputer 7. The error flag register 15 takes in an error flag indicating that an error has been left in the error correction processing in the digital signal processing unit 4 provided in the preceding stage of the CD-ROM decoder 5, and sends the control microcomputer from the second data bus 17. Transfer to 7.

The write address generation circuit 18 generates a continuous address at a constant cycle, and
2 specifies the write address of the CD-ROM data to be written to the buffer RAM 6. The start address generation circuit 19 writes an address when the head of each sector is written in the buffer RAM 6 into the write address generation circuit 1.
8 and hold it until writing of one sector of CD-ROM data is completed, and then the first data bus 1
Send to 6. The head address is transferred from the second data bus 17 to the control microcomputer 7 so as to generate preset data of a transfer address generation circuit 21 described later. The error correction circuit 20 captures the head address data sent to the first data bus 16 and, based on the data, the CD-RO written in the buffer RAM 6.
M data is sequentially read, and an error detection code (EDC) and an error correction code (EDC) set in the user data are read.
CC) to detect and correct the code error. Here, the data for which the predetermined correction processing has been completed is written to the buffer RAM 6 again, and then sequentially transferred from the transfer buffer 24 to the host computer.

The transfer address generation circuit 21 loads preset data corresponding to the address of the buffer RAM 6 in which the CD-ROM data to be read is written, and responds to an instruction from the transfer trigger generation circuit 22 to
A continuous address is generated at a fixed cycle starting from an address corresponding to the preset data. The address generated here is transmitted from the first data bus 16 to the buffer RAM.
6, and specifies the read address of the CD-ROM data that has been subjected to the error correction processing. The transfer byte counter 23 indicates a CD-RO to be read from the buffer RAM 6.
After loading data indicating the number of bytes of M data as preset data, the buffer RAM 6 stores the data in the CD-ROM.
It counts down every time data is read out, and gives a stop instruction to the transfer trigger generating circuit 22 when a predetermined number of counts are completed. The transfer buffer 24 takes in the CD-ROM data read according to the address generated by the transfer address generation circuit 21 through the first data bus 16 and transfers the data to the host computer. The preset microcomputer loaded into the transfer address generation circuit 21 and the transfer byte counter 23 is generated by the control microcomputer 7 based on the start address transferred from the start address generation circuit 19 and the transfer instruction given from the host computer.

The operation control circuit 25 includes a synchronization signal detection circuit 1
Based on the timing signal output from 4, the time until the error correction processing by the error correction circuit 20 is completed is measured, and a timing signal indicating the completion of the operation is generated. The error correction processing by the error correction circuit 20 is performed by the buffer R
After fetching one sector of CD-ROM data from the AM 6, the error correction is performed inside the error correction circuit 20. During that time, the next sector of CD-ROM data is written into the buffer RAM 6. The interrupt instruction generating circuit 26 receives a timing signal from the operation control circuit 25 or an instruction to stop the transfer byte counter 23, and transmits an interrupt instruction to the control microcomputer 7. The control microcomputer 7, which controls the operation of the analog signal processing unit 3 and the digital signal processing unit 4 by time-division processing, responds to the interrupt instruction from the interrupt instruction generating circuit 26, temporarily suspends the processing operation up to that point. It causes the CD-ROM decoder 5 to execute the following processing operation.
For example, in response to an interrupt instruction from the interrupt instruction generating circuit 26, the transfer trigger generating circuit 22 is activated after interrupting other processing operations, and data transfer from the buffer RAM 6 to the host computer is started.

In the above CD-ROM system,
The header information for each sector is repeatedly taken out and taken into the control microcomputer 7, and the sector requested by the host computer is detected based on the address information in the header information.

[0010]

In the control microcomputer 7 for performing the sector detection processing based on the address information,
In addition to the operation control of the D-ROM decoder 5, the operation control of the analog signal processing unit 3 and the digital signal processing unit 4 is performed in a time-division manner, so that the load on the control microcomputer 7 is increased. In particular, in the case of the mode 2 format in which the header is not subjected to the error detection / correction code, it is necessary to determine whether or not the header information is correct by referring to the error flag transferred from the error flag register 15. 7 has a problem of insufficient processing capacity. Therefore, it is difficult to speed up the control operation of the control microcomputer 7, and the amount of data that can be handled by the CD-ROM decoder 5 is limited.

SUMMARY OF THE INVENTION An object of the present invention is to provide a high-performance and easy-to-use CD-ROM decoder which reduces the load on an operation control microcomputer.

[0012]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and has a feature in that digital data read from a disk medium is corrected for errors contained in the data. In the CD-ROM decoder which transfers the data to the computer device side, means for taking in address information attached to each sector of the digital data continuously read from the disk medium, and a target address are set. Means for generating a start signal when the address coincides with the target address, and starting transfer of digital data to the computer device in response to the start signal.

[0013]

According to the present invention, the start signal is generated when the address information matches the target address information, so that the CD-RO of the sector to which the desired address is assigned is generated.
When the M data is input, the transfer of the CD-ROM data to the computer device starts regardless of the instruction of the operation control microcomputer. The operation control microcomputer only needs to give an instruction to the CD-ROM decoder when setting the address information of the sector requested by the computer device as the target address information, and is input continuously for each sector. There is no need to determine whether the address information of the CD-ROM data is the desired address information.

[0014]

FIG. 1 is a block diagram showing the structure of a CD-ROM decoder according to the present invention. In this figure, components other than an address information discriminating unit 30 for taking in address information, such as a descramble circuit 11 and an error correction circuit 20, are the same as those in FIG. 7, and are denoted by the same reference numerals.

Address information discriminating section 30 for searching for a desired sector based on the address information of the CD-ROM data
Is composed of an address information register 31, a target address information register 32, a comparison circuit 33, a transfer trigger generation circuit 34, and a transfer sector counter 35. The address information register 31 takes in address information of the header from the descrambled CD-ROM data output from the descramble circuit 11 for each sector,
The data is transmitted to the second data bus 17. The address information attached to each sector is composed of a 3-byte binary coded decimal (BCD) representing minutes, seconds, and a frame number, and is carried by one second every 75 frames. Carry by one minute every second (4500 frames). The target address information register 32 takes in and stores the target address information provided through the second data bus 17, and repeatedly outputs the target address information.
The target address information given to the target address generation circuit 32 indicates the address of the first sector requested to be transferred by the host computer, and is supplied by the control microcomputer 7 in response to an instruction from the host computer. The comparison circuit 33 compares the target address information output from the target address information register 32 with the address information output from the address information register 31, and generates a start pulse which rises when each information matches.
After loading transfer sector information indicating the number of sectors to be transferred as preset data, the transfer sector counter 34 responds to a timing signal output from the synchronization signal detection circuit 14 every time one sector of CD-ROM data is input. To generate a stop pulse that rises when the count value returns to the initial value. Then, the transfer trigger generating circuit 35 gives a transfer start instruction to the transfer address generating circuit 21 and the transfer byte counter 23 in response to the rise of the start pulse, and provides the transfer address generating circuit 21 in response to the rise of the stop pulse.
To stop the transfer. The stop pulse is
The interrupt instruction is also supplied to the interrupt instruction generating circuit 26, and an interrupt instruction is transmitted to the host computer when the transfer of a predetermined number of sectors is completed. On the other hand, the mode information register 36 provided in parallel with the address information register 31 takes in the mode identification code of the CD-ROM data output from the descramble circuit 11 and transfers it to the control microcomputer 7 from the second data bus 17.

After setting the target address information and setting the transfer sector information, the address information discrimination section 30 controls the control microcomputer 7 until input and transfer of CD-ROM data of a predetermined number of sectors are completed. It operates continuously without receiving instructions from. For example, as shown in FIG. 2, when transferring CD-ROM data for 75 sectors from the sector assigned the address of “03:15:59”,
First, the target address information "03:15:59" is stored in the target address information register 32, and at the same time, the transfer sector information "74" is set in the transfer sector counter 34. continue,
When the address information sequentially read into the address information register 31 becomes "03:15:59", the transfer circuit 35 detects the coincidence with the target address information and raises a start pulse. An instruction to start transfer is given to the generation circuit 21. Then, at the rise of the start pulse, the transfer byte counter 34 starts counting down. When the count value becomes “0” and the stop pulse rises, the transfer trigger generation circuit 35 instructs the transfer address generation circuit 21 to stop the transfer. Give instructions. At the same time, the interrupt instruction generating circuit 26 transmits an interrupt instruction to the control microcomputer 7 in response to the rise of the stop pulse. Therefore, continuously input CD-ROM data is transferred from the transfer buffer 24 to the host computer side for 75 sectors starting from the sector to which the address “03:15:59” is attached. During this time, the control microcomputer 7 is not involved in the operation of determining the address information,
Other control operations can be performed.

FIG. 3 is a block diagram showing a configuration of a CD-ROM decoder according to the present invention to which a function of correcting a code error of address information is added. The address information discriminating section 40 for searching for a desired sector after correcting the code error of the address information of the CD-ROM data adds an increment circuit 37, a selecting circuit 38 and a comparing circuit 39 to the address information judging section 30 of FIG. It is composed. The increment circuit 37 generates the next predicted address information by adding “1” to the address information read from the address information register 31. Here, the increment circuit 37
When the address information is fetched into the address information register 31, the next address information is fetched into the address information register 31. The selection circuit 38 receives the address information read from the address information register 31 and the increment circuit 37, selects one of them, and outputs it. The comparison circuit 39 includes: address information read from the address information register 31;
It is determined whether or not the contents of the address information read from the increment circuit 37 match, and a control pulse corresponding to the determination result is generated. This control pulse is applied to the selection circuit 38. When the two pieces of address information match, the address information of the address information register 31 is selected, and when they do not match, the address information of the increment circuit 37 is selected and output. When the two pieces of address information do not match, the address information stored in the address information register 31 includes a code error. Therefore, the increment circuit 38 does not take in the address information from the address information register 31 but stores the address information itself. The next address information is generated by adding "1" to the current address information.

The target address information register 32, comparison circuit 33, transfer sector counter 34 and transfer trigger generation circuit 35 are the same as those in FIG.
Is configured to generate a transfer start instruction when the address information output from the CPU matches the target address information, and to generate a transfer stop instruction when the number of transfer sectors reaches the value of the transfer sector information. .

The address information stored in the increment circuit 38 is stored in the address information register 3 at the same timing.
Although the address information is shifted by 1 sector from the address information stored in 1, since "1" is added, if there is no code error, the address information matches the address information stored in the address information register 31. However, when a code error occurs, the address information stored in the address information register 31 becomes discontinuous, whereas the address information stored in the increment circuit 38 at the same timing becomes continuous. Address information does not match. For example, as shown in FIG. 4, the address information input to the address information register 31 is "03:
15:58 "and" 03:15:59 "where it should be" 03: 15: A7 ", the address information stored in the increment circuit 38 is next to" 03:15:58 ". Is "03:15:59", and the regularity is maintained. Therefore, when the address information read from the address information register 31 does not match the address information read from the increment circuit 38, it is determined that the address information stored in the address information register 31 contains a code error, and the comparison circuit 39 , The selection circuit 38 selects the address information read from the increment circuit 38. At the same time, the increment circuit 38 adds "1" to the address information stored therein to generate the next address information, thereby maintaining the regularity of the address information read from the next increment circuit 38. I have. For example, as shown in FIG. 4, when the address information stored in the address information register 31 is "03: 15: A7", the address information "03:15:59" stored in the increment circuit 38 itself is "1:15:59". Is added to generate address information “03:15:60” and newly stored. The subsequent operation of determining the address information corresponds to the case of the timing chart shown in FIG.

According to the above configuration, even when input address information loses regularity due to a code error, the regularity generated from the address information one sector before is maintained instead of the address information. The address information for correction is output. Therefore, even if the address information of the sector to be transferred is missing due to a code error, the sector indicated by the target address information is detected by the address information determining unit 40.

[0021]

According to the present invention, the address information is discriminated in the CD-ROM decoder, and the specific sector of the target CD-ROM data can be detected without the instruction of the control microcomputer. The number of sectors of the CD-ROM data transferred to the host computer is C
By counting in the D-ROM decoder, a predetermined number of sectors of CD-ROM data are automatically transferred starting from the specific sector detected by the determination of the address information. Therefore, it is not necessary for the control microcomputer to determine the address information, so that the burden on the control microcomputer can be reduced, and the CD-ROM decoder can quickly respond to an instruction from the host computer. Further, in the application products of the CD-ROM system, the control microcomputer can be easily developed, and the versatility can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the first embodiment.

FIG. 3 is a block diagram showing a second embodiment of the present invention.

FIG. 4 is a timing chart for explaining the operation of the second embodiment.

FIG. 5 is a block diagram showing a configuration of a CD-ROM system.

FIG. 6 is a diagram showing a format of CD-ROM data.

FIG. 7 is a block diagram showing a configuration of a conventional CD-ROM decoder.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 compact disk 2 pickup unit 3 analog signal processing unit 4 digital signal processing unit 5 CD-ROM decoder 6 buffer RAM 7 control microcomputer 11 descramble circuit 12 write buffer 13 header register 14 synchronization signal detection circuit 15 error flag register 16 first Data bus 17 Second data bus 18 Write address generation circuit 19 Start address generation circuit 20 Error correction circuit 21 Transfer address generation circuit 22 Transfer trigger generation circuit 23 Transfer byte counter 24 Transfer buffer 25 Operation control circuit 26 Interrupt instruction generation circuit 30, 40 selection control circuit 31 address information register 32 target address information register 33 comparison circuit 34 transfer sector counter 35 transfer trigger generation circuit 36 mode information register 37 a. Increment circuit 38 Selection circuit 39 Comparison circuit

Claims (4)

(57) [Claims] 1. A CD-ROM decoder for correcting digital data read from a disk medium to correct an error contained in the data and transferring the corrected data to a computer device side. Means for fetching address information attached to each sector, means for setting a target address, and generating a start signal when the address information matches the target address, wherein the computer responds to the start signal A CD-ROM decoder for starting transfer of digital data to a device. 2. A CD-ROM decoder which corrects errors included in data read from a disk medium and transfers the corrected data to a computer device side, wherein one of the digital data continuously read from the disk medium is read. Means for taking in address information attached to each sector, means for setting a target address, generating a start signal when the address information matches the target address, and counting the number of sectors of the input digital signal Means for generating a stop signal when a predetermined number of sectors is reached, starting transfer of digital data to the computer device in response to the start signal, and responding to the stop signal. CD-RO for stopping transfer of digital data to a computer device
M decoder. 3. A CD-ROM decoder for subjecting digital data read from a disk medium to a process of correcting an error contained in the data and transferring the digital data to a computer device side, wherein one of the digital data continuously read from the disk medium is read. A first register that fetches and stores address information attached to each sector, a second register that stores target address information indicating a target address, and a storage content of the first register that is stored in the second register. A comparison circuit that generates a first timing signal when the data matches the stored content; and a counter that counts the number of sectors of the input digital data and generates a second timing signal when the count reaches a predetermined count value. Opening the transfer of the digital data to the computer device in response to the first timing signal. And a control circuit for stopping transfer in response to the second timing signal. 4. A CD-ROM decoder for subjecting digital data read from a disk medium to a process of correcting an error contained in the data and transferring the digital data to a computer device side, wherein one of the digital data continuously read from the disk medium is read. A first register that fetches and stores the address information assigned to each sector, an increment circuit that advances the address information stored in the first register by one, and stores the information; A selection circuit that replaces the address information read from the first register with the address information read from the increment circuit when the contents of the first register do not match the storage contents of the first register and outputs the selected address information; Register and the selection circuit
A comparison circuit for generating a first timing signal when the content of the output of the second register matches the content stored in the second register;
A counter that counts the number of sectors of the digital data and generates a second timing signal when the count reaches a predetermined count value; and a counter of the digital data to the computer device in response to the first timing signal. A control circuit for starting transfer and stopping transfer in response to the second timing signal.
OM decoder.