JP2946531B2 - Auto focus circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an autofocus circuit for a video camera.

[Summary of the Invention]

According to the present invention, there is provided a video signal in which a mid-high frequency component in a video signal is detected, an evaluation value is obtained by integrating the detected mid-high frequency component in the video signal, and a lens position control is performed using the evaluation value. In the camera autofocus circuit,
By configuring the filter for detecting the middle and high frequency components in the video signal, from the input signal, by subtracting the input signal that has passed through the low-pass filter having characteristics similar to those obtained when the light passed through the lens system, The slope of the curve of the evaluation value characteristic is made substantially constant so that focus control can be accurately performed over a wide range.

[Conventional technology]

As one of the autofocus methods, utilizing the fact that the frequency component excluding the DC component of the video signal is maximized at the in-focus position, the value obtained by integrating the frequency components excluding the DC component of the video signal is used as evaluation value data. In some cases, the position of the lens is controlled to a position where the evaluation value data is maximized.

In such an autofocus method, the position of the lens is controlled to a focus position at which the evaluation value data becomes maximum, and before and after the evaluation value data is compared, it is determined whether the evaluation value data changes from increasing to decreasing. Control is performed to make a judgment. Such control is called hill-climbing control.

FIG. 18 shows an example of such a conventional autofocus circuit.

In FIG. 18, a lens 201 is moved by a drive motor 202. The image passed through the lens 201 is a CCD image sensor 203
Is imaged. The output of the CCD image sensor 203 is output to the signal processing circuit 20.
Supplied to 4. A luminance signal Y is extracted from the signal processing circuit 204, and the luminance signal Y is supplied to a detection circuit 206 via a filter 205 that extracts a frequency component excluding a DC component of the video signal. The output of the detection circuit 206 is supplied to the A / D converter 207. The output of the A / D converter 207 is supplied to the integrating circuit 208. A / D converter within predetermined area by integrating circuit 208
The output of 207 is integrated. The output of the integrating circuit 208 is used as evaluation value data.
Supplied to A drive signal of the drive motor 202 is output from the controller 210, and the drive signal is supplied to the drive motor 202 via the driver 211.

The controller 210 controls the lens position of the lens 201 at a position where the evaluation value data output from the integrating circuit 208 is maximized. For such control, hill-climbing control is used.

That is, for example, it is assumed that the relationship between the lens position and the evaluation value data is represented by a curve as shown in FIG. In this case, while moving the lens 201 in one direction, the evaluation value data D _n obtained at the lens position l _n and the evaluation value data D _{n + 1} obtained at the subsequent lens position l _{n + 1} are compared. , Evaluation value data obtained at lens position l _n
D _n is the lens 201 is moved to smaller than the evaluation value data D _{n + 1} obtained by the lens position l _{n + 1} consecutive thereto.

As shown in FIG. 19, when the lens position is moved rightward, the evaluation value data increases until the evaluation value data passes through the lens position l _{focus at} which the maximum value D _max is reached. When the evaluation value data passes through the lens position l _{focus at} which the maximum value D _max is reached, the evaluation value data starts to decrease. Therefore, while moving the lens position in one direction, it is determined whether or not the evaluation value data D _n , D _{n + 1 of} the front and rear lens positions l _n , l _{n + 1} turn from increasing to decreasing. When such hill-climbing control is performed, it can be determined that the evaluation value data has reached the lens position l _focus at which the evaluation value data has the maximum value D _max , thereby obtaining the in-focus position.

[Problems to be solved by the invention]

Conventionally, for example, a third-order analog Chebyshev approximation filter is used as the filter 205 for extracting a frequency component excluding a DC component of a video signal in such an autofocus circuit. FIG. 20 shows evaluation value characteristics in a conventional autofocus circuit using such an analog filter.

As shown in FIG. 20, in such a conventional autofocus circuit, the slope of the curve of the evaluation value characteristic is not constant. When the lens position moves away from the in-focus position l _focus , the slope of the curve of the evaluation value characteristic almost disappears. Thus, if the initial position of the lens is distant from the focus position as shown by l _p in FIG. 20 is a lens port John l _p
Evaluation value data and the lens position l following this
There is almost no difference from the evaluation value data at _{p + 1, making} it difficult to focus.

If the overall gain is increased so that focusing can be achieved even when the initial position of the lens is far from the focus position, and the curve of the evaluation value characteristic is inclined to some extent even if the initial position of the lens is far from the focus position, , A wide dynamic range is required, and processing becomes difficult.

Accordingly, it is an object of the present invention to provide an autofocus circuit in which the slope of a curve of an evaluation value characteristic is constant and a focus position is easily obtained.

[Means for solving the problem]

The present invention is directed to an automatic apparatus for detecting a middle-high frequency component in a video signal, integrating the detected middle-high frequency component of the video signal to obtain an evaluation value, and performing lens position control using the evaluation value. In the focus circuit, the filter for detecting the middle and high frequency components in the video signal is configured to subtract from the input signal an input signal that has passed through a low-pass filter having characteristics similar to characteristics when the signal has passed through a lens system. An auto-force circuit is characterized in that:

[Action]

As a filter circuit for extracting a predetermined frequency component in a video signal, a filter circuit including a lens system blur function approximating low-pass filter and a subtractor is used. When such a filter circuit is used as a filter circuit for extracting a predetermined frequency component in a video signal, the curve of the evaluation value characteristic approaches the curve of the ideal evaluation value data.

〔Example〕

Embodiments of the present invention will be described in the following order.

a. Overall configuration b. Specific configuration of filter circuit b1. First example of filter circuit b2. Second example of filter circuit b3. Third example of filter circuit b4. Fourth example of filter circuit b5. Filter Fifth Example of Circuit b6. Sixth Example of Filter Circuit b7. Seventh Example of Filter Circuit c. Evaluation Value Characteristics in One Embodiment a. Overall Configuration FIG. 1 shows one embodiment of the present invention. Things. In FIG. 1, a lens 1 is moved by a drive motor 2. An image that has passed through the lens 1 is captured by the CCD image sensor 3. The output of the CCD image sensor 3 is supplied to the signal processing circuit 4. The luminance signal Y is extracted from the signal processing circuit 4 and supplied to the A / D converter 5. The luminance signal Y is digitized by the A / D converter 5.

The output of the A / D converter 5 is supplied to the filter circuit 6. The filter circuit 6 includes a lens system blur function approximation low-pass filter 7 and a subtraction circuit 8. The lens-system blur function approximation low-pass filter 7 has characteristics similar to characteristics in which high-frequency components are lost when blur occurs through the lens system. The specific configuration of the filter circuit 6 will be described later in detail.

The output of the filter circuit 6 is supplied to the detection circuit 9. The detection circuit 9 detects the output level of the filter circuit 6.
The output of the detection circuit 9 is supplied to the integration circuit 10. Integrating circuit
At 10, the outputs of the detection circuits 9 in the predetermined area are integrated.

The output of the integrating circuit 10 is used as evaluation value data, and the evaluation value data is supplied to the controller 11. A drive signal for the drive motor 2 is output from the controller 11, and the drive signal is supplied to the drive motor 2 via the driver 12.

The controller 11 controls the lens position of the lens 1 at a position where the evaluation value data output from the integrating circuit 10 is maximized. For such control, the lens 1
The so-called hill-climbing control is used in which the evaluation value data of successive lens positions is compared while moving in one direction, and the lens position at which the evaluation value data of the continuous lens position changes from increasing to decreasing.

When the in-focus position is obtained by such hill-climbing control, it is desired that the slope of the curve of the evaluation value characteristic is substantially constant as shown in FIG. In FIG. 2, the horizontal axis is the lens position, the vertical axis is the evaluation value data, and _if is the focus position.

In one embodiment of the present invention, the filter circuit 6 includes a lens system blur function approximate low-pass filter 7 and a subtraction circuit 8. As the lens system blur function approximation low-pass filter 7, an averaging digital low-pass filter is used as described later in detail.
Such a filter is not limited to an averaging digital low-pass filter.

Lens system blur function approximation low-pass filter 7 and subtractor 8
Using a filter composed of the following, to detect the spectral components in the video signal to obtain an evaluation value,
The curve of the evaluation value characteristic approaches an ideal curve as shown in FIG. An ideal curve is a curve in which the inclination becomes substantially constant.

b. Specific Configuration of Filter Circuit Hereinafter, a specific configuration of the filter circuit 6 will be described.

b1. First Example of Filter Circuit The filter circuit 6 includes a lens system blur function approximating low-pass filter 7 and a subtractor 8. As this lens system blur function approximation low-pass filter 7, for example, an N-stage (2m) averaging digital low-pass filter can be used.

The transfer function H (z) of the averaging digital low-pass filter of N stages (2m) is Indicated by FIG. 3 shows a configuration of an averaging digital low-pass filter based on the above equation. Note that terms of the group delay correction amount Z ^m are excluded.

In FIG. 3, one-sample delay circuits 22 _{1 to} 22 of 2 m stages are shown.
_2m are cascaded, and one end of this cascade connection
Is derived. Output between the respective stages of the delay circuits 22 ₁ through 22 _2m are supplied to the adding circuit 23. The output of the adder circuit 23 is (1 / (2m +
1)) It is supplied to the multiplication circuit 24. An output terminal 25 is derived from the (1 / (2m + 1)) multiplication circuit 24.

FIG. 4 shows the characteristics of such an averaging digital low-pass filter. In this example, ((2m
+1) = 33). In FIG. 4, a solid line indicates an amplitude characteristic, and a broken line indicates a phase characteristic.

The filter circuit 6 in FIG. 1 can be realized by a configuration in which the input signal passed through the averaging digital low-pass filter shown in FIG. 3 is subtracted from the input signal.

That is, as shown in FIG. 5, the filter circuit 6 supplies the signal from the input terminal 21 to one input terminal of the subtraction circuit 26, and outputs the output of the averaging digital low-pass filter 28 to the other input terminal of the subtraction circuit 26. This is realized by a configuration in which the output signal of the low-pass filter 28 is subtracted from the signal from the input terminal 21 by the subtraction circuit 26, and the output of the subtraction circuit 26 is extracted from the output terminal 27. Note that the subtraction circuit 26
This corresponds to the subtraction circuit 8 in the figure.

b2. Second Example of Filter Circuit However, in the averaging digital filter shown in FIG. 3, the outputs between the stages of the _2m delay circuits 21 _{1 to} 22 _2m and the delay circuits 22 _{1 to} 22 _2m are added. The addition circuit 23 is required, and the hardware becomes very large. Therefore, simplification of hardware will be considered.

Subtracting the equation from 1 gives the following high-pass filter characteristics.

The equation can be modified as follows.

FIG. 6 shows a configuration of a high-pass filter based on the equation. In FIG. 6, a digital signal from an input terminal 31 is supplied to an m sample delay circuit 32, a (2m + 1) sample delay circuit 33, and also to a subtraction circuit. The output of the (2m + 1) sample delay circuit 33 is supplied to the subtraction circuit 34.

The output of the subtraction circuit 34 is supplied to the addition circuit 36. The output of the addition circuit 35 is supplied to the subtraction circuit 36 and is also fed back to the addition circuit 35 via the one-sample delay circuit 37.

The output of the m-sample delay circuit 32 is a (2m + 1) multiplication circuit 38
Supplied to (2m + 1) The output of the multiplication circuit 38 is a subtraction circuit
Supplied to 36. The output of the subtraction circuit 36 is (1 / (2m + 1))
The signal is supplied to the multiplication circuit 39. (1 / (2m + 1)) multiplication circuit 39
The output terminal 40 is derived from.

The characteristics of the digital high-pass filter of the equation or the transfer function shown in the equation are as shown in FIG. In addition,
In this example, ((2m + 1) = 33). In FIG. 7, a solid line indicates an amplitude characteristic, and a broken line indicates a phase characteristic.

b3. Third Example of Filter Circuit The configuration shown in FIG. 6 also requires the coefficient multiplying circuit 38 or a multi-stage delay circuit, and the hardware scale is not sufficiently reduced. Also, if there is a multiplication circuit, it is difficult to increase the speed. FIG. 8 further simplifies the hardware.

In FIG. 8, the m sample delay circuit 52 and (m + 1)
The sample delay circuit 53 is cascaded. The input digital signal from the input terminal 51 is supplied to the subtraction circuit 54, and is also supplied to the subtraction circuit 54 via the m sample delay circuit 52 and the (m + 1) sample delay circuit 53.

m sample delay circuit 52 and (m + 1) sample delay circuit
The output from the connection point with 53 is supplied to the adding circuit 56 and also to the multiplying circuit 55 having a coefficient of 2 m. The multiplication circuit 55 with the coefficient 2m is realized by a bit shift circuit. The output of the multiplication circuit 55 is supplied to the addition circuit 56. Adder circuit 56
Is supplied to the subtraction circuit 58.

The output of the subtraction circuit 54 is supplied to the addition circuit 57. The output of the addition circuit 57 is supplied to the subtraction circuit 58 and is also fed back to the addition circuit 57 via the one-sample delay circuit 59. The output of the subtraction circuit 58 is taken out from the output terminal 60.

A third example of the present invention is based on the configuration shown in FIG.
It simplifies the hardware.

That is, in FIG. 6, the (1 / (2m + 1)) multiplication circuit
Since 39 determines the overall gain, it can be omitted.

Further, the configuration shown in FIG. 6 requires a multiplication circuit 38 for the coefficient (2m + 1). Since such a multiplying circuit 38 must be configured using a multiplier, the hardware scale becomes large and it becomes an obstacle to speeding up.

The multiplication of (2m + 1) can be constituted by a multiplication circuit of a coefficient 2m and an addition circuit. The multiplication circuit with a coefficient of 2m can be realized by a bit shift circuit. As described above, if the multiplication circuit for the coefficient (2m + 1) is constituted by the bit shift circuit and the addition circuit, the hardware scale can be reduced and the processing speed can be improved.

In the filter circuit shown in FIG. 8, the multiplication circuit 38 for the coefficient (2m + 1) in FIG. 6 is composed of a multiplication circuit 55 for the coefficient 2m and an addition circuit 56 formed of a bit shift circuit. As a result, the hardware scale can be reduced.

In FIG. 6, a (2m + 1) sample delay circuit
33 can be replaced by a cascade connection of an m sample delay circuit and an (m + 1) sample delay circuit. (2m + 1)
The sample delay circuit 33 is replaced with an m sample delay circuit and (m + 1)
If replaced with a sample delay circuit, the output of the connection point between the m sample delay circuit and the (m + 1) sample delay circuit is supplied to the multiplication circuit 38 of the coefficient (2m + 1), so that the m sample delay circuit 32 can be omitted. it can.

In the filter circuit shown in FIG. 8, (2 m
+1) The sample delay circuit 33 is a cascade connection of the m sample delay circuit 52 and the (m + 1) sample delay circuit 53, and the output of the connection point between the m sample delay circuit 52 and the (m + 1) sample delay circuit 53 is multiplied by a coefficient 2m. The hardware scale is reduced by supplying the data to a bit shift circuit and an addition circuit 56 as the circuit 55.

b4. Fourth Example of Filter Circuit FIG. 9 shows a fourth example of the filter circuit.
In FIG. 9, an (m + 1) sample delay circuit 62 and an m sample delay circuit 63 are cascaded. The input digital signal from the input terminal 61 is supplied to the subtraction circuit 64, and is also supplied to the subtraction circuit 64 via the (m + 1) sample delay circuit 62 and the m sample delay circuit 63.

(M + 1) Sample delay circuit 62 and m sample delay circuit
The output from the connection point with 63 is supplied to the addition circuit 66 and also to the multiplication circuit 65 having a coefficient of 2 m. Multiplication circuit 65
Can be realized by a bit shift circuit. The output of the multiplication circuit 65 is supplied to the addition circuit 66.

The output of the adding circuit 66 is supplied to the one-sample delay circuit 72. The output of the one-sample delay circuit 72 is supplied to a subtraction circuit 68.

The output of the subtraction circuit 64 is supplied to the one-sample delay circuit 71. The output of the one-sample delay circuit 71 is supplied to the addition circuit 67. The output of the adding circuit 67 is supplied to a one-sample delay circuit 69. The output of the one-sample delay circuit 69 is fed back to the addition circuit 67 and is also supplied to the subtraction circuit 68. Subtraction circuit
The output of 68 is taken out from the output terminal 70.

In the fourth example, the configuration of the third example shown in FIG. 8 is further simplified.

That is, a register that latches the addition output and the subtraction output is required at the subsequent stage of the addition circuit and the subtraction circuit. Therefore, when realizing the third example shown in FIG.
A one-sample delay circuit is provided after the subtraction circuit 54, and a one-sample delay circuit is provided after the addition circuit 56.
A one-sample delay circuit will be provided after 57.
With the provision of the one-sample delay circuit after the adder circuit 57, it is necessary to further provide a one-sample delay circuit for delay adjustment after the adder circuit 56.

In the fourth example, the output of the addition circuit 67 is supplied to the one-sample delay circuit 69, and the output of the one-sample delay circuit 69 is fed back to the addition circuit 67 and supplied to the subtraction circuit 68. The one-sample delay circuit 69 delays the output of the adder circuit 57 by one sample in the third example and feeds it back, and the one-sample delay circuit that latches the added output of the adder circuit 57. It is common. The delay circuit 62 has a one-sample delay circuit for delay adjustment. Thus, the hardware can be reduced.

b5. Fifth Example of Filter Circuit FIG. 10 shows a fifth example of the filter circuit. In FIG. 10, an (m-1) sample delay circuit 82, a one-sample delay circuit 83, and an m-sample delay circuit 84 are cascaded. An input digital signal from an input terminal 81 is supplied to a subtraction circuit 85, and (m-1) a sample delay circuit 82, a one-sample delay circuit 83, and an m-sample delay circuit
The signal is supplied to a subtraction circuit 85 via 84.

(M-1) Sample delay circuit 82 and one-sample delay circuit
The output at the point of connection with 83 is supplied to a multiplication circuit 86 of coefficient m. The multiplication circuit 86 for the coefficient m can be constituted by a bit shift circuit. The output of the multiplication circuit 86 for the coefficient m is supplied to the addition circuit 87.

The output at the connection point between the one-sample delay circuit 83 and the m-sample delay circuit 84 is supplied to a multiplication circuit 88 of coefficient m. In addition,
The multiplication circuit 88 for the coefficient m can be constituted by a bit shift circuit. The output of the multiplication circuit 88 for the coefficient m is supplied to the addition circuit 87. The output of the adding circuit 87 is supplied to the subtracting circuit 89.

The output of the subtraction circuit 85 is supplied to the addition circuit 90. Adder circuit
The output of 90 is supplied to a subtraction circuit 89 and a delay circuit
The signal is fed back to the adding circuit 90 via 91. The output of the subtraction circuit 89 is taken out from the output terminal 92.

In the third and fourth examples shown in FIGS. 8 and 9, the signals multiplied by 2m and the signals not multiplied by 2m are added by the adders 56 and 66, respectively. The multiplication circuits 55 and 65 for performing the 2m multiplication are realized by bit shift circuits. Therefore, the word length of the signal obtained by multiplying 2 m by the multiplication circuits 55 and 65 is longer than the data bit of the input signal by the bit shift for multiplying the data bit of the input signal by 2 m. For example, if (m = 16), the coefficient 2m becomes 32, so that the data is shifted by 5 bits, and the data length is increased by 5 bits. Therefore, the addition circuit 56
, And 66, signals having different word lengths must be added, and the addition circuits 56 and 66 need to have word lengths corresponding to the number of data bits output from the multiplication circuits 55 and 65. For this reason, the hardware scale becomes large.

In the fifth example, the word lengths of the two added input data added by the adding circuit 87 are substantially equal, so that the hardware can be further simplified as compared with the configuration shown in FIG. 8 and FIG. Can be measured.

In the fifth example, the order of the filter is one step lower than that of the above-described examples of the filter. That is, in the example of the filter described above, the filter is configured based on the N-stage (2 m) averaging digital low-pass filter shown by the equation. From the averaging digital low-pass filter shown by this equation, 1
A digital high-pass filter composed of a low-order averaging digital low-pass filter will be considered.

From the equation, the transfer function H (Z) of the one-stage lower-order averaging digital low-pass filter is Indicated by When a high-pass filter is constructed from the above equation, its transfer function H (Z) becomes Becomes

If the group delay Z ^{(m- (1/2))} is considered to be excluded,
Z ^{(m- (1/2))} may not be realizable.

However, if an attempt is made to construct a digital high-pass filter based on the equation, the term (2mZ ^{− ((2m−1) / 2)} ) must be realized. However, since the delay of 1/2 sample cannot be performed, it cannot be realized as it is.

Therefore, in this embodiment, the following approximation is performed.

That is, from the average of the two samples before and after, the sample value of the signal that should be between them can be estimated. That is, mZ ^{− ((2m−1) / 2)} ≒ (mZ ^{− ((2m−2) / 2)} + mZ ^{− ((2m−0) / 2)} ) / 2.

From this, mZ− ^{(2m−1 / 2)} ≒ (mZ ^{− ((2m−2) / 2)} + mZ ^{− ((2m−g)} ) / 2} (mZ− ^(m−1) + mZ− ^m ) / 2 ...

Therefore, the term (2mZ ^{-((2m-1) / 2)} ) is (m
Z- ^(m-1) + mZ ^-m )).

In the fifth example, hardware is configured based on an equation. And based on the formula, 2mZ
^{The term-((2m-1) / 2)} is obtained. That is, the output of the connection point between the (m-1) sample delay circuit 82 and the one-sample delay circuit 83 is supplied to the multiplication circuit 86 of coefficient m, and the connection point between the one-sample delay circuit 83 and the m-sample delay circuit 84 The output is supplied to a multiplication circuit 86 having a coefficient m, and the output of the multiplication circuit 86 and the output of the multiplication circuit 88 are added by an addition circuit 87.

In such a case, the word lengths of the output of the multiplication circuit 86, which is the two addition inputs of the addition circuit 87, and the output of the multiplication circuit 88 are substantially equal. Therefore, the configuration of the adding circuit 87 can be simplified. That is, the word length of the adder circuit 87 is (the number of data bits + 1
Bit) is fine.

FIG. 11 shows a characteristic diagram in this case. In this example, (2m = 32). In FIG. 11, a solid line indicates an amplitude characteristic, and a broken line indicates a phase characteristic.

As can be seen from the characteristics shown in FIG. 11, in the case of such a configuration, although the high-frequency component disappears, it is not enough as a characteristic for detecting the middle-high-frequency component of the video signal in the autofocus circuit. is there.

b6. Sixth example of filter circuit FIG. 12 shows a sixth example of the filter circuit.
In FIG. 12, (m-1) sample delay circuits 102 and 1
The sample delay circuit 103 and the m sample delay circuit 104 are cascaded. The input digital signal from the input terminal 101 is supplied to the subtraction circuit 105, and is also supplied to the subtraction circuit 105 via the (m-1) sample delay circuit 102, the one-sample delay circuit 103, and the m-sample delay circuit 104.

(M-1) The output at the connection point between the sample delay circuit 102 and the one-sample delay circuit 103 is supplied to the adder circuit 107. 1
The output at the connection point between the sample delay circuit 103 and the m-sample delay circuit 104 is supplied to the addition circuit 107. The output of the addition circuit 107 is supplied to the multiplication circuit 106 for the coefficient m. Note that the coefficient m
Can be configured by a bit shift circuit. The output of the multiplication circuit 106 is supplied to the subtraction circuit 109.

The output of the subtraction circuit 105 is supplied to the addition circuit 110. The output of the addition circuit 110 is supplied to the subtraction circuit 109 and is fed back to the addition circuit 110 via the delay circuit 111. Subtraction circuit 10
The output of 9 is taken out from the output terminal 112.

In the sixth example, the multiplication circuits 86 and 88 of the coefficient m in the fifth example are reduced to one multiplication circuit 106 to reduce the hardware.

b7. Seventh Example of Filter Circuit FIG. 13 shows a seventh example of the filter circuit. In FIG. 13, an m-sample delay circuit 122, a one-sample delay circuit 123, and a (m-1) sample delay circuit 124 are cascaded. The input digital signal from the input terminal 121 is supplied to the subtraction circuit 125, and is also supplied to the subtraction circuit 125 via the m sample delay circuit 122, the one sample delay circuit 123, and the (m-1) sample delay circuit 124.

The output at the connection point between the m-sample delay circuit 122 and the one-sample delay circuit 123 is supplied to a multiplication circuit 126 for a coefficient m. The output of the multiplication circuit 126 for the coefficient m is supplied to the addition circuit 127.

The output at the connection point between the one-sample delay circuit 123 and the (m-1) -sample delay circuit 124 is supplied to the multiplication circuit 128 for the coefficient m. The output of the multiplication circuit 128 of the coefficient m is supplied to the addition circuit 127.

The output of the adder 127 is supplied to a one-sample delay circuit 133. The output of the one-sample delay circuit 133 is supplied to the subtraction circuit 129.

The output of the subtraction circuit 125 is supplied to a one-sample delay circuit 134. The output of the one-sample delay circuit 134 is supplied to the addition circuit 130. The output of the adder circuit 130 is a one-sample delay circuit 131
Is supplied to the subtraction circuit 129 via the
Returned to 30. The output of the subtraction circuit 129 is taken out from the output terminal 132.

This seventh example is different from the fifth example shown in FIG. 10 in that a register for latching the output of the adder circuit 90 and a delay circuit for delaying the output of the adder circuit 90 by one sample are provided by a common delay circuit.
131 simplifies the hardware.

b7. Seventh example of filter circuit FIG. 14 shows a seventh example of the filter circuit.
In FIG. 14, an m-sample delay circuit 142, a one-sample delay circuit 143, and a (m-1) sample delay circuit 144 are cascaded. The input digital signal from the input terminal 141 is supplied to the subtraction circuit 145, and is also supplied to the subtraction circuit 145 via the m sample delay circuit 142, the one sample delay circuit 143, and the (m-1) sample delay circuit 144.

The output at the connection point between the m-sample delay circuit 142 and the one-sample delay circuit 143 is supplied to the adder circuit 147. The output of the connection point between the one-sample delay circuit 143 and the (m-1) sample delay circuit 144 is supplied to the adder circuit 147. The output of the adding circuit 147 is supplied to the multiplying circuit 146 for the coefficient m. The output of the multiplication circuit 146 is supplied to the one-sample delay circuit 153. The output of the one-sample delay circuit 153 is supplied to a subtraction circuit 149.

The output of the subtraction circuit 145 is supplied to the one-sample delay circuit 161. The output of the one-sample delay circuit 161 is supplied to the addition circuit 150. The output of the adder 150 is a one-sample delay circuit 151
Supplied to The output of the one-sample delay circuit 151 is supplied to the subtraction circuit 149 and is fed back to the addition circuit 150. The output of the subtraction circuit 149 is taken out from the output terminal 152.

In the eighth example, the register for latching the output of the adder circuit 110 and the delay circuit for delaying the output of the adder circuit 110 by one sample in the sixth example shown in FIG. It is intended to simplify the wear.

c. Evaluation Value Characteristics in One Embodiment FIGS. 15A to 15C show a curve of evaluation value data of a conventional auto force circuit in which an evaluation value is obtained using an analog high-pass filter, and the present invention is applied. It is compared with the obtained evaluation value data curve.

FIG. 15A shows an evaluation value characteristic when a doll is set as a subject. In FIG. 15A, A1 shows a curve of evaluation value data in a conventional autofocus circuit, and A2 shows a curve of evaluation value data in an autofocus circuit to which the present invention is applied.

FIG. 15B shows the evaluation value characteristics when the subject is a screen in which the left side is black and the right side is white as shown in FIG. In FIG. 15B, B1 shows a curve of evaluation value data in the conventional autofocus circuit,
B2 shows a curve of evaluation value data in the autofocus circuit to which the present invention is applied.

FIG. 15C shows evaluation value characteristics when the screen of a Siemens star as shown in FIG. 17 is set as a subject. In FIG. 15C, C1 shows a curve of evaluation value data in the conventional autofocus circuit, and C2 shows a curve of evaluation value data in the autofocus circuit to which the present invention is applied.

As shown in FIGS. 15A to 15C, evaluation is performed by using a filter circuit that extracts a predetermined frequency component in the video signal and that includes a low-pass filter approximating a lens system blur function and a subtraction circuit. The slope of the curve of the value characteristic approaches a constant, and the curve of the ideal evaluation value data can be approximated.

〔The invention's effect〕

According to the present invention, as the filter circuit for extracting a predetermined frequency component in the video signal, a filter circuit including a lens system blur function approximation low-pass filter and a subtraction circuit is used. When such a filter circuit is used as a filter circuit for extracting a predetermined frequency component in a video signal, the curve of the evaluation value characteristic approaches the curve of the ideal evaluation value data. For this reason, the hill-climbing control becomes easy, and the in-focus position can be obtained over a wide range.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a graph used for explaining the embodiment of the present invention, FIG. 3 is a block diagram of an example of an averaging low-pass filter, and FIG. FIG. 5 is a block diagram of a first example of a filter circuit applicable to one embodiment of the present invention, and FIG. 6 is a block diagram of a filter circuit applicable to one embodiment of the present invention. FIG. 7 is a block diagram of a filter circuit applicable to one embodiment of the present invention, and FIG. 8 is a block diagram of a third example of a filter circuit applicable to one embodiment of the present invention. FIG. 9 is a block diagram of a fourth example of a filter circuit applicable to one embodiment of the present invention. FIG. 10 is a block diagram of a fifth example of a filter circuit applicable to one embodiment of the present invention. FIG. 11 shows a filter applicable to one embodiment of the present invention. FIG. 12 is a block diagram of a sixth embodiment of the filter circuit applicable to one embodiment of the present invention, and FIG. 13 is a filter diagram applicable to one embodiment of the present invention. FIG. 14 is a block diagram of a seventh embodiment of the circuit, FIG. 14 is a block diagram of an eighth embodiment of a filter circuit applicable to an embodiment of the present invention, and FIGS. 15A to 15C are embodiments of the present invention. Graph to explain the effect of
FIG. 17 and FIG. 17 are schematic diagrams used to describe a subject, FIG. 18 is a block diagram of an example of a conventional autofocus circuit, FIG.
FIG. 20 and FIG. 20 are graphs used for explaining a conventional autofocus circuit. Explanation of main symbols in the drawings: 6: filter circuit, 7: low-pass filter approximating lens system blur function, 8: subtraction circuit.

Claims (2)

(57) [Claims] An intermediate value component of a video signal is detected, an intermediate value component of the detected video signal is integrated, an evaluation value is obtained, and lens position control is performed using the evaluation value. In the autofocus circuit described above, the filter for detecting the middle and high frequency components in the video signal has a transfer function H (z) from the input signal. An autofocus circuit is configured to perform an output for subtracting an input signal that has passed through an averaging digital low-pass filter of N (N = 2m) stages represented by: 2. The method according to claim 1, wherein a middle-high band component in the video signal is detected, the middle-high band component in the detected video signal is integrated to obtain an evaluation value, and the position of the lens is controlled using the evaluation value. In the auto-focus circuit described above, a filter for detecting a middle-high frequency component in the video signal includes an m-sample delay circuit for delaying the input signal by m samples, and a first filter for multiplying the output of the m-sample delay circuit by (2m + 1).
A (2m + 1) sample delay circuit for delaying the input signal by (2m + 1) samples, a first subtraction circuit for subtracting the output of the (2m + 1) sample delay circuit from the input signal, and the first subtraction An addition circuit to which an output of the circuit is supplied; a one-sample delay circuit that delays the output of the addition circuit by one sample and feeds back to the addition circuit; and subtracts an output of the addition circuit from an output of the first multiplication circuit. An auto-focus circuit, comprising: a second subtraction circuit that performs a multiplication of an output of the second subtraction circuit by (1 / (2m + 1)).