JP2943776B2 - Information processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus, and more particularly to a processing function of an information processing apparatus that performs register renaming capable of executing instructions out of order.

In recent years, there has been a demand for further improvement in performance of information processing apparatuses, and in order to achieve higher performance, a high-speed system called “super scalar type” has been adopted.

In a superscalar type processor, a plurality of instructions are simultaneously decoded and instructions are issued. However, each instruction has a dependency on a processing result, and it is sufficient to control the instruction issuance while maintaining the dependency. Performance cannot be obtained. For this reason, in many superscalar-type processors, instruction issuance control that does not follow the order in which instructions appear, which is called “out-of-order issuance”, is performed.

In the out-of-order issuance control, the order of issue of instructions is changed. Therefore, when the result processed by each instruction is written in a general-purpose register or the like, the order of write may also be changed. In the example shown below, the instruction of (2) waits for the result of the division instruction of (1) to be written to the S0 register, so that the instruction of (3) is changed to the instruction of (2) by out-of-order issuance control. Although issued in advance, in this case, writing to the S3 register by the instruction (3) occurs prior to writing by the instruction (2).

S0 ← S1 / S2 (1) S3 ← S0 × S4 (2) S3 ← S5 × S6 (3)

Normally, since it is expected that the execution results in the order in which instructions appear are reflected, it is necessary to control the order of registers to be finally written. For this control, "Renaming" is an operation of changing the write register name to a number "tag" that is unique in the system.
To identify data dependencies.

As a technique for realizing these functions, score boarding, the Tomasulo algorithm, and the like are known. For example, in the literature (Hennessy and Patterson, "A Quantitative Approach to Computer Architecture Design, Implementation, and Evaluation," December 25, 1992,
Reference is made to Nikkei BP, pages 293-298).

The Tomasulo algorithm has a buffer called a "reservation station" in order to wait for indeterminate data of a preceding instruction in a functional block unit having a dependency.

As one method of controlling renaming, a result of a renamed register is not directly written to a general-purpose register, but is temporarily stored in a register called a “renaming register”. There is a control for writing the result when the execution order is guaranteed.

FIG. 3 shows an example of the configuration of the conventional system. FIG. 3 shows a general-purpose register 1 having four read and three write ports and a reservation station R as a conventional method.
In S18-1 / 18-2, a configuration is shown in which three instructions can be issued simultaneously and out-of-order issue between two operation instructions is possible. 3, 2 is a read address decoder, 4 is a write address decoder, 5 to 7 are write data registers,
11-1 to 11-3 are write address registers;
Reference numerals -1 to 12-4 denote a read data register, 13 denotes an address adder, 15 and 16 denote fixed-point / floating-point arithmetic units, and 17 denotes a cache unit.

As for the operand data of the instruction decoded by the instruction issuance control unit (not shown), the read address of the general-purpose register 1 is set in the read registers 9-1 to 9-4, and the read data registers 12-1 to 12-12 are read.
-4, and supplied to the address adder 13 and the fixed-point / floating-point arithmetic units 15 and 16. In this case, since the instructions are read from the general-purpose register SR1 in the decoding order, an instruction that cannot be issued occurs because the processing of the preceding instruction is not completed.

Instructions that cannot be issued are temporarily stored in the reservation stations RS18-1 / 18-2, and wait for determination of operands by preceding instructions. From the reservation stations 18-1 / 18-2, the arithmetic units 15/16 are sequentially ordered from the instruction whose operand data is determined.
Issued for

In this conventional system, since no reservation station is provided on the address adder 13 side, a memory access instruction using the address adder 13 cannot be issued out-of-order. For this reason, the operand decode is waited for in the instruction decode stage, so that the subsequent instruction cannot be issued, which causes a decrease in performance.

The result of processing is stored in the general-purpose register 1 through the write data registers 5, 6, and 7. However, if there is a write overtaking between instructions that depend on output, Control is performed to suppress the writing of the preceding instruction into the general-purpose register 1. Since the operation result may be referred to by a subsequent instruction, it has a register for each stage and a data replacement path for the reservation station.

[0015]

However, the above-mentioned conventional method has the following problems.

The first problem is that, as described above, it is necessary to incorporate a function for performing register renaming control. However, in a reservation station system or the like based on the Tomasulo algorithm, the reservation station is Structurally, it is difficult to realize a RAM (random access memory) configuration, and the layout tends to be dispersed.
This means that the amount of hardware tends to be large and the control becomes complicated.

The second problem is that in the superscalar system, a plurality of instructions are processed at the same time, so that a plurality of data must be read from a general-purpose register at the same time.
For this reason, the general-purpose register is composed of a RAM macro having a large number of read / write ports, and it is necessary to secure a path for replacing data from the renaming register and the like, and it is necessary to route an enormous data line. That's what it means.

Incidentally, in recent microprocessors, 4
In order to realize the simultaneous issuance of instructions or the like, it is configured with a memory having 10 or more ports, and chip design has become extremely difficult.

Therefore, the present invention has been made in view of the above-mentioned problems, and an object of the present invention is to enable register renaming control to be realized by a very simple control, and to realize a large number of replacement paths. Is performed in the RAM structure, and many wirings can be omitted.
It is an object of the present invention to provide an information processing apparatus that significantly improves an increase in delay.

[0020]

According to one aspect of the present invention, there is provided an information processing apparatus which performs register renaming and is capable of executing an instruction out of order. To store and retrieve
A word general-purpose register and an n-word renaming register for storing an execution result of an undetermined instruction executed by out-of-order issuance are each configured by a multi-port memory. A first read means for connecting the read bit lines of the memory cells of the renaming register to read word data at a position indicated by a first address decoder as a register of m + n words; A write bit line is separated from a write bit line of a memory cell of the renaming register, and first write means for writing to a general-purpose register at a word position indicated by a second address decoder; and a third address decoder. Renaming register for indicated word location It has a second writing means for writing, a.

In the present invention, the data written to the general-purpose register by the first writing means is the contents of the renaming register read by the first reading means.

[0022]

Embodiments of the present invention will be described. According to a preferred embodiment of the present invention, in an information processing apparatus capable of performing register renaming and executing instructions out-of-order, an m-word general-purpose register (FIG. 2) for storing and retrieving the result of instruction execution is provided. 1
-2) and an n-word renaming register (1-1 in FIG. 2) for storing the execution result of an undetermined instruction executed by out-of-order issuance are each configured by a multi-port memory, and a general register is read. The bit line and the read bit line of the renaming register are shared, and the means for reading as a register of m + n words and the write bit line of the general-purpose register and the write bit line of the renaming register are separated, and the processing result is temporarily stored in the renaming register. When writing to a general-purpose register, the contents of the renaming register read by the above-mentioned reading means are selectively latched (1-3 in FIG. 2) and stored in the general-purpose register (1-2 in FIG. 2). It is intended to be written.

According to the embodiment of the present invention, register renaming control can be realized by simple control. In addition, since many of the replacement paths are performed in the RAM structure and many wirings can be omitted, it is possible to greatly improve the layout, accommodation, and delay of the wiring.

[0024]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention;

FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention. Referring to FIG. 1, register 1 contains 1
This is a register file composed of two parts, a 28-word general-purpose register SR and a 64-word renaming register RR. Eight sets of read registers 9-1
To 9-8 are connected to the address decoder 2, respectively.
Register file 1 as 192 word decode output
Connected to. The four sets of RR (renaming register) write registers 10-1 to 10-4 are respectively connected to the address decoder 3, and are connected only to the renaming register RR as a 64-word decode output. 4
A set of SR (general purpose register) write registers 11-1 to 11-1
11-4 are connected to the address decoder 4, respectively.
General-purpose register SR as 128-word decode output
Connected only to Eight sets of read registers 9-1 to 9
The read results of the renaming register RR and the general-purpose register SR read from the position indicated by -8 are respectively eight sets of read data registers 12-1.
To 12-8.

Each of the read data registers 12-1 to 12-12
-8 is connected to address adders 13 and 14 and two sets of fixed point / floating point arithmetic units 15 and 16, and the address adders 13 and 14 are further connected to the cache unit 1.
7 is connected.

The cache unit 17 accesses the cache memory in the processor based on the address information in the main memory calculated by the address adders 13 and 14, and if a hit occurs, the contents of the cache at the specified position are read. If it is a mishit, data is fetched from the main memory.

The fixed point / floating point arithmetic unit 1
In steps 5 and 16, arithmetic processing specified by the instruction issuing unit is performed using the read register 12 as input data.

The results processed by the cache unit 17 and the fixed-point / floating-point arithmetic units 15 and 16 are stored in the write data registers 5, 6, 7 and 8, respectively.
And the RR write registers 10-1 to 10-4
Is written to the renaming register location specified by.

FIG. 2 shows the structure of the register file 1 including the general-purpose register SR and the renaming register RR in one embodiment of the present invention.

Referring to FIG. 2, register file 1
Is a 64-word renaming register 1-1 and 128
It comprises a word general register 1-2. Bit lines 101, 102, 103, 104, 10 of the read ports of the register file corresponding to the eight sets of read ports
5, 106, 107, and 108 are connected by a register R, and data is read as a 192 word register.

The write bit lines 109, 110, 111, and 112 for the renaming register 1-1 are connected to the write data registers 5, 6, 7, and 8, respectively, and the contents of the write data registers are designated by the RR write address decoder 3. Is written to the corresponding word position.

The read data of the renaming register 1-1 read via the signal lines 101 and 102 is selected and latched by the latch with selector 1-3, and the latched data is stored in the general-purpose register 1-2. Is written to the word position designated by the SR write address decoder 4 via the write bit line 113 for the write operation.

Similarly, the contents of the renaming register 1-1 are selected and latched by the latch with selector 1-4 via the signal lines 103 and 104, and written into the general-purpose register 1-2 via the signal line 114. . Similarly, the contents of the renaming register 1-1 are selected and latched by the latch with selector 1-5 via the signal lines 105 and 106, and are sent to the general-purpose register 1-2 via the signal line 115.
Selected by latches 1-6 with selectors through 7 and 108,
Latched, and the general-purpose register 1-
2 is written.

The operation of the embodiment of the present invention will be described in comparison with the conventional system shown in FIG.

As described above, in the conventional method described with reference to FIG. 3, since no reservation station is provided on the address adder side, a memory access instruction using the address adder cannot be issued out-of-order. Therefore, it is necessary to wait for the determination of the operand in the instruction decode stage, and the subsequent instruction cannot be issued, which is a factor of performance degradation. The processing result is stored in the general-purpose register via the write data registers 5, 6, and 7. However, if there is a write overtaking between the output-dependent instructions, the general-purpose register of the preceding instruction is output. Control is performed to suppress writing to the SR. Further, since the operation result may be referred to by a subsequent instruction, each stage has a register and a data replacement path for the reservation station.

On the other hand, in the embodiment of the present invention shown in FIG. 1, a register file capable of simultaneously reading eight operands and simultaneously writing four operands is provided in order to greatly improve the performance. In this configuration, four instructions can be issued simultaneously.

In this embodiment, an instruction issuance control unit (not shown) has a control unit (not shown) for reordering instruction issuance, instead of waiting for operands in the data path. Is performed for an instruction whose data has been or will be determined in the renaming register RR or the general-purpose register SR.

Each of the general-purpose register update instructions is assigned a "tag" information = a renaming register number which is unique in the system, and the processing result of each instruction is temporarily stored in a corresponding position of the renaming register. You.

The processing result stored in the renaming register RR is written to the general-purpose register SR when the processing of all preceding instructions is completed. That is, writing to the general-purpose register SR is made in-order.

Regarding reading of operand data,
An instruction whose writing to the general-purpose register SR has been completed is read from the general-purpose register SR, and an instruction whose preceding instruction has not been completed and has not been written to the general-purpose register SR is read from the renaming register RR.

When writing data from the renaming register RR to the general-purpose register SR, the path for reading out the renaming register RR is shared with the path for reading out RR / SR.

That is, the bit lines of the read data of the memories of the renaming register RR and the general-purpose register SR are common, and the data read by this bit line is temporarily stored between the renaming register RR and the general-purpose register SR. The latch is selectively latched by the implemented latch with selector, and the latch output data is written to the general-purpose register SR.

When the renaming register RR and the read bit line of the general-purpose register SR are shared, there is a concern that the reading of the RR / SR and the writing to the general-purpose register SR may compete with each other. Therefore, even if the writing to the general-purpose register SR is performed between reading operations, the performance is not significantly reduced.

In one embodiment of the present invention, the memory configuration of the RR / SR is such that the read side shares the bit lines, thereby doubling the number of bit lines and selecting the RR / SR read data. Or need to be done.

Further, in one embodiment of the present invention, by making the number of write ports uniform, the width of RR / SR is uniform, the accommodating property is improved, and the chip layout is facilitated.

[0047]

As described above, according to the present invention,
The effect is that the layout is easy and the accommodation is greatly improved. The reason is as follows.

In the reservation station configuration and the like,
This is a configuration in which a plurality of buffers and a plurality of data paths are mixed, resulting in an irregular layout. However, according to the present invention, many data paths can be regularly accommodated in the register file block. .

Further, according to the present invention, since each block can be connected with a compact and short wiring, it is expected that the delay time is improved.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a register file (RR / SR) in one embodiment of the present invention.

FIG. 3 is a diagram showing an example of a configuration of a conventional system.

[Explanation of symbols]

 1 Register File 1-1 Renaming Register 1-2 General-purpose Register 1-3-1-6 Latch with Selector 2 Read Address Decoder 3-4 Write Address Decoder 5-8 Write Data Register 9-1-9-8 Read Address Registers 10-1 to 10-4 Write address registers 11-1 to 11-4 Write address registers 12-1 to 12-8 Read data registers 13, 14 Address adders 15, 16 Fixed point / floating point arithmetic unit 17 Cache unit 18 −1 / 18-2 Reservation Station

Continuation of the front page (56) References Michael D. Smith, 2 others, "Boosting Beyond Static Scheduling in a Superscalar Processor", Proceedings of the 17th Annual Symposium on Computer Architecture, 1990 (May. 1990, 1990). 344-354 (58) Field surveyed (Int.Cl. ⁶ , DB name) G06F 9/38 G06F 9/30 G06F 9/34

Claims (3)

(57) [Claims] 1. An information processing apparatus capable of executing register register renaming and executing instructions out-of-order, comprising: a general-purpose register of m words for storing and retrieving the result of instruction execution; An n-word renaming register for storing the execution result of the determined undetermined instruction is configured by a multi-port memory, and a read bit line of a memory cell of the general-purpose register;
First read means for combining the read bit line of the memory cell of the renaming register and reading word data at a position indicated by a first address decoder as a register of m + n words; and a memory cell of the general-purpose register A write bit line,
A first write unit that separates a write bit line of a memory cell of the renaming register and writes the general-purpose register at a word position indicated by a second address decoder; and a word indicated by a third address decoder. An information processing apparatus, comprising: second writing means for writing to a position renaming register. 2. The data writing device according to claim 1, wherein the data written to said general-purpose register by said first writing means is the contents of said renaming register read by said first reading means. Information processing device. 3. An information processing apparatus capable of performing register renaming and executing instructions out-of-order, comprising: a general-purpose register for storing and retrieving a result of the instruction execution; The renaming registers for storing the execution result of the determined instruction are each configured by a multi-port memory, the read port of the general-purpose register and the read port of the renaming register are shared, and the write port of the general-purpose register and the renaming register are separated. An information processing apparatus configured to select and latch read data of the content written in the renaming register and write the read data to the general-purpose register.