JP2940803B2 - Solid-state imaging device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame transfer type solid-state imaging device.

[0002]

2. Description of the Related Art A CCD solid-state image pickup device used in a video camera or the like is constituted by a combination of a light receiving pixel for generating information charges upon receiving a subject image and a CCD shift register for sequentially transferring the information charges generated in the light receiving pixels. Be composed. In the CCD shift register, a plurality of transfer electrodes for transferring information charges by controlling a potential in the channel region are arranged on a channel region surrounded by the separation region. The plurality of transfer electrodes have a two-layer structure in which adjacent transfer electrodes overlap each other in consideration of the transfer efficiency of information charges. That is, the potential in the channel region can be controlled without interruption by covering the space between the first-layer transfer electrodes arranged at regular intervals with the second-layer transfer electrode.

FIG. 4 is a plan view schematically showing a frame transfer type CCD solid-state imaging device. The imaging section 1 is composed of a plurality of CCD shift registers that are continuous in the vertical direction, accumulates information charges generated in response to incident light in each bit during a light receiving period, and stores the information charges in a frame transfer clock φF during a transfer period. Transfer output according to The storage unit 2 is composed of a CCD shift register that is continuous with the shift register of the imaging unit 1, receives the vertical transfer clock φV, captures and stores information charges output from the imaging unit 1 during a transfer period.
The horizontal transfer unit 3 is composed of one row of CCD shift registers that are continuous in the horizontal direction, receives the output of the shift register of the storage unit 2 for each bit, and outputs information charges in units of horizontal lines according to the horizontal transfer clock φH. The output unit 4 includes a capacitor for converting a charge amount into a voltage value and an amplifier for extracting a potential change of the capacitance, and sequentially converts information charges output from the horizontal transfer unit 4 into a voltage value in 1-bit units, and outputs a video signal. Output as

In such a CCD solid-state image pickup device of the frame transfer system, an image pickup section which receives light from a subject accumulates information charges and simultaneously transfers and outputs the information charges accumulated during a predetermined period to the storage section. It has become.
For this reason, a transfer electrode for transferring and driving information charges is also provided in the light receiving region of the light, and a power supply wiring for supplying a drive clock to the transfer electrode is arranged in a peripheral portion of the light receiving region.

FIG. 5 is a plan view showing the structure of an image pickup section 1 of a frame transfer type CCD solid-state image pickup device, and FIG. 6 is a sectional view taken along line XX of FIG. In a surface region of a semiconductor substrate 10 made of P-type single crystal silicon, a plurality of isolation regions 11 in which P-type impurities are implanted at a high concentration are formed in parallel with each other so as to extend in one direction. These separation areas 11
The channel region 12 is defined by the above, and a light receiving region is formed. The channel region 12 has a buried channel structure in which an N-type diffusion layer 13 is formed on the surface side of the semiconductor substrate 10. Semiconductor substrate 1 surrounding light receiving area
An isolation region 14 in which P-type impurities are implanted at a high concentration is also formed in the peripheral portion of 0. These separation regions 11, 1
Silicon substrate 10 on which channel region 4 and channel region 12 are formed
A plurality of first-layer transfer electrodes 16a made of polycrystalline silicon intersect with the channel region 12 via the insulating film 15 and extend across the light-receiving region to the peripheral isolation region 14 above. Be placed. On these transfer electrodes 16a, a second-layer transfer electrode 1 also made of polycrystalline silicon is formed.
6b is arranged to cover the gap between the transfer electrodes 16a. Thus, transfer electrodes 16a and 16b having a two-layer structure are formed. Then, in the peripheral portion of the light receiving region, aluminum wirings 18a and 18b are arranged on transfer electrodes 16a and 16b via insulating film 17, and each transfer electrode 16a is provided through contact hole 19 provided in insulating film 17, respectively.
a, 16b. This aluminum wiring 18
a and 18b are provided corresponding to the number of phases of the transfer clock supplied to the transfer electrodes 16a and 16b.
When the transfer electrodes 16a and 16b are driven in four phases, four transfer electrodes are arranged. Therefore, a multi-phase driving clock is applied to each of the transfer electrodes 16a and 16b via the aluminum wirings 18a and 18b, and information charges are unidirectionally driven by the action of the potential in the channel region 12 which changes in response to the driving clock. Are sequentially transferred to

[0006]

In the solid-state image pickup device of the frame transfer system, a fixed voltage is applied to the transfer electrodes 16a and 16b so that the channel region itself of the CCD shift register functions as a light receiving pixel. For example, the four-phase drive clock φ1 is applied to the transfer electrodes 16a and 16b.
When driving by applying ~ φ4, two or three of these
One of them is fixed at a high level to form a potential well in the channel region 12 for a predetermined period, and information charges generated by photoelectric conversion are stored in the potential well. Therefore, the size of the light receiving pixel is determined by the width of the channel region 12 and the width of the transfer electrodes 16a and 16b.

In the case of the solid-state imaging device described above, it is difficult to form the first-layer transfer electrode 16a and the second-layer transfer electrode 16b so as to have the same electrical characteristics. For this reason, if the number of phases of the drive clock is set to an odd number, the characteristics of the light receiving pixels in the odd-numbered rows and the even-numbered rows become inconsistent, causing a problem that the distortion of the video signal is increased. Therefore, the number of phases of the driving clock of the solid-state imaging device is reduced by the transfer electrodes 16a, 16
b, the degree of freedom in designing the solid-state imaging device is reduced. For this reason, the solid-state imaging device must be designed for each application, which is a factor that increases the manufacturing cost of the solid-state imaging device. In particular, at present, when it is desired to expand the range of use of an imaging device corresponding to multimedia, it is necessary to operate a solid-state imaging device under various conditions, and a solid-state imaging device capable of coping with such a situation has arisen. One of the important issues is to reduce the manufacturing cost of the solid-state imaging device.

Accordingly, it is an object of the present invention to eliminate the restriction on the number of phases of the driving clock, expand the range of use of the solid-state imaging device, and reduce the manufacturing cost of the solid-state imaging device.

[0009]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and is characterized by a semiconductor substrate and a plurality of separation regions in a surface region of the semiconductor substrate. A plurality of channel regions that are partitioned and extend in one direction and are arranged in parallel with each other, and intersect the plurality of channel regions and extend to a peripheral portion of the channel region to form a certain gap on the semiconductor substrate. A plurality of transfer electrodes that are arranged in the same layer with a distance therebetween, form potential barriers at regular intervals in the plurality of channel regions, and electrically form a plurality of light receiving pixels, and the plurality of transfer electrodes around the channel region. A plurality of power supply wirings arranged to intersect the transfer electrodes and selectively apply a given multi-phase drive clock to the plurality of transfer electrodes; and the plurality of transfer electrodes and the plurality of powers. Lies in the arbitrarily settable the connection position of the feed line corresponding to the number of phases of the desired driving clock.

[0010]

According to the present invention, since a plurality of transfer electrodes are formed in the same layer, the electrical characteristics of each transfer electrode become uniform, and the number of phases of the drive clock applied to each transfer electrode can be freely selected. become able to. By determining the number of phases of the drive clock by selecting the connection position of each transfer electrode with respect to the plurality of power supply wirings, the number of phases of the drive clock can be freely selected without changing the structure of the transfer electrode.

[0011]

FIG. 1 is a plan view showing the structure of an image pickup section of a solid-state image pickup device according to the present invention, and FIG. 2 is a sectional view taken along the line Y--Y. In the surface region of the semiconductor substrate 20 made of P-type single crystal silicon, a plurality of isolation regions 21 made of P-type regions are formed in parallel with each other, and a channel region 22 is defined by these isolation regions 21. The separation region 21 and the channel region 22 are the same as those of the solid-state imaging device in FIG. 5, and the separation region 21 and the channel region 22 constitute a light receiving region. In addition, the channel region 22
An N-type diffusion layer 23 is formed on the front side of the semiconductor substrate 20 to form a buried channel structure.

In the peripheral portion of the semiconductor substrate 20, an isolation region 24 formed of a P-type region is formed so as to surround the light receiving region. On the silicon substrate 20 on which the isolation regions 21 and 24 and the channel region 22 are formed, a plurality of transfer electrodes 26 made of polycrystalline silicon intersect the channel region 22 via the insulating film 25 and cross the light receiving region. It is arranged to extend over the isolation region 24 in the peripheral part. This transfer electrode 2
6 is formed wider at the center of the channel region 22 than on the isolation region 21. As a result, the gap between the transfer electrodes 26 is narrowed at the center of the channel region 22 to maintain the transfer efficiency of information charges, and is widened on both sides of the channel region 12 to ensure the efficiency of light incidence on the channel region 22. Is done. By setting the gap between the transfer electrodes 26 to 0.5 μm or less, continuity of potential control can be maintained. In order to prevent the transfer efficiency of information charges from lowering, in addition to making the gap between the transfer electrodes 26 smaller, the channel region 22 is formed in the channel region 22 in the gap portion.
By implanting impurity ions of the opposite conductivity type, the potential gap at the gap may be eliminated. That is, when P-type impurity ions are implanted into the gaps between the transfer electrodes 26, the N-type impurity concentration in the channel region 22 decreases, and the potential is formed shallower.
Impurity ions are implanted so that a potential dent or protrusion does not occur in the gap between the transfer electrodes 26.

On the separation region 24 in the peripheral portion, for example,
Four aluminum wirings 28 a to 28 d are arranged via insulating film 27 so as to overlap the end of transfer electrode 26. Each of these aluminum wirings 28a to 28d has
A maximum of four-phase drive clocks φ1 to φ4 are applied. When the transfer electrode 26 is driven by the three-phase drive clocks φ1 to φ3, three of the four aluminum wires 28a to 28d
Contact holes are formed between the aluminum wirings 28a to 28c and the transfer electrodes 26, and each transfer electrode 2
6 is connected. Then, the aluminum wirings 28a-2
8c, a three-phase drive clock φ1 is applied to each transfer electrode 26.
~ Φ3 is applied. At this time, since each transfer electrode 26 is formed in the same layer, all of the transfer electrodes 26 have the same electrical characteristics, and the light receiving pixels have the same characteristics in each row with respect to the three-phase drive clocks φ1 to φ3. Become. Also, the transfer electrode 26
The aluminum wiring 28d not connected to the semiconductor substrate 1 is electrically connected to the input / output pads provided on the semiconductor substrate 1, but the input / output pads are not connected to a well-known lead frame on which the semiconductor substrate 1 is mounted. To do. This prevents an increase in the number of input / output pins of the solid-state imaging device.

Therefore, during the light receiving period, each channel region 2
One light receiving pixel is formed for each of the three transfer electrodes 26 in 2, and information charges are accumulated in the light receiving pixels. In the transfer period after the elapse of the predetermined light receiving period, the channel region 22 that changes in response to the three-phase drive clocks φ1 to φ3.
, The information charges accumulated in each light receiving pixel are sequentially transferred and output along the channel region.

When the transfer electrode 26 is to be driven by the four-phase driving clocks φ1 to φ4, contact holes are formed between the four aluminum wirings 28a to 28d and the transfer electrode 26, respectively. What should I do? That is, without changing the structure of the transfer electrode 26,
Transfer electrode 26 for aluminum wirings 28a to 28d
If only the connection position is changed, the number of phases of the drive clock applied to the transfer electrode 26 can be changed from three to four. Therefore, in the manufacture of two (or three or more) types of solid-state imaging devices, all can be common except for the step of forming contact holes for connection between each transfer electrode 26 and the aluminum wirings 28a to 28d. In addition, the manufacturing cost can be reduced.

As described above, if the number of phases of the drive clock of the solid-state imaging device can be easily changed, the transfer electrodes 26
, The vertical width of the light receiving pixel determined by the width of the light receiving pixel can be easily changed. For example, as shown in FIG. 3, four transfer electrodes 26 have a width of one pixel in four-phase driving, whereas three transfer electrodes 26 have one width in three-phase driving.
It is the width of the pixel. Therefore, by changing the number of driving phases from four to three, the width of the light receiving pixels can be reduced to ／. This makes it possible to change the vertical arrangement pitch and the horizontal arrangement pitch of the light receiving pixels, that is, the so-called aspect ratio.

In the above embodiment, the case where four aluminum wirings 28a to 28d are arranged and three-phase driving clocks φ1 to φ3 are used is exemplified. However, five or more aluminum wirings 28a to 28d are formed, The drive clock can be four or more phases. However, if the number of aluminum wirings is increased, the area of the semiconductor substrate 1 is increased. For normal use, the number of phases of the drive clock is 3 to 5
It is within the range of phases, and about 5 aluminum wirings are optimal.

[0018]

According to the present invention, the number of phases of the drive clock can be easily changed without changing the structure of the transfer electrode. For this reason, various restrictions on the electrode structure and the number of driving phases are relaxed, the degree of freedom in designing the solid-state imaging device is expanded, the usage range of the solid-state imaging device is widened, and the manufacturing cost of the solid-state imaging device can be reduced. it can.

[Brief description of the drawings]

FIG. 1 is a plan view illustrating a structure of an imaging unit of a solid-state imaging device according to the present invention.

FIG. 2 is a sectional view showing a section taken along line YY of FIG. 1;

FIG. 3 is a cross-sectional view showing a state of a potential in a channel region of the solid-state imaging device of the present invention.

FIG. 4 is a schematic plan view of a frame transfer type CCD solid-state imaging device.

FIG. 5 is a plan view showing an imaging unit of a conventional solid-state imaging device.

FIG. 6 is a sectional view showing a section taken along line XX of FIG. 5;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Image pick-up part 2 Storage part 3 Horizontal transfer part 4 Output part 10, 20 Silicon substrate 11, 14, 21, 24 Separation area 12, 22 Channel area 13, 23 Diffusion layer 15, 17, 25, 27 Insulating film 16a, 16b, 26 Transfer electrode 18a, 18b, 28a-28d Aluminum wiring 19, 29 Contact hole

Claims (3)

(57) [Claims] 1. A semiconductor substrate, which is divided by a plurality of isolation regions in a surface region of the semiconductor substrate and extends in one direction,
A plurality of channel regions which are arranged parallel to one another, with crossing the plurality of channel regions, the plurality of channels
Extending to the peripheral portion of the light receiving region where the pixel region is disposed , disposed on the same layer with a certain gap on the semiconductor substrate,
A plurality of transfer electrodes that form potential barriers at regular intervals in the plurality of channel regions to electrically form a plurality of light receiving pixels, and are disposed in a peripheral portion of the light receiving region so as to intersect with the plurality of transfer electrodes; is, the driving clock of the given multi-phase and a plurality of power supply lines for selectively applying to the plurality of transfer electrodes, and select the connection position between the plurality of transfer electrodes and the plurality of power supply lines Drive clock phase
A solid-state imaging device characterized by determining the. 2. The plurality of transfer electrodes are formed to be wider on a central portion of the plurality of channel regions than on the plurality of separation regions, and to have a narrow gap between adjacent transfer electrodes. The solid-state imaging device according to claim 1, wherein 3. The solid-state imaging device according to claim 1, wherein an impurity injection layer for controlling a potential level is formed in the channel region at a gap between the plurality of transfer electrodes.