JP2937380B2 - Wiring forming method and apparatus - Google Patents

Description

Description: BACKGROUND OF THE INVENTION The present invention relates to a method and an apparatus for forming a wiring, and in particular, to a method for forming a linear wiring on an insulating film on a substrate without applying, exposing and developing an organic photosensitive material. The present invention relates to a wiring forming method suitable for forming a pattern and a wiring forming apparatus for implementing the method.

[Conventional technology]

Due to the mass production effects of semiconductors, the unit price per chip is decreasing year by year and the functionality is increasing, and the equipment equipped with semiconductors is expanding to products that did not use semiconductors, such as automobiles and air conditioners. . In particular, facsimile machines, cameras, OA equipment, etc. have become markets that cannot survive unless their own one-chip microcomputers are installed to increase the added value of their products.
The demand for ated circuits (hereinafter referred to as ASICs) is steadily expanding. ASICs can be broadly divided into two types depending on the specific application. In other words, custom ICs and application specific standard products (ASSPs)
Is written). A custom IC is an IC made by an LSI maker according to a user's order, and an ASSP is a kind of general-purpose product that the LSI maker plans and designs for a large number of users in a specific field. Therefore, the latter is the number of production
In contrast to the production of small varieties of about one million, the former requires users to produce multiple varieties with a production volume of less than 100,000. Furthermore, it is expected that the diversification of products will progress year by year, and the demand for multi-product production in smaller quantities will increase.

However, the wiring forming method conventionally used in the production of ASICs is exactly the same as that of LSIs for mass production, ie, memories such as DRAMs and SRAMs, general-purpose microcomputers, CPUs, and the like. That is, as shown in the process flow diagram shown in FIG. 2, Al sputter deposition → organic photosensitive material (hereinafter referred to as “resist”) application and baking → exposure →
The wiring was formed through a multi-step process of development → Al film etching → resist removal.

With respect to the above prior art, there has been reported a method of drawing wiring directly on an insulating film using a focused laser beam, which does not require an exposure mask as well as a resist. In this method, the surface of an insulating film is heated by condensed laser light, and Cr (CO) ₄ , W (CO) ₆ , Mo (C
O) _6, TiCl _4, triisobutyl aluminum Nam [Triisobutyl
-Aluminum, TIBA], bis (1,1,1,5,5,5hexafluoro-2,4-pentanedionate) copper (II) [bis- (1,1,
1,5,5,5-hexafluoro-2,4-pentanedionate) copper
(II)] etc. as raw materials, respectively, Cr film, W film, Mo film,
A Ti film, an Al film, and a Cu film are formed.

References described so far regarding direct writing of metal by a laser beam include Applied Physics Letters, Vol. 45 (1984), pp. 617 to 619 [Ap.
pl.phys. Lett., 45 , 617-619 (1984)] and Applied Physics Letters, Vol. 46 (1985), pp. 204-206 [Appl. Phys. Lett., 46 , 204-206 ( 1985)]
And the like.

Next, selective CVD of metal is described as one process used in the wiring forming method of the present invention, which is not directly related to the conventional wiring forming method. This method was originally designed for LSI
This technology has been developed to improve metal embedding in connection holes (contact holes or through holes) provided for connecting upper and lower wiring to the interlayer insulating film that has become apparent with the high integration of semiconductors. In particular, W selective CVD is the most expected method for practical use.

In the selective CVD of W, the insulating film (SiO
₂ etc.) On a sample where the surface and Si or metal surface are mixed,
A mixed gas of tungsten hexafluoride (WF ₆ ) gas and hydrogen (H ₂ ) gas is introduced and brought into contact with the substrate Si or a metal (here, the case of Si is shown) by one of the following reactions. This is a method for growing a W film.

_On the insulating film such as SiO _2, the reaction of (1) does not occur, and the reaction of (2) does not proceed at a temperature of 700 ° C. or less. In the above, selective filling is achieved.

References described so far regarding the selective CVD of W include the Journal of Electrochemical Society, Vol. 131 (1984), pp. 1427 to 1433 [JE
131 , 1984, pp. 1427-1433] and Proceedings of VSI Multilevel Interconnection Conference, June 1987, pp. 132-137 [Proc. of VLSI Multilevel
Interconnection Conference, June 1987, pp132-137)
And the like.

Recently, a method of using a SiH ₄ -based gas instead of H ₂ as a reducing gas has been reported. For example, this method is described in the ECS Japan Chapter 1st Symposium (1988), “Cross-Technology for Super LSI7” Preprints, pp. 48-65. By using this method, high-speed film formation can be performed at a low substrate heating temperature of 250 to 320 ° C. In addition, in the case of this method, the selectivity is lost at 340 ° C. or higher, and it is not possible to selectively fill the holes.

[Problems to be solved by the invention]

Conventional wiring technology using the above resist is excellent in terms of high integration, miniaturization, and improvement in throughput when mass-producing the same product, but for users who require small-lot multi-product production, The conventional wiring forming method with a large number of processes is too costly, so that there is a problem that an LSI maker can only receive orders for products with a certain production number or more.

On the other hand, as described above, a technique of drawing metal wiring directly on an insulating film without using a resistor by a focused laser beam has also been reported.However, in this method, only a laser beam spot is formed. Since a metal film cannot be formed, it takes an enormous amount of time to scan the entire wiring pattern with a laser beam. Therefore, with this technology
It is practically impossible to form the wiring of the LSI itself, and this wiring technology is currently used only in a local area when viewed from the whole wiring such as wiring correction and white point correction of a mask. In order to use it for wiring formation, it is necessary to consider not only the reduction in the number of steps in wiring formation but also the throughput of wiring formation itself, but the above method does not take this point into consideration.

An object of the present invention is to provide a good wiring formation throughput,
It is another object of the present invention to provide a wiring forming method capable of reducing the number of steps in forming a wiring and supporting an IC manufactured in a small number of products.

[Means for solving the problem]

In order to achieve the above-mentioned object, the present invention provides a specific measure for reducing the number of steps in forming a wiring as a method of applying a resist.
This eliminates the processes of exposure / development and etching of the metal film, and forms a metal wiring pattern directly on the insulating film. In addition, the present invention is a drastic improvement in the metal film formation speed as compared with the conventional wiring forming method using a direct drawing of a wiring by a laser beam without using a resist and a mask.

That is, in the present invention, in order to achieve the above object, in a method of forming a wiring pattern directly on an insulating film on a substrate, (i) an active layer corresponding to a desired wiring pattern on a surface of the insulating film on the substrate; (Ii) Selective metal CVD Two processes of CVD are sequentially performed.

In the above processing, as for the formation of the active layer on the insulating film in (i), a method of scanning an electron beam focused on the surface of the insulating film can be used. Further, before the electron beam is scanned, the surface of the insulating film is subjected to a surface treatment with a halogen gas plasma in advance, so that the sensitivity of forming the active layer with respect to the electron beam can be improved.

As for the formation of the active layer (i), a method of scanning an ion beam focused on the surface of the insulating film can also be used.

In the above-described method using an electron or ion beam, at the current beam current density level, the scanning speed is almost equal to or slightly lower than the scanning speed required for exposure when a normal electron beam exposure resist is used. The time required for forming the active layer varies depending on the desired wiring pattern and the size of the target wafer, but is usually several tens of minutes to several hours per wafer. Therefore, the total time required for forming the active layer per wafer and the time required for forming the metal film by selective CVD of metal (usually several minutes) is equal to the time required for forming the wiring by direct metal writing with a laser beam. It is several orders of magnitude smaller than that, and is in a range that can be practically used as a wiring formation method for a small number of chips. In the future, if an electron beam or ion beam apparatus having a current density higher than the current value is developed, the time required for forming the wiring can be further reduced.

Further, as a method for forming an active layer on the surface of the insulating film in the above (i), after the surface of the insulating film is surface-treated with halogen plasma, light is irradiated in an exposure apparatus, and only the portion irradiated with the light is subjected to a photochemical reaction. It is also possible to use an activation method. This method requires a mask (referred to as a reticle in a commonly used reduced projection type exposure apparatus), as compared with the method using beam scanning described above, as in the case of using an ordinary resist for ultraviolet exposure. However, this is a drawback, but the time required for forming the active layer per wafer is about several minutes, and the throughput is greatly improved as compared with the beam scanning method. Therefore, it is considered that it is preferable to use the method as a wiring forming method for a case where the number of production chips is larger than that of an IC produced by forming an active layer by the electron beam or the ion beam. As is clear from the comparison between FIGS. 1 and 2 showing the wiring formation process of the present invention and the prior art, respectively, this method has a large number of wiring formation steps compared to the conventional process using a resist. Can be reduced. However, as long as the wiring step by selective CVD of the metal used in the present invention is performed, including the case of using any active layer forming method such as electron beam, ion beam, etc., LSI for high integration and miniaturization is required. Not suitable. This is because the film grows not only in the vertical direction but also in the horizontal direction as shown in FIGS. 1 (c) and 1 (d) during the selective CVD of the metal. This is because the wiring width also increases at the same time.

Next, regarding the metal selective CVD treatment of the above (ii),
Most commonly known tungsten W selection CV
D, that is, set up a CVD reactor for the selective CVD, it used one step CVD method to flow onto a heated substrate a mixed gas of a reducing gas such as WF ₆ and H ₂ or SiH _4, or, WF ₆ Using a two-stage CVD method, which flows alone or a gas diluted with an inert gas such as Ar onto the substrate, and then flows WF ₆ and the reducing gas onto the heated substrate,
Alternatively, it is achieved by using a two-stage or more CVD method in which WF ₆ and H ₂ are passed, and then WF ₆ and another reducing gas are passed.
As the reducing gas, H ₂ , SiH ₄ , Si ₂ H ₆ , BH ₃ , PH ₃ or the like can be used alone or in combination.

In the above description, the most common WF ₆ is
Although the method for forming the film has been described, it is also possible to form W film by heating and vaporizing WCl ₆ or WCl ₅ having a low vapor pressure at room temperature and using this as a source gas.
Further, MoF ₆ , MoCl ₆ , and MoCl ₅ can also form a Mo film in the same manner as described above. In addition, in the case of surface-reaction-controlled CVD, differences in the surface reaction occur due to differences in the surface state.Thus, by selecting the type of metal compound gas, it is possible to selectively form Ti, Al, Cu, etc. Needless to say.

In the plasma processing apparatus for halogen gas used in the present invention, high-frequency (preferably 10 kHz
Above) to generate plasma. However, when plasma is generated, it sputters the processing chamber walls and the like, and if metal contaminants adhere to the wafer, W is grown with the nucleus in subsequent W CVD processing. May lead to a decrease in sex. Therefore, the plasma processing apparatus employs a so-called cathode coupling method in which the substrate is negatively charged when a high frequency is applied to the electrode via the blocking capacitor, and the portion that becomes a metal contamination source in proximity to the substrate surface is quartz. It is important to make the structure covered with a plate in order to exert the effect of the present invention.

[Action]

Of the above configurations, the formation of the active layer on the insulating film surface
Normally, the surface that is not formed by metal selective CVD has a higher Si or metal element content compared to the chemical composition of the insulating film surface in the area where there is no other active layer. Has the effect of allowing formation.

The inventors of the present application have confirmed the effect of the formation of the active layer on the insulating film surface by the following experimental data. That is, a sample was prepared by forming a film of about 200 ° W on a Si wafer having a natural oxide film on the surface by selective CVD of W using WF ₆ and H ₂ as raw materials, and the interface of this sample was measured by Auger electron spectroscopy ( Auger Electron Spectroscopy, hereinafter AES)
A depth direction analysis was performed by the apparatus. FIG. 11 (a) shows the 3k
FIG. 5 shows a profile in the depth direction of AES analyzed for the sample using an electron beam for excitation of V, 1.2 μA, wherein the horizontal axis indicates sputtering time, and the vertical axis indicates Auger electron intensity of each element. From this figure, it can be seen that F and O
Can be seen as existing as interface residual impurities.
In addition, the same voltage and current were applied to the same sample (three samples of 125 mm diameter wafer with a central part of about 7 mm square and analysis position within 1 cm). FIGS. 11 (b) and 11 (c) show the results of AES depth direction analysis performed in the same manner as described above using an electron beam whose irradiation area was changed (ie, irradiation current density was changed). . From these figures, it can be seen that by increasing the irradiation current density, the F and O detection sensitivity,
In particular, it can be seen that the detection sensitivity of F is significantly lower than that of W or Si. In the above experiment, the measurement order of these elements was performed in the order of F → O → C → Si → W. For example, the measurement order of the elements was reversed, for example, W → Si → C → O → F. Then, even at the irradiation current density in the case of FIG. 11A, F was not detected at all as shown in FIG. 11C, and the sensitivity of O was relatively lower than that of Si.

The above phenomenon is considered to be due to F and O detached from the surface during the irradiation of the electron beam used for the measurement. In such an example, it is also known that when the surface of CaF ₂ as an insulator is irradiated with an electron beam, F atoms are desorbed at a rate of about one F atom per irradiated electron. In other words, it indicates that the irradiation of electrons has the effect of increasing the content of Si or a metal element on the surface of that portion as compared with the surface of other portions without electron irradiation.
Further, even if the surface is an oxide, the active layer is formed by the desorption of O by the irradiation of the electron beam as described above, but the surface is treated with a gas plasma containing F to form an active layer on the surface of the insulating film. By terminating the above, it becomes possible to form the active layer on the surface more efficiently for the above-mentioned reason. Here, as the gas of the gas plasma, F
However, the same effect can be obtained with another halogen gas (for example, Cl-based). That is, performing the surface treatment of the insulating film with the halogen gas plasma before irradiating the electron beam has an effect of increasing the sensitivity to the electron beam irradiation in forming the active layer on the insulating film surface. .

Further, in the above-described example, the energy of electron irradiation is applied to the surface of the insulating film. However, for example, when the insulating film is SiO ₂ , the absorption wavelength becomes a short wavelength ultraviolet light of 200 nm or less,
Since ultraviolet light that has been used for conventional resist exposure does not absorb the surface, it is necessary to perform surface treatment with halogen gas plasma to form a halogen element adsorption layer on the insulating film surface to absorb ultraviolet light. is there.

Generally, when an atom or molecule is adsorbed on a solid surface,
In particular, when chemisorption is strong against interaction, a new energy level is generated between the surface and the adsorbed species, which affects the electronic valence band of the substrate. Such an adsorbed species interacting with the underlayer naturally affects its own electronic structure. For example,
Isolated molecule of dimethyl cadmium (CH ₃ ) ₂ Cd (gas state)
Comparing the absorption spectrum with the absorption spectrum after adsorption, a peak is observed at about 215 nm in the absorption spectrum of the molecule itself, and light absorption is hardly observed at a long wavelength of 300 nm or more. In contrast, that of the adsorbed species shows light absorption even at 600 nm. Thus, when a molecule is adsorbed, its absorption generally shifts to longer wavelengths. Therefore, in the above case, only the adsorbed species can be selectively reacted by irradiating the surface of the substrate with an argon ion laser (514.5 nm) that does not absorb in the gas phase. When the surface adsorbed species is irradiated with light, the excitation process may be electronic excitation and vibrational excitation, and the reaction may be desorption or decomposition of the adsorbed species.

As described above, the surface treatment with the halogen gas plasma on the insulating film in the present invention has an effect of enabling light to be absorbed even in a wavelength region not originally absorbed by the insulating film, and thereafter, irradiation of ultraviolet light is performed. Has the effect of exciting and desorbing the halogen element adsorption layer.
Then, on the insulating film after the halogen element is desorbed, the Si or metal element bonded before desorption remains in a released state, and this becomes a growth nucleus when performing a selective CVD of a metal later. .

As literatures relating to general phenomena caused by light irradiation of the above-mentioned adsorbed species, for example, `` Surface, Vol. 26, No. 11,
Examples include those described on pages 825 to 836 (1988).

Next, it is shown by the following experimental data that the ion beam irradiation has the effect of forming an active layer on the insulating film surface in the same manner as the electron beam irradiation. 2 shown in Table 1
We made various kinds of samples and used X-ray photoelectron spectroscopy (X-ray Phot
oelectron Spectroscopy, XPS, or Electron Spectros
copy for Chemical Analysis, ESCA. Hereinafter referred to as ESCA)
The activation of the SiO ₂ surface by Ar sputter etching was examined using an apparatus.

・ Ar sputter etch: back pressure: 3 × 10 ^-7 Torr, Ar flow rate: 100 sccm, P: 10 mTorr, RF power: 480 W (13.56 MHz), substrate bias: −550 V, etching amount: 250Å (SiO ₂ film conversion) And the content ratio of Si and O on the surface (O / Si) was determined. Table 2 shows the results.

Stoichiometrically, the O / Si ratio is 2.0 for perfect SiO ₂ , but the values in Table 2 are all 2.0 or more (that is, O-rich than SiO ₂ ). This sample prior to analysis in order to contain O ₂ adsorbed to exposure to the atmosphere. As is apparent from Table 2, in Ar sputtering, O has a higher sputtering efficiency than Si, and therefore, the surface of the Ar sputter etch sample (# 2 sample) is the surface of the untreated sample (# 1 sample). It is richer than Si.

Further, for more detailed verification, the spectrum of the Si2P peak when the X-ray incident angles on the SiO ₂ surface were 30 ° and 90 ° were obtained. The ESCA results of the untreated sample (# 1) and the Ar sputter etch sample (# 2)
These are shown in FIGS. Here, the horizontal axis represents the binding energy, and the vertical axis represents the peak intensity. The shallower the incident angle of the X-rays, the shallower the depth of the X-rays penetrating from the surface, indicating information closer to the surface layer. In general, stable Si-
When the O bond is cut and unbonded Si or Si-Si bond occurs,
It is known that a chemical shift to the low energy side occurs. In FIG. 12 (a), the peaks at 30 ° and 90 ° on the untreated SiO ₂ surface completely coincide with each other, whereas the surface after the Ar sputter etching shown in FIG. Shifts to the low energy side at the peak of 30 ゜,
The line width is broad. For the 30 ° peak, which is the surface layer, the above two samples (# 1 and # 1)
FIG. 12 (c) shows the result of the comparison in 2). From this figure, in the sample # 2, the stable Si—O bond was broken by Ar sputter etching on the SiO ₂ surface, and the unbonded Si and Si—Si
It can clearly be seen that binding has taken place, ie the surface has been activated. This indicates that an ion beam having a high irradiation ion current density that collides with the surface more or more than the Ar sputter etch has a sufficient activation effect on the insulating film surface. In the above description, Ar
Although ions have been described, other ions have a similar effect because O has a higher sputtering efficiency against ion bombardment than Si. Further, with respect to a Ga ion beam usually used in a focused ion beam (FIB) device, Ga adheres to an irradiated portion at the same time as the above operation, and the Ga itself is a growth nucleus in selective metal CVD. Therefore, a new effect is also added, and an effect of forming an active layer on the surface of the insulating film is obtained.

A commonly used EB exposure apparatus can be used as the electron beam irradiation chamber used for the above-described process of forming the active layer on the insulating film surface. As the ion beam irradiation chamber, the secondary ion analysis (Secondary
An ion mass spectroscopy (SIMS) device or a focused ion beam (FIB) device can be used. These are devices that process wafers in a vacuum.They can be transported in a vacuum in a relatively simple manner and continuously select metal CVD.
However, in the ultraviolet irradiation chamber, it is necessary to improve a commonly used reduced projection type exposure apparatus so that the wafer can be placed in a vacuum. this is,
This is because once the wafer is exposed to the atmosphere, oxygen and moisture in the atmosphere are adsorbed on the surface of the formed active layer, and the active point density on the surface is reduced.

After performing the active layer forming process on the insulating film surface described above,
By performing selective CVD using WF ₆ and a reducing gas such as H ₂ or SiH ₄ , no W is formed on the insulating film on which the active layer is not formed, and only the surface of the active layer is grounded. W or a reaction with a reducing gas causes W to grow.
That is, this selective CVD process has an effect of forming a wiring by growing W only on the active layer corresponding to the wiring pattern.

Note that the insulating film used in the present invention is used for LSI such as a thermal oxide film, a thermal nitride film, an inorganic insulating film such as PSG, BPSG, a plasma oxide film, and a plasma nitride film, or an organic insulating film such as SOG and PIQ. Refers to all insulating films.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings by dividing into four cases including a reference example.

Reference Example 1 This reference example is a reference example in the case where the process of forming an active layer on the surface of an insulating film is performed by scanning a focused electron beam in the wiring forming method according to the present invention. FIG. 3 shows the process flow, and FIG. 7 shows an apparatus used for forming the wiring. This embodiment will be described below with reference to FIG. 3 while referring to FIG.

After placing the wafer 109 in the load lock chamber 101 shown in FIG. 7, the inside of the load lock chamber 101 is evacuated. 10 inside
After evacuating to about ^-5 Torr, the wafer 109 is heated to about 200 ° C. by a lamp heater (not shown) in the same chamber,
The water adhering to the wafer 109 is burned out. After confirming that the pressure rise in the load lock chamber 101 due to the baking out of water from the wafer 109 during heating stops (after about 2 minutes), the heating is stopped, the gate valves 104 and 105 are opened, and the wafer 109 is removed. The wafer is transferred to the electron beam irradiation chamber 116 by a wafer transfer mechanism (not shown) and installed. The electron beam irradiation chamber 116 includes an XY stage 117, an electron lens 118, an electron gun 1
It is made up of 19 and is evacuated to about 10 ^-8 Torr by a turbo pump (not shown) in advance. Gate valve 105 that is carried out when wafer 109 is loaded into electron beam irradiation chamber 116
, The pressure in the electron beam irradiation chamber 116 slightly increases, but recovers to the original pressure at the moment when the gate valve 105 is closed after the wafer 109 is installed. After confirming this, CAD
An electron beam is scanned according to data input in advance to a computer (not shown) for (Computer Aided Design).

In this reference example, 3 × 3 mm
Lines and spaces of 0.5 μm and 2.5 μm (that is, 1000 rectangular lines of 0.5 μm × 3 mm) were drawn in the corners. The electron beam was drawn at an acceleration voltage of 20 kV and a current of about 10 nA. In this reference example, 3 ×
Since only a small area of 3 mm square was drawn, scanning of the electron beam was completed in a matter of seconds.

Next, the gate valve 105 is opened, and the wafer 109 is transferred by a wafer transfer mechanism (not shown) to the film forming chamber 102 which has been evacuated to 10 ⁻⁵ Torr or less in advance. Wafer 109
After being transported and set in the film formation chamber 102, the gate valve 105 is closed, and Ar gas is introduced from the gas introduction pipe 111 to the back side of the wafer 109. The gate valve 104 is closed at the same time as the pressure in the film formation chamber 102 gradually starts to increase, and H ₂ gas is introduced into the film formation chamber 102. In the film forming chamber 102, the wafer 109 receives infrared rays from the halogen lamp 106 for heating the wafer through the quartz window 114 and is heated to a predetermined temperature. The power of the wafer heating halogen lamp 106 is controlled by a thermocouple 107 installed between the quartz window 114 and the back surface of the wafer 109 and calcium fluoride (C
aF ₂ ) The infrared radiation emitted from the surface of the wafer 109 through the window 115 is monitored, and the temperature is controlled by an infrared radiation thermometer 110 installed so that the temperature of the wafer 109 can be measured. Further, the inner wall of the film formation chamber 102 is water-cooled, and the temperature of the inner wall of the film formation chamber 102 except for the surface of the wafer 109 is sufficiently set so that the film formation reaction does not substantially proceed even when the wafer 109 is heated. Temperature (about 120 ° C or less). After the wafer 109 is heated to a predetermined temperature, WF ₆ gas is introduced in addition to H ₂ gas to selectively grow W. Then, after the film is grown to a predetermined film thickness (about 0.5 μm in this reference example), the introduction of the H ₂ gas and the WF ₆ gas is stopped, and the halogen lamp 106 for heating the wafer is turned off and evacuated. Here, the gate valve 104 is opened, and the wafer 109 is transferred to the load lock chamber 101. Next, the gate valve 104 is closed, N ₂ is introduced and leaked, and the wafer 109 is cooled at the same time.
After the pressure in 01 reaches the atmospheric pressure, the wafer 109 is taken out of the room, and the W wiring forming process is terminated.

FIG. 13 shows how the wafer surface changes as the process progresses. FIG. 13 (a) shows the initial wafer surface, where the surface is an insulating film (SiO ₂ ). FIG. 13 (b) shows that a 0.5 μm line is 2.5 μm by an electron beam.
This shows a state in which the active layers 202 are formed at intervals of 3 μm with the above space. FIG. 13 (c) shows a state in which a 0.5 μm-thick metal wiring 203 having a thickness of 0.5 μm is formed using the active layer formed as described above as a nucleus. Here, W also grows in the horizontal direction and the wiring width increases, resulting in 1.5 μm.
m lines and spaces are formed.

Next, with respect to the wafer after the formation of the W wiring in the present reference example, the appearance was evaluated with respect to the selectivity and the film morphology, and the electrical evaluation was performed with respect to the film specific resistance of the wiring. The selectivity was evaluated by observing the number of W particles per unit area in the space where the SiO ₂ was exposed between the wires after the formation of the W wires in a dark field with a magnification of 2000 times using an optical microscope. did. Regarding film morphology, the surface of the film after forming the W wiring film is scanned with a scanning electron microscope (Scanning Ele).
ctron Microscopy, SEM.
Observation and evaluation were performed at a magnification of 20,000. As a result, regarding selectivity, W particles were not found at all in the range of 3 × 3 mm square, and it was confirmed that the selectivity was extremely good. In order for the film morphology, in this reference example with H ₂ as the reducing gas, the film thickness 0.
Although it became a film peculiar to the H ₂ reduction film having a surface roughness of about 0.1 μm with respect to 5 μm, it is considered that the surface roughness of such a degree can be sufficiently used as a wiring. Next, pads were provided at both ends of the W wiring, the resistance between the pads was measured with a prober, and the specific resistance of the film was calculated from the wiring cross-sectional area and the wiring length observed and measured by the above SEM. There are 75 sets of patterns on one wafer, and there is a part in one pattern where wiring between pads can be measured.
Since there are 10 points, a total of 750 points can be measured, but of these, 50 points were arbitrarily measured. The resulting film resistivity is 8～12Myuomegacm, normal H ₂ reduction of W
About the same as the film resistivity obtained by CVD. Incidentally, according to the reference example, with an emphasis on keeping the wiring resistance low, generally Makuhi resistor is known that low H ₂ reduction CV
Although the W wiring was formed by D, if a slight increase in resistance is allowed, the W wiring is formed by using SiH ₄ reduction CVD, and the W surface is excellent in the film morphology having a smooth film surface.
It is also possible to obtain a membrane.

Comparative Example: In forming an active layer on an insulating film surface by an electron beam,
In order to compare the case where the irradiation electron current was reduced, the same apparatus and the same conditions as in Reference Example 1 were used except that the electron beam current when scanning the electron beam was reduced from 10 nA to 1 nA in Reference Example 1 above. Wiring was formed.

Although the selectivity was as good as that of Reference Example 1, the film morphology was extremely coarse, and W
The W film was more appropriate to call the one in which the grains were arranged on a straight line. This is presumably because in the formation of the active layer by the electron beam, the density of active points on the active layer was low due to the low irradiation electron current, and the crystal was grown in the early stage of W film formation while the density of W nuclei was low.

Example 1 In this example, among the wiring forming methods of the present invention, before the active layer forming process, the halogen gas plasma process on the insulating film surface was performed, and the active layer forming process on the insulating film surface was sensitive. This is an embodiment in a case where the operation can be performed. FIG. 4 shows the process flow, and FIG. 8 shows an apparatus used for forming the wiring.

This embodiment is different from the first embodiment in that FIGS.
As can be understood from comparison with the figures, the plasma processing chamber 103 is provided between the film forming chamber 102 and the electron beam irradiation chamber 116, and the wafer 109 is moved from the load lock chamber 101 to the electron beam irradiation chamber 116. The point is that before the transfer, the wafer 109 is once transferred to the plasma processing chamber 103, subjected to plasma gas processing, and then transferred to the electron beam irradiation chamber 116. Therefore, in the description of this embodiment, the wafer 109 is placed in the plasma processing chamber 103,
Only the steps up to the point where the sheet is conveyed to step 6 will be described, and the other points are completely common except for particularly different points.

The plasma processing chamber 103 is evacuated to about 10 ⁻⁷ Torr by a cryopump (not shown) in advance.
The plasma processing chamber 103 performs only the surface treatment of the wafer 109, and the electrode on the wafer side is a cathode coupling so that metal contaminants and the like from the inner wall and electrodes of the plasma processing chamber 103 do not adhere to the wafer 109. During the discharge, a negative potential bias is applied to the wafer side so that ions during the discharge are sputtered on the inner wall of the plasma processing chamber 103 as much as possible, and only the wafer 109 on the side of the cathode electrode 108 is surface-treated. It is configured. Further, the cathode electrode 108 is provided with a quartz cover (not shown) in order to minimize metal contamination from the electrode exposed portion on the outer periphery of the wafer 109.
From the load lock chamber 101 for the wafer 109 to the plasma processing chamber 103
The pressure in the plasma processing chamber 103 slightly increases due to the opening of the gate valve 105 accompanying the transfer into the chamber, but when the gate valve 105 is closed after the wafer 109 is installed, the pressure recovers to the original pressure instantaneously. After confirming this, Ar gas and NF ₃ gas are introduced into the plasma processing chamber 103 from the gas inlet 112. Then
The high-frequency power is applied to the cathode electrode 108 of the plasma processing chamber 103 by the high frequency power source 113 to generate NF ₃ plasma. After discharging for a predetermined time, the introduction of Ar gas and NF ₃ gas and the application of high-frequency power are stopped, and the discharge is stopped.
After confirming that the pressure in the plasma processing chamber 103 has been restored to about 10 ⁻⁷ Torr again, the gate valve 120 is opened, and the wafer 109 is evacuated to 10 ⁻⁶ Torr or less in an electron beam irradiation chamber 116. The wafer is transferred and installed by a wafer transfer mechanism (not shown). Thereafter, all the processes were performed in the same manner as in Reference Example 1 (that is, the same as in the Comparative Example) except that the irradiation was performed with the irradiation electron current in electron beam irradiation set to 1 nA.

The selectivity, film morphology, and film specific resistance of the wiring were evaluated for the finally obtained wafer after the formation of the W wiring in the same manner as described in Reference Example 1. The result was obtained. Here, it should be noted that in the formation of the active layer on the surface of the insulating film, although the irradiation was performed while the current of the electron beam to be irradiated was reduced to 1/10 of that in the reference example 1, it was the same as in the comparative example. In addition, the morphology of the film surface did not become coarse, and was equivalent to that of Reference Example 1. This is probably because the sensitivity to electron irradiation was improved because the surface of the insulating film was previously fluorinated by NF ₃ plasma treatment as described above. In addition, this result:
This indicates that when the irradiation electron current is increased by 10 times to 10 nA and the irradiation is performed, the scanning speed can be increased by 10 times, and therefore, an improvement in throughput can be expected.

Reference Example 2: This reference example is one of the wiring forming methods related to the present invention.
This is a reference example in the case where a focused ion beam is scanned as a process of forming an active layer on the surface of an insulating film. FIG. 5 shows the process flow, and FIG. 9 shows an apparatus using wiring formation.

In the present embodiment, the process is exactly the same as that of Embodiment 1 except that the activation treatment of the insulating film surface is changed from an electron beam to an ion beam. 9, reference numeral 121 denotes an ion beam irradiation chamber, which includes an ion lens 122, a differential exhaust chamber 123,
It is configured to include the ion generation chamber 124.

The ion beam used in the present reference example was a Ga ion beam generally used for a focused ion beam (FIB), and irradiation was performed at an ion current of 10 nA and an acceleration voltage of 3 to 10 kV. The minimum size of the condensed beam diameter was set to 0.5 μm, but it was difficult to further reduce the beam diameter because the acceleration voltage was low as described below. That is, in general,
It is necessary to increase the acceleration voltage in order to reduce the focused diameter of the ion beam.
Sputtering on the surface of the insulating film occurs more than Ga does. As mentioned earlier, the insulating film surface is activated by sputtering, but by preliminary experiments conducted by changing the acceleration voltage, it was better to attach a metal called Ga rather than a Si-rich surface generated by sputtering. Since it was already known that even at the same ion current, the nucleation density of the W wiring was increased and the film morphology was improved, in this reference example, irradiation was performed within the acceleration voltage range where Ga adheres. However, when a finer wiring width is required, the acceleration voltage is increased and the scanning speed is reduced,
By sputter-etching the surface of the insulating film, it becomes possible to form an active layer having a finer pattern.

In this reference example, the wafer obtained by forming W wiring by selective CVD of W was evaluated for selectivity, film morphology and film specific resistance of the wiring in the same manner as described in reference example 1. The same excellent results as in Reference Example 1 were obtained.

Embodiment 2 In the present embodiment, in the wiring forming method of the present invention, as an active layer forming process on the insulating film surface, first, a halogen gas plasma process is performed to form an active layer on the insulating film surface by ultraviolet irradiation. This is an embodiment in which a line-and-space test pattern similar to that of Reference Example 1 is formed by irradiation with ultraviolet rays to form an active layer on the surface of an insulating film using a projection reduction exposure apparatus. . FIG. 6 shows the process flow, and FIG. 10 shows an apparatus used for forming the wiring.

This embodiment is different from the first embodiment in that FIGS.
As can be seen from comparison with the figure, the electron beam irradiation chamber 116
Is that an ultraviolet irradiation chamber 125 is provided in place of the above. The ultraviolet irradiation chamber 125 includes a quartz window 126, an optical lens 127, a reticle 128, and an ultraviolet lamp 129. The difference between the process flows of FIGS. 4 and 6 is that, in the present embodiment, the halogen gas in the halogen gas plasma treatment was changed from NF ₃ gas to Cl ₂ gas, and the activation treatment of the insulating film surface was performed. Is changed from electron beam irradiation to ultraviolet irradiation. Otherwise, the wiring forming process was performed in exactly the same manner as in Example 1.

A g-line (436 nm) aligner, which is generally marketed as a reduction projection exposure apparatus, is provided in the ultraviolet irradiation chamber 125 with a wafer 109.
Was modified so that it could be irradiated with ultraviolet light in vacuum. The ultraviolet irradiation was performed at an intensity of about 300 mW / cm ² for about 3 seconds (that is, 900 mW / cm ² ). In this embodiment, after the exposure at the ultraviolet wavelength of 436 nm as described above, the same effect can be expected if the wavelength is shorter than this, so that a commercially available i-line (365 nm) aligner or KrF
It is also possible to use an excimer (248 nm) aligner.

Also in this embodiment, similarly to Reference Example 1, W selection CV
The selectivity, the film morphology, and the film specific resistance of the wiring were evaluated for the wafer obtained by forming the W wiring by D in the same manner as described in Reference Example 1. The result was obtained.

As described above, several embodiments of the present invention have been described. However, the present invention is not limited only to the apparatuses and conditions shown in the above-described embodiments. Any type of lens may be used, and the ultraviolet irradiation device may be not only a reduced projection type but also a conventionally used ultraviolet exposure device such as a one-projection type. However, when a wafer is placed in a vacuum to perform continuous processing, a mask-contact type that involves the movement of a mask requires a technically devised transfer system. Also,
In the plasma processing of the present invention, there is no metal contamination on the wafer, a halogen-based gas such as NF ₃ , Cl ₂ , and BCl ₃ can be introduced, and an etching chamber capable of applying a high frequency is used.
In the case of D, a cold wall type CVD film forming chamber capable of selective film formation of W is used, and an apparatus having a transfer mechanism capable of vacuum transfer of a wafer between these processing chambers is used. The same effect as described above can be obtained.

In the above embodiment, the surface treatment of the insulating film by the halogen-based gas plasma was performed in the chamber for Ar sputter etching.However, since the surface treatment is mainly based on the chemical etching action, a method free from other metal contamination, for example, EC
It is possible to use a method that is applied to or studied in a semiconductor process such as the R microwave plasma method. Furthermore, for the selective CVD systems and metal of interest, WF ₆ -H ₂ system or WF ₆ -SiH ₄ described in the above Example
The system is not limited to the selective CVD of W by the system, but a system that enables the selective CVD, for example, MoF ₆ -H ₂ system, selective CVD of Mo by the MoF ₆ -SiH ₄ system, alkyl Al and other organometallic compounds as raw materials. It goes without saying that the present invention can be applied to the selective CVD of Al and the selective CVD of Cu.

〔The invention's effect〕

As described above, according to the present invention, it is not necessary to use a conventional resist when forming a wiring, and a significant reduction in the number of steps in the wiring formation process is realized. It can greatly contribute to shortening. In particular, there is an effect that a large cost reduction can be achieved particularly for a semiconductor production department having a large variety of small-quantity production.

[Brief description of the drawings]

FIG. 1 is an explanatory view showing a wiring forming process of a wiring forming method according to the present invention, FIG. 2 is an explanatory view showing a wiring forming process of a conventional method, and FIGS. 4 and 6 are wirings of an embodiment of the present invention, respectively. FIGS. 8 and 10 are diagrams showing the configuration of the wiring forming apparatus used in the above embodiment, respectively, and FIGS. 3 and 5 are the process flows of forming the wiring of the reference example, FIGS. FIG. 9 is a block diagram of the wiring forming apparatus used in the above reference example, and FIG. 11 is a graph showing the variation of the irradiation current density used in the experiment for showing the action of forming the active layer on the insulating film surface by the electron beam. Depth profile by AES, Fig. 12 shows the spectrum of the Si2p peak by ESCA used in the experiment to show the action of forming the active layer on the insulating film surface by the ion beam, and Fig. 13 shows the example of the present invention. Wiring formation It is explanatory drawing which shows the detail of a process. EXPLANATION OF SYMBOLS 101: load lock chamber 102: film forming chamber 103: plasma processing chamber 104, 105, 120: gate valve 106: halogen lamp for heating a wafer 107: thermocouple, 108: cathode electrode 109: wafer 110 … Infrared radiation thermometer 111,112… Gas inlet 113… High frequency power supply 114… Quartz window 115… Calcium fluoride window 116… Electron beam irradiation room 117… XY stage 118… Electron lens, 119 ... Electron gun 121 ... Ion beam irradiation chamber 122 ... Ion lens, 123 ... Differential exhaust chamber 124 ... Ion generation chamber, 125 ... Ultraviolet irradiation chamber 126 ... Quartz window, 127 ... Optical lens 128 …… reticle, 129 …… UV lamp

──────────────────────────────────────────────────続 き Continuation of front page (72) Inventor Masakazu Ishino 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Pref. Hitachi Manufacturing Co., Ltd. (56) References JP-A-60-138918 (JP, A) JP-A-63-164240 (JP, A) JP-A-63-278348 (JP, A) JP-A-3-202471 (JP, A) JP-A-2-178930 (JP, A) JP-A-2-504444 (JP) , A) WO 89/11553 (WO, A1) (58) Fields investigated (Int. Cl. ⁶ , DB name) H01L 21/28-21/288 H01L 21/3205-21/3213 H01L 21/768

Claims (4)

(57) [Claims] 1. A method for forming a wiring pattern directly on an insulating film on a substrate by selective CVD of a metal without providing a step of coating, exposing and developing an organic photosensitive material, wherein the surface of the insulating film is formed by halogen. After surface treatment with gas plasma, the surface of the insulating film is scanned with a focused electron beam to determine the content of Si or a metal element in the portion of the insulating film surface to which the electron beam is irradiated. After forming an active layer corresponding to a desired wiring pattern on the insulating film surface by increasing the
D. A wiring forming method, comprising: 2. A method for forming a wiring pattern directly on an insulating film on a substrate by selective CVD of a metal without providing a step of coating, exposing and developing an organic photosensitive material, wherein the surface of the insulating film is halogenated. After the surface treatment with the gas plasma, the insulating film surface is irradiated with light in the exposure chamber, and the content of Si or the metal element in the light-irradiated portion of the insulating film surface is compared with the non-light-irradiated portion of the insulating film surface. A method of forming a wiring, comprising forming an active layer corresponding to a desired wiring pattern on the surface of the insulating film by increasing the height, and then performing selective CVD of a metal. 3. A plasma processing chamber, means for introducing a gas containing at least a halogen gas or a halogen compound gas into the plasma processing chamber, and a substrate having an insulating film surface-treated with halogen gas plasma in the plasma processing chamber. A scanning electron beam irradiation chamber for irradiating a focused electron beam with
Selection C for performing selective CVD of metal on the substrate irradiated with the focused electron beam on the insulator surface in the scanning electron beam irradiation chamber
A wiring forming apparatus comprising: a VD chamber; and a mechanism for transporting the substrate between the plasma processing chamber, the scanning electron beam irradiation chamber, and the selective CVD chamber without exposing the substrate to the atmosphere. 4. A plasma processing chamber, means for introducing a gas containing at least a halogen gas or a halogen compound gas into the plasma processing chamber, and a substrate having an insulating film surface-treated by halogen gas plasma in the plasma processing chamber. An ultraviolet exposure chamber for performing exposure to ultraviolet light, a selective CVD chamber for performing selective CVD of metal on a substrate irradiated with ultraviolet light on an insulator surface in the ultraviolet exposure chamber, and the plasma without exposing the substrate to the atmosphere. A wiring forming apparatus comprising: a processing chamber; and a mechanism for transporting between the ultraviolet exposure chamber and the selective CVD chamber.