JP2934448B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial applications]

The present invention relates to a highly integrated semiconductor integrated circuit that operates at high speed and with low power consumption.

[Prior art]

2. Description of the Related Art Semiconductor integrated circuits tend to increase power consumption due to charge / discharge of load capacitance as the integration density increases. For this reason, semiconductor integrated circuit technology that operates at high speed and with low power consumption is important. In recent years, demand for portable electronic information devices such as laptop personal computers and electronic organizers, portable electronic media devices such as audio recording devices not using magnetic media, and electronic still cameras has been increasing. In order to store a large amount of information in these portable electronic devices and retain the information, a low power consumption ultra-highly integrated semiconductor circuit (ULSI) that enables battery operation and battery information retention operation (battery backup) is required. )Is required. In order to reduce the power of the ULSI, it is effective to reduce the operating voltage of the main circuit block and the amplitude of a signal that carries information between circuits. DRAM (Dynamic Random Access Memory) is a representative of ULSI. In order to reduce the power consumption of the DRAM, it is important to reduce the data line charge / discharge power, which accounts for about half of the power consumption. Conventionally, regarding the low power consumption of DRAM, NC Lu and HH Chao, “Half-Vide Day Bitline Sensing in Cimos Deram” IEEJ, Solid State Circuit, Vol.
1984 (N, C, Lu and HHChao, “Half-VDD bit-Line se
nsing scheme in CMOS DRAM'S "IEEE J. Solid-State Cir
cuits, Vol. SC-19, pp. 451-454, 1984). The feature of the half VDD precharge method is that the signal amplitude of the data line is halved compared to the VDD precharge method (details are described in JP-A-51-74535, USP 3514765, etc.). The charge consumption in one cycle may be halved,
(2) The noise in the memory array is small. (3) The cycle time can be shortened because the charge / discharge time of the data line is short. However, when the signal amplitude of the data line is reduced along with the high integration of the memory, the conventional LSI has been configured with one type of MOS-FET regardless of the signal amplitude. When the threshold voltage is approached, there is a problem that the circuit malfunctions and the speed performance is remarkably impaired. Therefore, even if the signal amplitude is reduced by half,
The power consumption is about twice that of the VDD precharge method, and the advantage of low power consumption cannot be enjoyed. The above is an example of the case of a DRAM, but also in a conventional logic LSI, the lower limit of the signal amplitude is limited by the threshold voltage of the MOS-FET, so that a high-speed and ultra-low power ULSI There was a problem that can not be realized.

[Problems to be solved by the invention]

As described above, in the conventional technology, there is a problem that the element characteristics of the MOS-FET define the lower limit of the low power consumption of the ULSI such as the DRAM, and the high speed required for the battery operation or the battery backup device is required. In addition, there is a problem that ULSI with low power consumption cannot be provided. It is an object of the present invention to provide a semiconductor integrated circuit which can solve such a conventional problem and can operate at high speed with low power consumption and can operate or back up a battery.

[Means for Solving the Problems]

The above object is to reduce the signal amplitude of a main circuit block that regulates power consumption and the threshold voltage of a MOS-FET that forms the circuit block, or to reduce the gate and source of the MOS-FET that forms the circuit block ( This is achieved by driving the voltage between the drains or the voltage between the drain and the source dynamically or statically with a large voltage value sufficiently exceeding the threshold voltage of the MOS-FET.

[Action]

By the above means, only the signal amplitude of the main circuit can be reduced, and ULSI that achieves both high speed and low power consumption can be provided.

【Example】

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
In the following embodiment, an example in which the present invention is applied to a DRAM will be described.
However, dynamic and static
Random access memory (RAM) or read-only
-Memory (ROM) and even microcomputers
To any type of LSI, such as a logic LSI
Is also good. The component is a bipolar transistor.
Star, MOS transistor, combination of these elements,
Or a GaAs-type transformer using a material other than Si, for example.
Any of such as a resistor may be used. FIG. 1 shows a first embodiment of the present invention. Fig. 1
(A) is a circuit configuration of the present embodiment. This circuit is
A VthMOS transistor with a low threshold voltage Vth is applied to the sense amplifier.
It uses a resistor (Q1 ', Q2', Q3 ', Q4').
Operate the data line of this circuit at low voltage amplitude (1.0V)
Will be described with reference to operation waveforms in FIG.
You. Change the voltage of word line W0 from VSS (0V) to VDH (1.5V).
Then, the information stored in the storage capacitor CS is read out to the data line D.
Is done. Next, P1P is changed from VDL (1.0V) to VSS (0V), P1N
When VSS (0V) is changed to VDL (1.0V), sense amplifier drive
Transistors QP and QN turn on and sense amplifier drive line CSP
From HVC (0.5V) to VDL (1.0V) and CSN from HVC (0.5V)
To VSS (0V). At this time, the sense amplifier of the present invention is used.
The transistors are low threshold voltage transistors (Q1 ', Q2',
Q3 ', Q4'), gate and source (drain)
In), the voltage exceeds the threshold voltage sufficiently,
The transistor of the amplifier turns on enough and the signal voltage of the data line
Can be sufficiently amplified. However, with conventional sense amplifiers
Means that the voltage between the gate and the source (drain) is
Voltage, the number of transistors in the sense amplifier is sufficient.
And the signal voltage on the data line cannot be amplified sufficiently.
You. The operation of the data lines thereafter is the same as that of the conventional DRAM.
is there. FIG. 1 (a ') shows the case where the data line is connected to the normal voltage amplitude.
(For example, 1.5 V). This place
If the sense amplifier of the present invention is used,
The charging / discharging speed of the power line is slightly increased. FIG. 1 (b) shows the book
9 illustrates the effect of the embodiment. VDLmin is Sense Ann
This is the data line charging voltage when the operation limit is reached. IDSm
ax assumes 64Mbit DRAM (Q1, Q2, Q3, Q4: W / L =
2μm / 0.5μm, operation of 16000 sense amplifiers), sense amplifier
Voltage between the gate and source (drain) of the
Flow between the drain and source of all sense amplifiers
Is the sum of the currents. MOS transistor gate and source
When the voltage between the (drain) is set to 0V,
RMSWNSON and JDM
EINDL, “Ion-Implanted Complementary MOS Transistor
s in Low-Voltage Circuits ", IEEE J. Solid-State Circ
uits, Vol.SC-7, No. 2, pp. 146-153, April 1972.
Have been. VTO is between the gate and source of the MOS transistor.
Voltage VGS and the square root of the current between drain and source ソ ー ス ID
Assuming that the relationship is simplified as √ID = A · VGS + B,
This is the value of VGS when ID = 0. Fig. 1 (c)
And (d) show the relationship between VTO and transistor channel length Lg.
One example of the engagement is shown. The sense amplifiers (Q1 ', Q2',
Q3 ', Q4') are low VthMOS transistors, other circuits are standard V
thMOS transistor, conventional sense amplifier (Q1, Q2, Q3, Q
4) is a high VthMOS transistor. Thus, Sen
A transistor with a large channel length Lg (Lg = 0.
5 μm) is used depending on the processing variation of Lg.
The threshold voltage of the transistor of the
This is to prevent the sensitivity of the sense amplifier from lowering.
You. Transistors other than sense amplifiers have high drive capability
In order to obtain a value, a small value of Lg (for example, 0.3 μm) is used.
The difference between the operation of the present embodiment and the conventional one is that VDL is about 1.0 V.
This is when the voltage becomes low. For example, FIG.
And the high VthMOS transistor (VTO = 0.5V) shown in (d)
In the case of the conventional method used for a sense amplifier, FIG.
As shown, the sense amplifier does not operate when VDL is 1.2V.
(The worst value of VTO is 0.6V). The low VthMOS transistor of this embodiment
When transistor (VTO = 0.3V) is used for sense amplifier
If the VDL is 1.2 V, the sense amplifier can operate
You. This is the gate and source (drain) of the sense amplifier.
VTO is 0.4V (worst value) for a voltage of 0.6V between
Is low enough. In this embodiment, VDL> 0.8V
Operable. At this time, the drain of the sense amplifier
The current IDSmax flowing between the sources is 100 μA (sense amplifier 1
6000), which is not enough compared to the data line charging current
It is a value that can be seen and there is no problem. FIG. 1 (c) and (d)
The low VthMOS transistor shown in
Is made by changing the ion implantation dose.
Other than the sense amplifier, the transistor drain and source
Where low voltage is applied between the memory arrays (for example,
I / O line switching transistor for ard)
By using a low VthMOS transistor for
The same effect as the low voltage operation of the amplifier can be obtained.
Depletion type instead of low VthMOS transistor
Obtaining the same effect as above even when using MOS transistors
Can be. In this case, the printer that does not drive the sense amplifier
During charging, the N-channel MOS transistor of the sense amplifier is
Lower the substrate potential of the transistor (P-channel MOS transistor
The substrate potential of the data line), and no current flows between the data lines.
To be. Thus, according to the present embodiment, a lower
Operates without significant loss in speed performance even at low supply voltages
Memory circuit that performs Also, only for sense amplifiers
High speed by using differently according to the application of the circuit
In addition, an LSI with low power consumption can be provided. And even memory
Not only in other LSIs such as a logic LSI (for example,
LSIs that operate at lower voltages
it can. FIG. 3 shows second and third embodiments of the present invention.
FIG. 3A shows the circuit configuration of the second embodiment. This time
The path is two conventional sense amplifier drive transistors each
Connect in parallel (QP1, QP2, QN1, QN2) and drive sense amplifier
Boost capacitances CBP and CBN are added to the lines CSP and CSN. Sen
P-channel MOS transistors Q3, Q4,
Substrate potential is the same as the sense amplifier drive lines CSP and CSN.
You. The operation of this circuit will be described with reference to FIG.
You. Change the voltage of word line W0 from VSS (0V) to VDH (1.5V).
Then, the information stored in the storage capacitor CS is read out to the data line D.
Is done. Next, P1P is changed from VSS (0V) to VDH (1.5V) and P1N
When VDL (1.0V) is changed to VDB (-0.5V), the sense amplifier
The drive transistors QP1 and QN1 turn on, and the sense amplifier drive
Flow line CSP goes from HVC (0.5V) to VDL (1.0V), CSN goes to HVC
(0.5V) to VSS (0V). Next, PBP is changed to VSS (0
V) to VDL (1.0V), and PBN from VDL (1.0V) to VSS (0
V), the sense amplifier drive line is boosted and CSP
Is from VDL (1.0V) to VDH (1.5V), CSN is VSS (0V)
To about VDB (-0.5V). At this time, P1P is VD
H (1.5V) to VSS (0V), P1N from VDB (-0.5V) to VDL
(1.0V) to inject into the sense amplifier drive line
Charge is passed through the sense amplifier drive transistor
No discharge. This allows the sense amplifier to
Gate and source of transistors (Q1, Q2, Q3, Q4)
The voltage between the source (drain) can be set to about VDL / 2 + 0.5V.
Therefore, the sense amplifier is sufficiently turned on, and the data lines D and D are connected to VDL (1.
0V) and VSS (0V). Sense amplifier drive line block
After the boost, P2P is changed from VSS (0V) to VDH (1.5V), and P2N is
Change from L (1.0V) to VDB (-0.5V) to drive sense amplifier
Turn on transistors QP2 and QP2 to increase the number of sense amplifiers.
Make sure it is wide enough. Subsequent data lines
The operation is the same as the conventional one. 3 (b).
To obtain boost voltage, boost capacitance CBP, CBN must be 1
It should be about 50pF (the data line is connected to the sense amplifier drive line)
If 1000 sense amplifiers with a capacity of about 300 fF are connected,
Fixed). The voltage value of each terminal is not as shown in FIG.
The voltage amplitude between the sense amplifier drive lines CPS and CSN is
It is sufficient that the voltage amplitude is larger than the voltage amplitude between the data line D and the data line D. VDH
Voltage can be generated by boosting VDL and stepping down external power supply
May be generated. CSP only or CSN only
May be the best. Connect boost capacitor CBP to VDL wiring
May be provided to boost the VDL. At this time,
The substrate potentials of the pump driving transistors QP1 and QP2 are the same as VDL.
Set to potential. Sense amplifier drive transistors QP1, QP2,
QN1 and QN2 are P-channel MOS transistors or N-channel
It can be a MOS transistor or a bipolar transistor
The potential of the sense amplifier drive line is changed from HVC to VDL and C on the CSP side.
What is necessary is to change from HVC to VSS on the SN side. Sense amplifier drive line
When boosting, the substrate potential of each transistor
Latch-up by preventing
Can be prevented. Set the substrate potential of sense amplifiers Q3 and Q4 to
The sense amplifier Q1,
Make the substrate potential of Q2 the same as the sense amplifier drive line CSN
Prevents rise of threshold voltage due to substrate effect
Therefore, the operation of the sense amplifier can be further improved.
Sense amplifier substrate potential equal to sense amplifier drive line
In order to achieve this, the substrate may have a triple-well structure.
The triple well structure is specified in JP-A-62-119958.
Have been. The first sense amplifier (Q1, Q2, Q3, Q4)
By using the low VthMOS transistor of the embodiment,
Furthermore, it can be operated at a low voltage. Thus, the book
According to the embodiment, the speed performance is significantly improved even at a lower power supply voltage.
It is possible to provide a memory circuit that operates without damage.
Not only for sense amplifiers, but also
Providing high speed and low power consumption LSI
Wear. Furthermore, not only memory but also other L such as logic LSI
For SI, we can provide an LSI that operates at lower voltage.
You. FIGS. 3C and 3D show the concept of the third embodiment.
I have. In FIG. 3 (c), the constant voltage generation circuit LVD is provided in the chip.
Provide H, LVDL, LVDBL and generate constant voltage VDH, VDL, VDBL
I have. The constant voltages VDH, VDL, VDBL and VDBH (= VSS)
Switches SP1, SP2, SN2, SN1, and sense amplifier drive lines CSP, C
Connect to SN. Each voltage relationship is VDH ≧ VDL> VDP (P
Recharge voltage)> VDBL ≧ VDBH (= ground voltage VSS) ≧ VBB
(Substrate voltage). The operation of this circuit is as follows.
You. First, the voltage of the data line D, and the sense amplifier drive
The voltages of the lines CSP and CSN are set to the precharge voltage VDP. next,
Turn on the switches SP1 and SN1, and turn on the sense amplifier drive lines SP1 and SN1.
Is turned on, and the sense amplifier drive line CSP is set to VDH and CSN is set to VDBH (V
SS). This allows the sense amplifier to be configured
The voltage between the gate and source (drain) of the transistor is VD
Because it can be larger than P, the sense amplifier turns on enough,
The data lines D and A can be amplified to about VDL and VDBL. Next, Sui
Switches SP1 and SN1 are turned off, and SP2 and SN2 are turned on. By this
The sense amplifier drive line CSP becomes VDL and CSN becomes VDBL,
The data lines D, can be fixed to VDL, VDBL. Switch SP1, SN
Turn off 1 and turn on SP2 and SN2 at the data line
Set when D, becomes about VDL, VDBL. By this
The data line is above VDL and below data line DGADBDL
Can be prevented. The relationship between the VDH and VDL values and the external power supply voltage VCC
The person in charge may be any kind of relationship. (For example, if VDH = VCC
May be VDL = VCC. ) The voltage of VDH is generated by boosting VDL.
May be live. Substrate voltage VBB is not less than VDBH
Is also good. (For example, VDBHA (= VSS) may be equal to VBB.)
The substrate voltage VBB is applied to the memory array, sense amplifier,
Or apply only one of them and ground the other
Voltage may be used. This uses a triple well structure of the substrate
Can be realized. Regarding the triple well structure of the substrate,
It is specified in 62-119958. Thus, the present embodiment
Shows that even at lower supply voltages, speed performance is significantly impaired.
It is possible to provide a memory circuit that operates without failure. Also,
Use differently depending on the application of the circuit, not just the sense amplifier
As a result, a high-speed and low-power LSI can be provided.
Furthermore, it is not limited to memory, but can be applied to other LSIs such as logic LSIs.
However, it is possible to provide an LSI that operates at a lower voltage. In FIG. 3D, constant voltage generating circuits LVDH and LVD are provided in the chip.
L, LVDBH are provided to generate constant voltages VDH, VDL, VDBH.
You. The constant voltages VDH, VDL, VDBH and VDBL (= VSS) are
Sense amplifier drive lines CSP, CSN via switches SP1, SP2, SN1, SN2
Connect to Each voltage relation is VDH ≧ VDL> VDP (pre
Charge voltage)> VDBL ≧ VDBH (= ground voltage VSS) ≧ VBB
(Substrate voltage). The operation of this circuit is as follows.
You. First, the voltage of the data line D, and the sense amplifier drive
The voltages of the lines CSP and CSN are set to the precharge voltage VDP. next,
Turn on the switches SP1 and SN1, and set the sense amplifier drive line CSP to VD
Set H and CSN to VDBH. This allows the sense amplifier to be configured.
Between the gate and source (drain) of the transistor
Since the voltage can be higher than VDP, sufficient sense amplifier
Turn on and amplify data lines D and D to about VDL and VDBL (VSS)
You. Next, turn off the switches SP1 and SN1 and turn on the switches SP2 and SN2.
You. As a result, the sense amplifier drive line CSP becomes VDL, CSN
Becomes VDBL (VSS), and data lines D and VDL, VDBL (VSS)
Can be fixed to Turn off switches SP1 and SN1 and turn off SP2 and SN2.
When the data lines D, VDL and VDBL are
Set when As a result, the data line D goes below VDL.
In addition, it is possible to prevent the data line from going below VDBL. VD
What is the relationship between the values of H and VDL and the external power supply voltage VCC?
May be. (For example, VDH = VCC or VDL = VCC
No. ) The voltage of VDH may be generated by boosting VDL.
Substrate voltage VBB need not be lower than VDBH. (example
For example, VDBH may be equal to VBB. ) The substrate voltage VBB is
Part and / or sense amplifier part
In addition, the other parts may be the ground voltage. This is the substrate
This can be realized by using the triple well structure. Three folds of substrate
The L structure is specified in Japanese Patent Application Laid-Open No. 62-119958.
You. Thus, according to the present embodiment, the lower power supply voltage
Memory that works without significantly compromising speed performance
Circuit can be provided. In addition, the circuit is not limited to the sense amplifier.
High-speed and low-consumption by using differently for different applications
It can provide power LSI. Furthermore, not limited to memory,
Operates at lower voltage on other LSIs such as logic LSIs
LSI can be provided. FIG. 3 (e) shows a specific circuit configuration of the embodiment of FIG.
This is one example. This circuit corresponds to the sense amplifier shown in FIG.
The case where only the CPS side of the drive line is shown is shown. Traditional sense
Connect two amplifier driving transistors in parallel (QP
1, QP2, QN1, QN2), P-channel MOS transistor QP1
The drain is VDH (for example, 1.5V) and the drain of QP2 is VDL
(For example, 1.0V). The substrate potential of QP1 and QP2 is VDH
is there. The operation of this circuit will be described with reference to the operation waveform of FIG.
I do. Word line W0 voltage changed from VSS (0V) to VDH (1.5V)
Then, the information stored in the storage capacitor CS is read to the data line D.
Will be issued. Next, P1P is changed from VDH (1.5V) to VSS (0V), P1N
Is changed from VSS (0V) to VDL (1.0V), the sense amplifier drive
Transistors QP1 and QN1 are turned on, driving the sense amplifier
Line CSP goes from HVC (0.5V) to VDH (1.5V), CSN goes to HVC (0.5V)
V) to VSS (0V). As a result,
Gates and sources of transistors Q3 and Q4
(Drain) voltage can be set to about VDL / 2 + 0.5V
Therefore, the sense amplifier is sufficiently turned on and the data line D is connected to VDL (1.0
V). This allows the sense amplifier to
The gate and source (drain) of the transistors Q1 and Q2
The voltage between the data lines also increases, and the data line goes to VSS (0V).
Can be amplified. Data line D voltage exceeds VDL (1.0V)
Around P1P from VSS (0V) to VDH (1.5V), P2P to VDH
(1.5V) to VSS (0V) for sense amplifier drive
Transistor QP1 turns off, QP2 turns on, and sense amplifier drive
The flow line CSP changes from VDH (1.5V) to VDL (1.0V). to this
Therefore, the voltage of the data line D becomes constant at VDL (1.0 V).
You. At this time, P2N is changed from VSS (0V) to VDL (1.0V),
Turning on the sense amplifier drive transistor QN2
So that the sense amplifier can be sufficiently amplified
I do. The operation of the data lines thereafter is the same as in the conventional case.
You. The voltage value of each terminal may be as shown in FIG.
The voltage of the sense amplifier drive line CSP is higher than the data line charging voltage VDL.
It should be bigger. The VDH voltage is generated by boosting VDL.
Alternatively, the voltage may be generated by stepping down the external power supply. sense
The amplifier driving transistors QP1, QP2, QN1, and QN2 are P-channel
MOS transistor or N-channel MOS transistor
Or a bipolar transistor.
Flow line potential from HVC on CSP side to VDL and VDH, HVC on CSN side
It should be VSS from. Substrate potential of sense amplifiers Q3 and Q4
Make the same potential as the sense amplifier drive line CSP
1 Set the substrate potential of Q2 to the same potential as the sense amplifier drive line CSN.
This prevents the threshold voltage from rising due to the substrate effect.
Operation can further improve the sense amplifier operation.
You. Make the substrate potential of the sense amplifier the same as the sense amplifier drive line.
The potential can be set by using a triple well structure of the substrate.
No. Regarding the triple well structure of the substrate, see Japanese Patent Application Laid-Open No. 62-11995.
Specified in 8. The sense amplifiers (Q1, Q2, Q3, Q4)
By using the low VthMOS transistor of the first embodiment,
Operation at a lower voltage. like this
In addition, according to the present embodiment, even at a lower power supply voltage,
Memory circuits that operate without significantly impairing performance
Wear. Not only for sense amplifiers, but also for circuit applications
High-speed and low-power consumption LSI
Can be provided. Furthermore, not only memory, but also logic LSI
In other LSIs, we also offer LSIs that operate at lower voltage.
Can be provided. The voltage relationships described in FIGS. 3 (c) to 3 (f)
Without limitation, the gate of the MOS-FET operating at low amplitude
The source-to-source voltage is reduced for a certain period during operation.
Get the same effect by exceeding it in minutes
Can be. FIG. 4 shows a fourth embodiment of the present invention. Fig. 4
(A) is a circuit configuration of the present embodiment. This circuit is a reference
Storage capacitor plate terminal CSB connected to the data line
Can be driven at once. Precharge circuit
(Q5 ', Q6', Q7 ', Q5, Q6, Q7)
The voltage uses a constant voltage VDP. This constant voltage VDP is shown in FIG.
The characteristics are as shown in (d) or (e). This time
The operation of the road will be described with reference to the operation waveforms of FIG. word
When the voltage of line W0 is changed from VSS (0V) to VDH (1.5V),
The information stored in the capacitor CS is read out to the data line.
When "1" is read, CD / (CD + CS) x (VDL-VDP) = 0.
25CD / (CD + CS) volts, when reading "0", CD / (CD
+ CS) × (VDP-VSS) = 0.75CD / (CD + CS) Volt, (CD
E is the data line capacity) is read out to the data line. This and
The dummy word line DW0 from VSS (0V) to VDH (1.5
V). At this time, the voltage of the reference data line D is
The charge voltage VDP remains at 0.75V. Then for reference
Set the voltage of the storage CS 'plate CSB connected to the data line to V
Change from DP (0.75V) to HVC (0.5V). By doing this,
Lighting data line voltage is CD / (CD + CS) × (VDP-HVC) = 0.25
CD / (CD + CS) volts dropped, signal voltage on data line D,
The difference is VDL / 2 for both “1” read and “0” read.
× CD / (CD + CS) = 0.5CD / (CD + CS) volts. Next
P1P from VDL (1.0V) to VSS (0V), P1N to VSS (0V)
To VDL (1.0 V) from the
The transistors QP1 and QN1 turn on, and the sense amplifier drive line CSP
(0.75V) to VDL (1.0V), CSN from VDP (0.75V) to V
Change to SS (0V). This allows the sense amplifier to be configured.
The gate and source (drain) of transistors Q1 and Q2
Voltage can be set to VDP (0.75V).
Turns on enough to amplify the data line to VSS (0V)
You. As a result, the transistors constituting the sense amplifier
High voltage between gate and source (drain) of Q3 and Q4
That is, the data line D can be amplified to VDL (1.0 V). Then P
2P from VDL (1.0V) to VSS (0V), P2N from VSS (0V)
VDL (1.0V) and set the sense amplifier drive transistor QP
2, By turning on QN2, amplification of the sense amplifier
To be able to do enough. Subsequent data line activity
The work is the same as before. The voltage on plate CSB is
HVC (0.5V) to VDP (0.75
V). The dummy word line DW0 is
When the data line voltage recovers to VDP (0.75V), VDH
(1.5V) to VSS (0V). The above describes the characteristics of VDP.
This has been described with reference to FIG. Fig. 4 (e) shows the characteristics of VDP.
However, a similar effect can be obtained. Voltage relationship of each terminal
May not be as shown in FIGS. 4 (b), (d) and (e)
VDP> VDL / 2 = HVC (FIG. 4 (d)) or VDP <VD
It is sufficient that L / 2 = HVC (FIG. 4 (e)). Fig. 4
As shown in (d) and (e), when VDL becomes high voltage, VDL
VDP = HVC at 1.5V or more. The operation in this case is the fourth
The operation is the same as the conventional one, as shown in FIG. Pre
As a method of driving the gate voltage, Japanese Patent Application No. 62-222317,
There is No. 63-148104. Plate voltage for dummy word line
To drive the pressure at a high speed, as shown in FIG.
Install drivers Q20 and Q21 in the middle of the plate drive line,
-Use word lines DW0 and DW1 as switching signals.
No. Q20, Q21, Q23, Q24, NAD1, NAD2 are in the memory array
Periodically. NAD1 and NAD2 in the figure are memory arrays.
, They may be arranged together. Q20.Q21, Q2 in the figure
3, Q24 may be arranged outside the memory array at once
No. NAD1 and NAD2 in the figure were configured with OR circuits, but NOR circuits
And an inverter. What is the dummy cell
Plate voltage for dummy word line
Is set to a constant voltage (VP) as before, and the dummy word line DW0
The data line voltage immediately after precharge to HVC (0.5V)
When this happens, VDH (1.5 V) may be changed to VSS (0 V).
Or, write a MOS transistor between CS and QW0.
HVC (0.5 V) may be provided. The voltage of VDP is
Even if VDL is generated by stepping down, HVC is stepped up (stepped down)
May be live. Sense amplifier driving transistor QP1,
QP2, QN1 and QN2 are N-channel MOS transistors
Both a MOS transistor and a bipolar transistor
The potential of the sense amplifier drive line can be changed from VDP to VD on the CSP side.
L and CSN should just go from VDP to VSS. Sense amplifier Q3, Q
Whether the substrate potential of 4 is the same as the sense amplifier drive line CSP
The substrate potential of the sense amplifiers Q1 and Q2 is set to the sense amplifier drive line CSN.
Threshold voltage due to substrate effect
Voltage can be prevented, so that the sense amplifier operation
Can be improved. Sense amplifier substrate potential
To set the same potential as the drive line, use a triple well structure of the substrate.
I just need to be. Regarding the triple well structure of the substrate,
It is specified in 62-119958. Sense amplifier drive line CSP
Or by sharing the precharge wiring with the CSN.
Precharge speed without increasing the wiring area
Can be faster. Sense amplifier (Q1, Q2, Q3, Q
4) using the low VthMOS transistor of the first embodiment
Thus, the device can be operated at a lower voltage.
Thus, according to the present embodiment, the operating amplitude of the circuit is
Lower supply voltage by changing according to voltage
Memory that works without significantly compromising speed performance
Circuit can be provided. In addition, the circuit is not limited to the sense amplifier.
High-speed and low-consumption by using differently for different applications
It can provide power LSI. Furthermore, not limited to memory,
Operates at lower voltage on other LSIs such as logic LSIs
LSI can be provided. FIG. 5 shows a fifth embodiment of the present invention. Fig. 5
(A) is a circuit configuration of the present embodiment. This circuit is
The boost capacitance CB is added to each data line. This
The operation of this circuit will be described with reference to the operation waveforms of FIG. Wa
When the voltage of the lead wire W0 is changed from VSS (0V) to VDH (1.5V),
The information stored in the storage capacitor CS is read out to the data line D.
You. Next, the voltage of the boost terminal PCB is changed from VSS (0V) to VDL
(1.0V), both data lines D and D are about 0.2V (CB is
At about 70fF). Next, P1P from VDL (1.0V)
When VSS (0V) and P1N are changed from VSS (0V) to VDL (1.0V),
The sense amplifier driving transistors QP and QN turn on,
SAMP drive line CSP changes from HVC (0.5V) to VDL (1.0V), C
SN changes from HVC (0.5V) to VSS (0V). At this time,
The gates of the transistors Q1 and Q2 that make up the sense amplifier
The voltage between source (drain) is about VDL / 2 + 0.2V
The sense amplifier is turned on enough and the data line
Can be amplified to S (0V). This allows the sense amplifier to
The gate and source (drain) of transistors Q3 and Q4
The voltage between the data lines D and VDL (1.0 V)
Can be amplified. The operation of the data lines thereafter is the same as before.
It is like. The voltage of the boost terminal PCB is
Change from VDL (1.0V) to VSS (0V) before charging. Each terminal
May not be as shown in FIG. 5 (b).
When driving the amplifier, the potential difference between the data line voltage and VSS is VDL / 2
I just need more. Data lines D and D both drop
As described above, the boost voltages may be applied in opposite phases. this
Also, when driving the sense amplifier, the data line voltage and VDL
What is necessary is just the potential VDL / 2 or more. Boost line CBL and sensea
The pump drive line CSP (or CSN) may be common. C
Transistors QP and QN are P-channel MOS transistors.
Whether it is a transistor or an N-channel MOS transistor,
An bipolar transistor may be used, and the sense amplifier drive line
If the potential changes from HVC to VDL on the CSP side and from HVC to VSS on the CSN side
Good. Sense amplifier Q3, Q4 substrate potential
Make the same potential as the flow line CSP or the substrate potential of the sense amplifier Q1, Q2
To the same potential as the sense amplifier drive line CSN.
To prevent the threshold voltage from rising due to the substrate effect.
Therefore, the operation of the sense amplifier can be further improved. Sensea
To make the substrate potential of the amplifier the same as the sense amplifier drive line
May use a triple well structure of the substrate. Triple board
The well structure is described in JP-A-62-119958.
I have. In the sense amplifier (Q1, Q2, Q3, Q4), the first embodiment
By using low VthMOS transistors,
It can be operated with voltage. Thus, the present embodiment
Shows that even at lower supply voltages, speed performance is significantly impaired.
It is possible to provide a memory circuit that operates without failure. Also,
Use differently depending on the application of the circuit, not just the sense amplifier
As a result, a high-speed and low-power LSI can be provided.
Furthermore, it is not limited to memory, but can be applied to other LSIs such as logic LSIs.
However, it is possible to provide an LSI that operates at a lower voltage. FIG. 6 shows a sixth embodiment of the present invention. Fig. 6
(A) is a circuit configuration of the present embodiment. This circuit is the fifth
The data line boost capacitance CB shown in FIG.
To the gates of the transistors Q1 and Q2
These gates and CB can be separated from data lines by QA and QB
Like that. The operation of this circuit is shown in FIG.
This will be described with reference to waveforms. As described above, the word line W0 is
Then, the information is read out to the data line D by the CS. this
At this time, the gate voltage CGA of QA and QB in FIG.
Is maintained at almost the same potential VDH. Therefore, the data
The information on line D is also transmitted through QA to the gate of Q1. What
Note that the above transmission CGA has sufficient QA and QB during precharge.
Any value can be used as long as it turns on. Also, the game of Q2
The reference potential is transmitted to the switch. Next, the sense amplifier drive
Drive transistors QP and QN, and turn on the sense amplifier drive line.
CSP from HVC (0.5V) to VDC (1.0V), CSN from HVC to VSS
(0V). At this time, QA, QB gate voltage CGA
Is connected to the potential of VDL by the capacitor CPC inserted between it and CSN.
QA and QB become high resistance state and
The data line D and the gates of Q1 and Q2 are electrically separated. This
As a result, the boost capacitance CB raises only the gates of Q1 and Q2.
Pressure, so that even if the capacity is smaller than in the fifth embodiment,
A sufficient gate voltage can be obtained. Next, boost terminal PCB
When the voltage of V is changed from VSS to VDL, the gate voltages of Q1 and Q2
To VDL / 2 + 0.2 or more. For this reason, Q1, Q2
It turns on sufficiently and amplifies the data line to VSS at high speed.
This also increases the voltage between the gate and source of Q3.
Thus, the data line can be amplified to VDL at high speed. After this
Operation of the data line and the boost terminal PCB of the fifth embodiment
Same as the example. Note that the precharge of CGA is
Via QPC2 while the pump drive transistor QN is on.
Do it. The precharge voltage is VDL (1.0 V).
As a result, when precharging CSN, the capacity with CPC
Due to the coupling, the CGA is boosted to almost VDH. like this
In addition, according to the present embodiment, even at a lower power supply voltage,
Memory circuits that operate without significantly impairing performance
Wear. Not only for sense amplifiers, but also for circuit applications
High-speed and low-power consumption LSI
Can be provided. Furthermore, not only memory, but also logic LSI
In other LSIs, we also offer LSIs that operate at lower voltage.
Can be provided. FIG. 7 shows a seventh embodiment of the present invention. Fig. 7
(A) is a circuit configuration of the present embodiment. The center of this circuit
The amplifier is Q12-Q15 connected with the data line and capacitance CC.
Consisting of a sense amplifier consisting of conventional A1 to Q4
It consists of two stages. The former is the conventional VD
Operates at a voltage VDH (1.5V) higher than L (1.0V). CH
P and CHN are the common drive lines. The operation of this circuit
The operation will be described with reference to the operation waveform of FIG. As mentioned earlier, the word
When line W0 becomes high potential, information is read from CS to data line D
Is done. This change in the data line potential is Q1 due to the coupling capacitance CC.
It is transmitted to the sense amplifier consisting of 2 to Q15. Next, CHP
From VPH (0.75V) to VDH (1.5V), CHN to VPH (0.75V)
Sense amplifier consisting of Q12 to Q15 when changing from
Starts amplification in response to the signal on the data line. At this time,
The gate-source voltage of Q12-Q15 is the precharge voltage
0.75V, which is applied to the MOS transistor
Sufficiently higher than the threshold voltage of 0.6 V
The capacitance attached to the output of the amplifier is about 1/10 of the data line (gate
And the capacity of CC only), so the sense amplifier
It can be carried out. And the output voltage is VSS (0
V) and VDH (1.5V). Next, set CSP and CSN as before
If VDL and VSS are used, the input of the sense amplifier consisting of Q1 to Q4
The power terminal is connected to the output terminal of the sense amplifier consisting of Q12 to Q15
The voltage between those gates and sources is NMOS
Q2 is 1.5V and Q3 of the PMOS is -1.0V, which is higher than the threshold voltage.
Get higher in minutes. Therefore, data lines can be charged and discharged at high speed.
You. In principle, the minimum value of the data line voltage amplitude in this embodiment is
Is the maximum value of the gate-source voltage of the PMOS (Q3, Q4)
0.6V which is equal to the threshold. Therefore, the operating speed
Considering the degree, the practical voltage is about 0.8V. Book
According to the embodiment, it is also possible to make the low level of CHN negative.
Therefore, further increase the voltage between the gate and source of the PMOS.
Operation at a lower voltage. An example
For example, if the low level of CHN is -0.5V, normal operation is possible.
Data line voltage swing with a 0.8V
The width can be up to 0.3V. This is the sense amplifier
It is smaller than the threshold voltage of the transistor. At the time of precharge,
As in the first embodiment, the data lines are switched by the signal PC.
And precharge, but in this embodiment,
Show the output end of the sense amplifier consisting of both Q12 and Q15
And precharge. Q16, 17, and Q18 are
It is a ranista. This precharge voltage is VDH (1.5
0.75V which is half of V). Therefore, the precharge signal PC
May be set to 1.35 V or more. As mentioned above,
In the embodiment, the voltage amplitude of the data line is
Starts even if it is lower than the threshold voltage of the amplifier transistor
The voltage between the gate and source at the time should be higher than the threshold voltage.
High speed and low power consumption
Can be. Therefore, according to the present embodiment, lower power supply
A note that operates at pressure without significantly impairing speed performance
Re-circuit can be provided. The essence of the present invention is
Lower the voltage amplitude of the load capacitance signal line (here, the data line).
Operating thresholds of the elements that make up the driver circuit for that signal line.
Drive circuit with a large voltage amplitude that exceeds the
It is to be. Therefore, not only for sense amplifiers,
High speed and low power consumption by using different roads
It can provide power consumption LSI. Furthermore, limited to memory
In other LISs such as logic LSIs,
Can provide an LSI that operates at high speed. In addition, large / small electricity
By optimizing the combination of voltage amplitude and threshold voltage,
Thus, an LSI with higher speed and lower power consumption can be provided. example
For example, in FIG. 7 (a), a part of Q1 to Q4
It is possible to further increase the speed by using a MOS-FET
You. FIG. 8 shows an eighth embodiment of the present invention. Fig. 8
(A) is an outline of a circuit configuration of the present embodiment. This circuit
Controls the substrate voltage VBB of the sense amplifier transistor.
The threshold voltage is set to an optimum value for operation.
Therefore, MOS transistors for threshold voltage monitoring and
Reference voltage VR generation circuit, comparison circuit COMP, substrate voltage VBB generation time
It is composed of roads. The operation is described with reference to FIG.
Will be explained. MOS transistor changes the substrate voltage VBB
By doing so, the threshold voltage changes. For example,
In the case of NMOS, as shown in FIG.
The threshold voltage increases as the distance increases. Also, conversely
The smaller the value, the smaller it becomes. Set the sense amplifier to low voltage (1.0V
), The threshold voltage must be reduced as described above.
It works fast. Therefore, in this embodiment,
8 As shown in FIG.
Drive with constant current and the threshold current
And compare it with the reference voltage VR by the comparison circuit COMP.
The output controls the output voltage of the VBB generator circuit,
The threshold voltage of the power MOS transistor becomes equal to VR
I'm trying. By doing so, for example, MOS
Due to manufacturing variations, the transistor threshold voltage
The voltage at point b is higher than the optimum value indicated by point a in FIG.
Even lowering VBB to VB1 shifts to point d and VR
Can be equal to In addition, when it becomes low (the same
(Point c in Fig.) Is shifted to point e by raising VBB to VB2.
And can also be made equal to VR. Therefore,
According to the present embodiment, a stable sense
Pump can be realized. When operating the VR, the standard value (a
Point) lower (point f) and higher (point g) during standby
This allows both high-speed operation and low power consumption during standby.
Wear. A similar circuit is added to the PMOS well.
VR should be negative for NMOS and positive for PMOS during operation.
Depletion type transistor threshold power
On the other hand, during standby, the positive and negative
By adopting the instrument type, even higher speed and lower
Voltage swing is possible. Note that the operation cycle is short
When the pressure needs to be changed at high speed,
It is only necessary to separate the sense amplifier substrate using a well structure.
No. This makes it possible to reduce the power of the VBB generation circuit.
You. FIG. 8 (c) is a concrete example of FIG. 8 (a).
is there. QB1 and QB2 are monitoring MOS transistors, QB3 to QB
2 is a monitoring MOS transistor, QB3 to QB8 are comparison circuits,
OSC is the oscillation circuit of the VBB generation circuit, INV1, INV2, C2, C3, QB
9 to QB12 are VBB generation circuits. Here, the monitoring MOS
The reason that the transistors are connected in two stages is that
To get ass. Along with this, VR is a goal
It must be twice the threshold power. In addition, this moni
The number of transistor stages is not limited to two.
The number of stages may be set so that the input power is optimal. Also, the substrate
The rectifier circuit (C2, C3, QB9 to QB12)
In the embodiment, the voltage multiplier is used to increase the control range of the threshold voltage.
Pressure is generated by the sense amplifier.
The threshold voltage change rate with respect to the operating voltage and the substrate voltage.
You can change it later. As described above, this embodiment
According to the threshold voltage of the sense amplifier,
The value can be changed during operation and during standby.
Low-voltage, high-speed, low-power consumption DRAM
it can. Therefore, according to the present embodiment, the lower power supply voltage
Memory that works without significantly compromising speed performance
Circuit can be provided. In addition, the circuit is not limited to the sense amplifier.
High-speed and low-consumption by using differently for different applications
It can provide power LSI. Furthermore, not limited to memory,
Operates at lower voltage on other LSIs such as logic LSIs
LSI can be provided. It should be noted that the present invention, the operation of the element
The means for detecting the threshold voltage and the detection output
Control the value voltage to the optimal value for circuit operation
The present invention is not limited to the above-described circuit system. As described above, the present invention has been described by taking the DRAM as an example.
Random access memory (RA
M), or read-only memory (ROM), or even
Logic LSIs such as microcomputers
The present invention may be applied to a shift type LSI. Also, its constituents
Are bipolar transistors and MOS transistors
Data, combinations of these elements, or materials other than Si
For example, any of GaAs type transistors
Good.

【The invention's effect】

As described above, according to the present embodiment, it is possible to provide a memory circuit that operates even at a lower power supply voltage without significantly impairing the speed performance, and can be used as a battery backup memory or a battery operation memory. In addition, a high-speed and low-power-consumption LSI can be provided by selectively using not only the sense amplifier but also the application of the circuit. Furthermore, an LSI operating at a lower voltage can be provided not only in a memory but also in another LSI such as a logic LSI.

[Brief description of the drawings]

FIG. 1 (a) is a diagram showing a circuit configuration of a first embodiment of the present invention, FIG. 1 (b) is a diagram showing effects of the first embodiment of the present invention, FIGS. 1 (c) and 1 (c). (D) is a diagram showing characteristics of the transistor of the first embodiment of the present invention and a conventional transistor.
FIGS. 2E and 2F are diagrams showing a first embodiment of the present invention and a conventional operation waveform, FIG. 2A is a diagram showing a conventional circuit configuration, and FIGS. ) Is a diagram showing a conventional operation waveform,
FIG. 3A is a diagram showing a circuit configuration of a second embodiment of the present invention, FIG. 3B is a diagram showing operation waveforms of the second embodiment of the present invention, and FIG. 3C. , (G) are diagrams showing the concept and operation waveforms of the third embodiment, and FIGS. 3 (d) and (h) are diagrams showing another concept and operation waveforms of the third embodiment, and FIG. e) is the third
FIG. 3 (f) is a diagram showing the operation waveform of the third embodiment, and FIG. 4 (a) is a diagram showing the fourth embodiment of the present invention.
FIGS. 4 (b) and 4 (f) show operation waveforms of the fourth embodiment of the present invention, and FIG. 4 (c) shows a fourth embodiment of the present invention. FIGS. 4 (d) and 4 (e) show effects of the fourth embodiment of the present invention, and FIGS. 5 (a) and 5 (a) show a fifth embodiment of the present invention. FIG. 5B is a diagram showing a circuit configuration of the embodiment, FIG. 5B is a diagram showing operation waveforms of the fifth embodiment of the present invention, and FIG. 6A is a diagram showing a circuit configuration of the sixth embodiment of the present invention. FIG. 6 (b) is a diagram showing operation waveforms of the sixth embodiment of the present invention, and FIGS.
(B) is a diagram showing a circuit configuration and operation waveforms of a seventh embodiment of the present invention. FIGS. 8 (a) and (b) are diagrams showing a concept and an effect of the eighth embodiment of the present invention. FIG. 8C shows a specific circuit configuration of the eighth embodiment of the present invention. Explanation of the symbols Q1, Q2, Q3, Q4, Q1 ', Q2', Q3 ', Q4', Q12, Q13, Q14, Q15 ...
... Sense amplifier, Q5, Q6, Q7, Q5 ', Q6', Q7 ', Q16, Q17, Q1
8: Precharge circuit, Q8, Q9: Y gate, VP: Plate voltage terminal, CS: Storage capacitance, Q10, Q11: Memory cell switching transistor, PC: Precharge signal input terminal, VDP …… Precharge voltage, HVC …… VDD / 2
Voltage terminal, VDL: Data line charging voltage terminal, QP, QN, QP1, Q
P2, QN1, QN2 ...... Transistor for driving sense amplifier, VSS
… Ground voltage, AMP… Main amplifier, DIB… Din buffer, Dout… Information output terminal, Din… Information input terminal, W / R… Information input / output switching terminal.

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yoshinobu Nakagome 1-280 Higashi-Koikekubo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd. (72) Yoshiki Kawajiri 1-280 Higashi-Koikekubo, Kokubunji-shi, Tokyo Hitachi, Ltd. In the Central Research Laboratory of the Works (72) Inventor Kiyoo Ito 1-280 Higashi Koikekubo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory of the Hitachi, Ltd. (56) References JP-A-2-18784 (JP, A) (JP, A) JP-A-56-105389 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) G11C 11/407

Claims (6)

(57) [Claims] A plurality of memory cells provided at predetermined intersections between a plurality of data line pairs and a plurality of word lines; and a plurality of memory cells provided corresponding to each of the plurality of data line pairs.
A plurality of sense amplifiers for amplifying a signal voltage from a memory cell generated between one and the other of the corresponding data line pairs to a predetermined voltage, a common drive line pair for driving the plurality of sense amplifiers, A first terminal having one end connected to one of the common drive line pairs;
And a first drive unit for driving the other end of the first capacitor to a first voltage, during the amplification operation period of the plurality of sense amplifiers, between the one and the other of the common drive line pair. The semiconductor integrated circuit according to claim 1, wherein the voltage has a period in which the voltage is higher than the predetermined voltage by the first capacitor. 2. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit drives a second capacitor having one end connected to the other of the common drive line pair, and drives the other end of the second capacitor to a second voltage. And a second driving means for driving the semiconductor integrated circuit. 3. The voltage between one and the other of the common drive line pair during the amplifying operation period of the plurality of sense amplifiers, the other end of the first capacitor being set to the first voltage. A semiconductor integrated circuit, which is driven to drive the other end of the second capacitor to the second voltage so as to be higher than the predetermined voltage. 4. The semiconductor integrated circuit according to claim 1, further comprising switch means connected to one end of the common drive line pair and to supply the predetermined voltage to the other end. When one of the plurality of word lines is selected and a signal of the memory cell is read out to a corresponding data line pair, the switch means is turned on for a predetermined period, thereby causing one of the common drive line pair to be turned on. Is charged to the predetermined voltage, and thereafter, the other end of the first capacitor is driven to the first voltage, whereby one of the common drive line pairs is driven to a voltage higher than the predetermined voltage. A semiconductor integrated circuit characterized by the above-mentioned. 5. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit includes a plurality of first precharge circuits for precharging the plurality of data line pairs to a precharge potential, and the common drive line. A second precharge circuit for precharging the pair to the precharge potential, wherein the precharge potential is a half of the predetermined voltage, and the memory cell is a dynamic memory cell Semiconductor integrated circuit characterized by the following: 6. The plurality of sense amplifiers according to claim 1, wherein the plurality of sense amplifiers include a p-channel MOS transistor pair having a gate and a drain cross-coupled, and an n-channel MOS transistor having a gate and a drain cross-coupled. A semiconductor integrated circuit characterized by including a pair of type MOS transistors.