JP2929631B2 - Communication device between processors - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inter-processor communication system, and more particularly, to an inter-processor communication system for exchanging messages between a plurality of processors (multiprocessor system).

(Prior Art) FIG. 5 shows a system diagram of a conventional multiprocessor system using a shared memory. As is clear from the figure,
The multiprocessor system includes a shared memory 11 connected to a system bus 10 and a plurality of CPUs 1 to n. Each of the CPUs 1 to n is provided with a local memory.

As shown in FIG. 6, a number of message writing areas corresponding to the relationship between the sender and the receiver of the message are set in the shared memory 11. In the above case, since there are n CPUs, n × (n−1) message write areas are set. The address of the message writing area is recognized in advance by both communicating parties.

Now, in the multiprocessor system, when exchanging messages, the n processors operate equally. Now, when the CPUn sends a message to the CPU1, the CPUn writes the message in the area n → 1 of the shared memory 11 and sends an interrupt signal (n → 1) to the CPU1 to cause an interrupt.

As described above, when the CPUs 1 to n exchange messages equally, the messages are stored in the message writing area at a predetermined address of the shared memory 11, and each CPU has the information shown in FIG. Thus, (n-1) types of interrupt signals are input.

(Problems to be Solved by the Invention) When the number of CPUs connected to the system bus 10 of the multiprocessor system increases, the message writing area of the shared memory 11 and the types of interrupt signals greatly increase. That is, when the number of CPUs increases by 1, the message writing area of the shared memory 11 and the type of interrupt signal increase by n each.

The capacity of the shared memory 11 can be increased relatively easily by the advance of the memory technology. However, when the type of the interrupt signal increases, many hardware components are required to determine the type.

When the number of hardware components increases, not only does the device become large and expensive, but also depending on the type of system bus, the number of interrupt types is limited due to its specifications, making it impossible to implement.

An object of the present invention is to eliminate the problems of the conventional device, and
An object of the present invention is to provide an inter-processor communication method capable of minimizing an increase in the types of interrupt signals even when the number of U increases. For example, it is an object of the present invention to provide an inter-processor communication system in which, when the number of CPUs is increased by one, only the type of the interrupt signal needs to be increased by one.

(Means and Actions for Solving the Problems) In order to achieve the above object, the present invention provides an inter-processor communication system in which a plurality of processors and a shared memory that can be commonly accessed by the plurality of processors are connected via a system bus. Each of the plurality of processors includes a storage unit connected to the system bus for storing a received interrupt signal, a local bus connected to the system bus via a bus interface, and a same bus connected to the local bus. The first means for generating the same type of interrupt signal to which its own identification number is added for the interrupt destination, and the first means for transmitting the interrupt signal and the second means for reading the interrupt signal from the storage means and detecting the other party that has caused the interrupt. The feature is that the second means and the second means are provided.

According to the present invention, when the processor causes an interrupt, the processor sends a message to a predetermined area of the shared memory, and then transmits the interrupt signal added with the identification signal by the first means to the storage means of the destination processor. To send to.

On the other hand, the interrupted processor detects the interrupted partner by the second means connected to the local bus connected to the system bus via the bus interface, and performs necessary processing.

As a result, the interrupted processor can operate independently of the processing means connected to the local bus.
An interrupt request from another processor can be accepted, and there is no need to wait for another processor to issue an interrupt request.

(Example) Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a system block diagram of one embodiment of the present invention. In the figure, the same reference numerals as those in FIG. 5 denote the same or equivalent components.

As shown, connected to the system bus 10
The CPU 1 illustrated as a representative of the CPUs 1 to n generally includes a local bus 21, a CPU 22, a local memory 23, a bus interface 24, and an interrupt logic circuit 25.
Similarly, the local bus 31, CPU 32, local memory 33, bus interface 34 and interrupt logic
Consists of 35.

The shared memory 11 can be the same as the conventional one, and has nx (n-1) message write areas as described with reference to FIG. Although the number of entries in each message writing area may be one, a plurality of entries is preferable. The following description is made for a case where there are a plurality of entries.

The interrupt logic circuits 25 and 35 are composed of FIFO memories that store input data in the order in which they are received and output the data in that order.

Also, the local memory 33, as shown,
It has a processor use area, an interrupt use area, a message use area, and the like. The address of the area used at the time of the interrupt corresponds to the CPU that issues the interrupt.
When interrupting 1, for example, the address 1000H may be accessed. This means that the interrupt logic circuit 25 of the CPU 1 on the system bus 10 has been addressed. Address 10
When 00H is accessed, the interrupt signal goes through the local memory 33 → CPU 32 → bus interface 34 → bus 10,
It is sent to the interrupt logic circuit 25. Further, if the other CPU accesses the address 1000H of its own local memory, it means that the other CPU has interrupted the CPU 1 as described above. Therefore, the type of interrupt signal input to CPU1 is 1
Be kind.

Next, the operation of CPUn when interrupting CPU1 from CPUn will be described with reference to FIG. 1 and FIG. FIG. 2 is a flowchart showing the processing of the CPUn.

First, it is determined whether or not the area in the shared memory 11 (the n → 1 area in FIG. 6) corresponding to the processor to be interrupted is full (step S1).

If it is not full (No at Step S1), the CPU n first writes a necessary message to the entry of the shared memory 11 in the area corresponding to the processor to be interrupted (the n → 1 area) (Step S2).

This is performed by writing the necessary message in an area corresponding to the n → 1 area of the message use area of the local memory 33. The written message is stored in the local memory 33 → CPU 32 → bus interface 34 → bus 1
The data is sent to a predetermined area of the shared memory 11 via 0.

Next, it is determined whether or not the message is the first one (step S3). When the judgment is affirmative, the identification number of the own processor is added, and the other processor is interrupted (step S4). The interrupt signal with this identification number is stored in the other interrupt logic circuit, that is, in the FIFO memory.

The interrupted processor, for example, CPU1, recognizes that an interrupt has occurred by its own CPU 22 taking in the output of the interrupt logic circuit 25 via the bus interface 24.

If the step S3 is negative, that is, if the message is not the first one, a return is made, and the message is stored in the next entry of the area (n → 1 area) in the shared memory 11.

In this way, when all the entries in the area (n → 1 area) in the shared memory 11 are full of messages (step S1 is affirmative), an error code is set (step S5), and a message communication processing request is issued. Is rejected.

As described above, according to the present embodiment, the interrupting processor accesses the specific address (for example, 1000H when interrupting the CPU 1) of the local memory use area at the time of the interrupt. Since the interrupt can be made, the same kind of interrupt signal reaches the processor that can make the interrupt.

Further, when the same processor, for example, the CPUn interrupts a plurality of times, and the previously sent message remains in the n → 1 area, as is clear from the processing of the steps S3 and S4, the second and subsequent interrupts are performed. The processor identification number output at that time is the interrupt logic circuit 25 of CPU1,
Not sent to FO memory. As a result, it is understood that the FIFO memory only needs to have a maximum of (n-1) storage entries.

Next, the processor to be interrupted (the CPU
The process 1) will be described with reference to FIG.

As described above, other processors, such as CPUn to CP
When there is an interrupt in U1 (step S11), the contents of a predetermined register in CPU 1 are saved to another (step S12). Next, the CPU 1 determines whether or not the identification signal is stored in its own interrupt logic circuit 25, that is, in the FIFO memory. (Step S13). If the identification signal is stored in the FIFO memory (step S13
Is negative), the identification number is read from the FIFO memory (step S14), and the corresponding task is notified (step S1).
Five).

The task waits for the notification of the identification number of the interrupted processor (step S21), and upon receiving the notification of the identification number, reads the message from the entry 1 of the n → 1 area on the shared memory 11 (step S21). Step S22). Next, necessary processing for the message is performed (step
S23). Subsequently, it is determined whether or not a message is included in the entry 2 of the n → 1 area. (Step S23). On the other hand, if step S24 is positive, the process proceeds to step S21 to wait for notification of the identification number of the interrupted processor.

FIG. 4 shows that the interrupted processors CPU1 to CPUn are
The same interrupt signals (1) to (n) are received, and the identification numbers of the other processors are stored in the FIFO.

As described above, according to the present embodiment, when the interrupted processor CPU1 detects the interrupt signal, by reading the processor identification number from the FIFO memory, it is possible to immediately know which processor has issued the interrupt. When the identification number is passed to the task, the shared memory 11 is accessed from the identification number and the message is read. At this time, when a message is stored in a plurality of entries of the shared memory 11, the message is read out successively.

As is clear from the above description, the interruptable processors CPU1 to CPUn need only have one type of interrupt signal detecting means, unlike the conventional method.

In the above-described embodiment, the interrupt signal is generated by accessing a specific address of the local memory of the processor. However, the present invention is not limited to this, and the interrupt signal may be generated by another method. .

(Effects of the Invention) As is clear from the above description, according to the conventional method,
When the number of processors connected to the interprocessor communication system is n, increasing the number of processors by one increases the number of interrupt signals by n. However, according to the present invention, the number of interrupt signals increases by only one and a relatively small hardware There is an effect that efficient inter-processor communication can be realized by hardware.

Therefore, when the present invention is applied to an inter-processor communication system having a very large number of processors, or applied to an inter-processor communication system which does not have many interrupt types due to a limitation of a system bus or the like, the effect is particularly large.

Further, according to the present invention, since the first storage means for receiving and storing the interrupt signal is connected to the system bus and separated from the local bus, the operation of the processing means connected to the local bus is different from the operation of the processing means connected to the local bus. Irrespective of this, it is possible to receive an interrupt request from another processor, and it is possible to obtain an effect of not waiting for another processor to make an interrupt request.

[Brief description of the drawings]

FIG. 1 is a system block diagram of one embodiment of the present invention, and FIG.
FIG. 3 is a flowchart showing a process of a processor that issues an interrupt, FIG. 3 is a flowchart showing a process of a processor that has been interrupted, FIG. 4 is an explanatory diagram showing an interrupt signal input to each processor at the time of an interrupt, and an identification number; Fifth
FIG. 6 is a block diagram showing the entire system of the inter-processor communication system, FIG. 6 is a conceptual diagram showing a message writing area of a shared memory, and FIG. FIG. 4 is an explanatory diagram showing signals. 11: Shared memory, 22, 32: CPU, 23, 33: Local memory, 25, 35: Interrupt logic circuit (FIFO)

Claims (1)

(57) [Claims] An inter-processor communication device in which a plurality of processors and a shared memory commonly accessible by the plurality of processors are connected via a system bus, wherein each of the plurality of processors is connected to the system bus and receives an interrupt signal. A local bus connected to the system bus via a bus interface; and the same type of the same interrupt destination connected to the local bus and having its own identification number added thereto. An inter-processor communication device comprising: first means for generating and transmitting an interrupt signal; and second means for reading the interrupt signal from the storage means and detecting the other party that has caused the interrupt.