JP2927346B2 - Elastic store circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a two-port memory for reading data written to a first port from a second port. When a two-port memory is used, an approach between a read address and a write address is detected and both addresses are initialized. More particularly, the present invention relates to an elastic store circuit capable of detecting that an address approaches a predetermined value or more with a simple circuit and suppressing the frequency of initial setting.

[0002]

2. Description of the Related Art With the recent demand for higher speed and higher function of digital data transmission systems, an elastic store circuit for performing data speed conversion or delay adjustment is required to have higher speed and higher function. Therefore, an elastic store circuit using a two-port memory having independent input / output ports is used.

In such an elastic store circuit, the write operation and the read operation are performed by independent clocks. Therefore, the approach of the write address to the read address due to the phase shift of each clock is detected. Control is required to correct the read address so as not to overtake the write address.

Conventionally, in this type of elastic store circuit, a subtractor monitors each of a read address and a write address sent to a two-port memory and calculates a distance difference between the read address and the write address. The detection unit that detects that the predetermined value has been reached is notified of an initialization (hereinafter, referred to as initialization) signal to each address generation circuit, thereby updating the address interval between the read address and the write address to the initial state. Set and returned to maximum distance.

In this configuration, in order to determine a distance difference between a read address and a write address and determine whether the difference is within a specified value, accumulation, calculation, and comparison are required for two addresses. Is big.

A technique for reducing the circuit scale by eliminating this adder is described in, for example, Japanese Patent Application Laid-Open No. Hei 6-188938. In this circuit, when the read address coincides with the write address and the phase difference becomes zero, the read address counter and the write address counter are loaded with an address value having a predetermined value difference.

On the other hand, another technique realized by a simple circuit is described, for example, in Japanese Patent Application Laid-Open No. 7-250101.

[0008] This elastic store circuit:
This will be described with reference to FIG.

As shown, in this elastic store circuit, a read address generator 110 supplies a read address to the two-port memory 10, and a write address generator 120 supplies a write address.

The read address is monitored by read address decode unit 130 and read address decode unit 13
0 detects a preset reference address from the monitored read address and sends a pulse.

On the other hand, the write address is monitored by a write address decoding unit 140. The write address decode unit 140 writes a write address within a specified value before and after a reference address centered on the reference address sent from the read address decode unit 130. Monitoring is performed using the AND circuits corresponding to the number of addresses, and pulses are transmitted when the addresses match. The output pulses of these AND circuits are output from the OR circuit 150.
Are continuously transmitted to the AND circuit 160 in a range of specified values before and after the reference address.

The AND circuit 160 receives, on the one hand, a pulse having a reference address value at the center based on the write address from the OR circuit 150 continuously, and, on the other hand, receives from the read address decoding section 130 a pulse matching the reference address. , Output as an initial setting signal to the read address generation circuit 110 and the write address generation circuit 120.

When the read address generating circuit 110 and the write address generating circuit 120 receive an initial setting signal, predetermined initial value addresses are set, respectively.
The maximum distance difference is ensured.

According to this structure, the reference address extraction logic circuit in the read address decoding unit 130, the extraction logic circuit for the number of write addresses within a prescribed value before and after the reference address of the write address decode unit 140, and The predetermined process can be performed by determining the approach between the read address and the write address only by a simple logic circuit called the AND circuit 160.

[0015]

The above-mentioned conventional elastic store circuit has the following problems.

The first problem is disclosed in Japanese Patent Application Laid-Open No. HEI 6-188938.
In the circuit described in the above publication and the above description, the number of logic circuits for detecting the phase difference between the read address and the write address is large.

The reason for this is that the phase difference between the read address and the write address in the above-mentioned publication is determined and the phase difference detection circuit determines the magnitude of the phase difference between the specified value and the phase difference m. It is necessary to accumulate, subtract, and compare addresses, and in the circuit configuration described above, since the logic circuit of the write address decoding unit issues an initial setting signal, writing within a prescribed value centered on the reference value of the read address is required. This is because they are provided corresponding to the number of addresses.

The second problem is disclosed in JP-A-7-250101.
In the circuit described in the above publication and the above description, there is a high possibility that the frequency of initial setting is increased.

The reason is that only the means for initializing and updating the read address generation circuit and the write address generation circuit when approaching a reference value of a write address within a prescribed value centered on the reference value of the read address is used. Correspondingly, there is no other buffering treatment.

An object of the present invention is to avoid a state in which a read address and a write address match as much as possible, to simplify a circuit for detecting a difference between a read address and a write address, to reduce the circuit scale, and to reduce the initial size. It is an object of the present invention to provide an elastic store circuit that can suppress the frequency of setting of the activation setting.

[0021]

An elastic store circuit according to the present invention uses a two-port memory for reading data written to a first port from a second port, and detects an approach between a read address and a write address. In the elastic store circuit for correcting by initializing both addresses at the time, a reference value address is set to one of a read address and a write address, and this is detected and output. Detect and output an initial setting address value having a distance difference between addresses of a predetermined width centered on the value address and a stop control address value having a predetermined range adjacent on both sides outside the initial setting address value. When receiving the output of the initial setting address value when receiving the output of the reference value address, Sets the read address and the write address to the initial value of the maximum distance, and generates a predetermined control signal when receiving the output of the reference value address and receiving the output of the stop control address value. In addition, there is provided an address detection and control means for performing control for moving one of the read address and the write address to set the distance to a predetermined distance.

In this configuration, in addition to the initial setting address value, a stop control address value having a predetermined range is provided adjacent to both sides outside the initial setting address value, and only one address is corrected before the initial setting. Thus, the distance difference between the read address and the write address can be set to almost the maximum.

A specific elastic store circuit according to the present invention uses a two-port memory for reading data written to a first port from a second port, and detects an approach between a read address and a write address. In an elastic store circuit for correcting by initializing both addresses, a first register for fetching and storing constituent bits constituting one of a read address and a write address, and data stored in this register A first address decoding unit having a first AND circuit for outputting a pulse when the address matches the reference value address, and the other address for the address set by the first address decoding unit. Second register for fetching and storing constituent bits to be configured
A second address decode portion and a second AND circuit for generating and outputting the upper bits stored the previous SL reference value address initialization address value to the center value to the second register when the reference The output of the value address is
And an initial setting means for setting a read address and a write address to an initial value of a maximum distance when receiving the output of the initial setting address value from the second address decoding unit when receiving the output from the second address decoding unit. Prepared , more detailed
More specifically, the second address decoding section reads out the read address.
Address or write address.
Second register for capturing and storing the configuration bits to be generated
And an initial setting address having the reference value address as a median value.
Value and both sides of this initial setting address value.
Each of the two stop control address values that form the range,
Generated by upper bits stored in the second register
And three second AND circuits for outputting.
The control signal generating means is provided from the second address decoding unit.
Stop control addresses adjacent to both sides outside the initial setting address value
Receiving a predetermined control signal generated and output with the
Counter of the number of addresses that make up the
A fourth AND circuit for detecting almost half of the
After receiving the control signal, the detection output of the fourth AND circuit is output.
Send a stop signal to stop writing or reading until
And an output FF circuit with a set reset .

With this configuration, the approach between the read address and the write address can be detected and the two addresses can be initialized by the minimum number of logic circuits.

[0025]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a functional block diagram showing an embodiment of the present invention. In the elastic store circuit shown in FIG. 1, the two-port memory 10, the read address generation circuit 11, the write address generation circuit 12, the read address decode unit 13, the write address decode unit 14, the AND circuits 15 to 17, the write stop It is assumed that a signal generation circuit 18 and a read stop signal generation circuit 19 are provided.

The difference from the conventional FIG. 6 is that the write address decoding unit 14 has three outputs, and these three outputs are used to generate an initial setting signal, a write stop signal, and a read stop signal, respectively. That is, the signals are input to the three AND circuits 15 to 17, respectively, and the outputs of the AND circuits 16 and 17 are respectively supplied to the write stop signal generation circuit 18 and the read stop signal generation circuit 19 via the write stop signal and the read stop signal. Control signal generating means for generating and outputting each stop signal is provided.

The two-port memory 10 has two ports, not shown, an input port and an output port.

The read address generation circuit 11 generates a read address designating an address in the two-port memory 10 in which data to be output is stored from the output port of the two-port memory 10 and outputs the read address to the two-port memory 10. . Further, the read address generation circuit 11 sets an address to a predetermined initial value when receiving an initialization signal from the AND circuit 15, and receives a read stop signal from the read stop signal generation circuit 19. During this time, the output of the read address is stopped.

The write address generating circuit 12 generates a write address designating an address in the two-port memory 10 for storing data input from an input port of the two-port memory 10 and outputs the write address to the two-port memory 10. Also,
The write address generating circuit 12 sets an address to a predetermined initial value when receiving an initial setting signal from the AND circuit 15, and while receiving a write stop signal from the write stop signal generating circuit 18, The output of the write address shall be stopped.

The read address decoding unit 13 presets a reference read address B, and constantly monitors the read address output from the read address generation circuit 11 to the two-port memory 10, and sets the read address B as a reference. Pulses are output to the AND circuits 15 to 17 when they match.

The write address decoding section 14 preliminarily expresses the width of the reference address as the reference write address by using the lower bits of the write address, and the three types of addresses in which the upper bits following the lower bits are consecutively located in the upper bits. A value is set and each output is ANDed by the AND circuit 15.
17 to 17 have been input. Then, the write address decoding unit 14 constantly monitors the upper bits of the write address transmitted from the write address generation circuit 12 to the two-port memory 10, and when the upper bits match the preset reference write address. It is assumed that a pulse is output to a corresponding one of the AND circuits 15 to 17.

As reference values, an initial distance difference ". ± .a" between the addresses for initial setting and a distance difference "b" between both side addresses for performing the write control and the read control are set around the reference address value B. The address value width “B ± a” for the setting signal and the address value “B
The address value “〜B” for the write stop signal is provided on both sides of ± a ”.
− (A + b) ”and the address value“ 〜B + (a + b) ”for the read stop signal. It becomes a value from the value “0”.

In the initial state, the distance difference between the write address and the read address is set to be the maximum value A. For example, for the read address "0", the write address is, for example, "( A / 2) It is set to about the address. It is also assumed that the reference address set in the read address decoding unit is set so that the address "B" is an intermediate value in lower bits.

The AND circuit 15 reads a write address from the write address decode unit 14 at a position of width "B ± a", and reads the read address position and the reference read address B sent from the address decode unit 13 as a reference. Is output when the address matches, the read address generation circuit 11
In addition, it is sent to the write address generating circuit 12 as an initial setting signal, while being sent as an alarm signal to an alarm receiving section (not shown) of the transmission pointer.

The AND circuit 16 reads the write address from the write address decode unit 14 at the position of the width "B- (a + 1) to B- (a + b)", and sends out the read address position and the read address decode unit 13. When the read address B serving as the reference matches, the output of the match is output to the write stop signal generation circuit 18.

The AND circuit 17 reads a write address from the read address decode unit 13 at a position of width "B + (a + 1) to B + (a + b)", and reads the read address position and the reference sent from the address decode unit 13. When the read address B coincides with the read address B, the coincidence output is output to the read stop signal generation circuit 19.

When the write stop signal generation circuit 18 receives a drive pulse from the AND circuit 16, the write stop signal generation circuit 18 uses a clock having the same clock as the address counter, for example, "(A /
2) It is assumed that a write stop signal of -a "is generated and sent as a write stop signal to each of the write address generating circuit 12 and the write data output section (not shown) of the reception pointer.

When receiving a drive pulse from the AND circuit 17, the read stop signal generating circuit 19 generates a read stop signal having a clock width of "(A / 2) -a" by the same clock as that of the address counter, and reads the read stop signal. , Address generation circuit 1
1 and a read data input unit (not shown) for the transmission pointer (not shown).

Next, the operation function will be described with reference to FIG.

First, in the initial state, the distance difference between the write address and the read address becomes the maximum value A,
The write address is “A /
The address is set to about 2 ". Address B is set as a reference address to be set in the read address decoding unit 13 so that the lower bit becomes an intermediate value.

First, the read address decoding unit 13
When the read address value B is sent to the two-port memory 10, it is detected and output by one pulse.

On the other hand, the write address decoding unit 14
The address value “B ± a” for the initial setting signal, the address value “〜B− (a + b)” for the write stop signal on both sides of the address value “B ± a”, and the address value for the read stop signal When the write address value matches each of “〜B + (a + b)”, the corresponding AND circuit 15
To 17 are output.

Therefore, the fact that the output of the read address decode unit 13 and the output of the write address decode unit 14 temporally overlap means that both addresses are close and the distance is shortened.

When the reference read address B sent from the address decoding unit 13 at the position of the write address having the address width "B ± a" matches, the AND circuit 15 sends an initial setting signal and an alarm signal. You. The initialization signal is sent to the read address generation circuit 11 and the write address generation circuit 12, and the read address generation circuit 11 and the write address generation circuit 12 use the initialization signal to maximize the distance difference between the read address and the write address. Initial value is set. The alarm signal is sent to an alarm receiving unit (not shown) and is displayed as a predetermined alarm.

The address width "B- (a + 1) -B-
When the reference read address B sent from the address decoding unit 13 at the write address position of (a + b) "matches, the write stop signal is output from the write stop signal generation circuit 18 via the AND circuit 16 to the write address. The write address is sent to the generation circuit 12. The write address generation circuit 12, which has received the write stop signal, outputs the clock width "(A / 2)-
By stopping the writing in response to the write stop signal of a ″, the distance from the read address can be increased to near the maximum value.

On the other hand, the address width "B + (a + 1) to B +
When the reference read address B sent from the address decoding unit 13 at the position of the write address of (a + b) "matches, the read stop signal is output from the read stop signal generation circuit 19 via the AND circuit 17 to the read address. The read address is sent to the generation circuit 11. The read address generation circuit 11, which has received the read stop signal, outputs the clock width "(A / 2)-
By stopping the read operation in response to the read stop signal a ", the distance from the write address can be increased to near the maximum value.

Since the determination of the approach between the two read addresses and the write address is performed only once in one cycle of the write / read operation from address 0 to address A of the 2-port memory, it is set for the determination. After passing through the specified address, there is a possibility that the distance will fall within the reference distance difference. However, the reference distance difference in a range where the read address does not overtake the write address or the write address does not overtake the read address before the next determination is calculated and set in advance from the clock phase difference and the memory amount. I do.

In the above description, the reference address value B is set in the read address decoding unit, and the address value "B ± a" for the initial setting signal and the address value "B ± a"
, The address values for the write stop signal “〜B- (a
+ B) "and the address value" -B for the read stop signal
+ (A + b) "is set in the write address decode unit, but the read and write addresses are reversed, a reference address value B is set in the write address decode unit, and the address for the initial setting signal is set in the read address decode unit. A value, an address value for a write stop signal, and an address value for a read stop signal may be set and output.

In the above description, the functional blocks are illustrated and described. However, the logical product circuit may be combined with another logical circuit, and the function can be freely separated and merged as long as the above function is satisfied. It is not limited.

[0051]

Next, an embodiment of a read address decode unit 13 and a write address decode unit 14 embodied with reference to FIG. 1 and FIG. 2 will be described.

First, the two-port memory 10 has addresses "0" to "255" in an 8-bit configuration, and the value "a", which is the initial set address width, is substantially "8", and the stop control address width. The value "b" is set to substantially "16", and the distance difference "-7" to "+8" between the read address and the write address for initial setting, and the distance difference "-23" to "-8" for the write control. ", And distance differences" +9 "to" +24 "for performing read control are set.

It is assumed that the addresses forming the maximum distance in the initial state are a read address of 0 and a write address of 128.

The read address decoding unit 13
In the case where the reference address B is set to the address “23” of the intermediate value of the lower 4 bits, the condition of the initial setting output to the AND circuit 15 in the write address decoding unit 14 is the distance difference “−7”. The address is from address 16 to address 31 of "+8". Similarly, the condition of the write control output to the AND circuit 16 is 0 for the distance difference “−23” to “−8”.
It is assumed that the address is set from address 15 to address 15 and the condition of the read control output to the AND circuit 17 is set from address 32 to address 47 of the distance difference “+9” to “+24”.

The reference address value B at address 23 is set as follows:
This is determined by predicting a distance difference between both addresses which is expected to be close due to a phase difference and a frequency difference between reading and writing in each elastic store circuit.

As shown in FIG. 2, read address decode section 13 takes in a read address sent from read address generating circuit 11 to two-port memory 10.
It is assumed that a register 131 having a bit configuration and an AND circuit 132 that reads out 8 bits of the register 131 and outputs it at an address 23 are provided.

The write address decode section 14 is an 8-bit register 1 for taking in the write address sent from the write address generation circuit 12 to the two-port memory 10.
41, a logical product circuit 142 set to a code "0001" capable of reading the upper 4 bits from the 8 bits of the register 141 and outputting addresses 16 to 31 and a code capable of outputting addresses 0 to 15 It is assumed that an AND circuit 143 set to “0000” and an AND circuit 144 set to a code “0010” capable of outputting addresses 32 to 47 are provided.

Therefore, the logical product circuit 15 is the logical product circuit 1
If there is an output at address 23 from the AND circuit 132 during an output from address 42 to address 16 to address 31, an initial setting signal is output due to excessive proximity. AND circuit 16
When the AND circuit 132 outputs the address 23 while the AND circuit 143 outputs the address 0 to address 15, it outputs a write inhibit signal as a pulse just before the proximity. Similarly, the logical product circuit 17 includes the logical product circuit 144
AND circuit 13 during output from address 32 to address 47
If there is an output at addresses 2 to 23, a read-out prohibition signal is output as a pulse because it is just before proximity.

Next, referring to FIG. 3, write stop signal generation circuit 18 and read stop signal generation circuit 1 in FIG.
A ninth embodiment will be described.

As shown in FIG. 3A, the write stop signal generation circuit 18 is constituted by a 256-base counter 181, an AND circuit 182, and a flip-flop (hereinafter, referred to as FF) circuit 183.

The write stop signal generation circuit 18 receives the output pulse of the AND circuit 16 and inputs the output pulse to the L (Lord) terminal of the 256-base counter 181, and simultaneously, the FF circuit 18
3 is input to the Set terminal to set the circuit.

The AND circuit 182 has a 256-base counter 1
Upon receiving the output of 81, it decodes the counter value “120” and outputs it to the FF circuit 183. The FF circuit 183 converts the counter value “120” output from the AND circuit 182 into a Res
Input to et terminal to reset the circuit. As a result, the FF circuit 183 uses the used address 25 as a write stop signal.
It outputs a signal having an address of 5 and having a substantially intermediate value of 120 clocks.

Similarly, the read stop signal generation circuit 19 receives the output pulse of the AND circuit 17 and
The signal is input to the L (Lord) terminal 91 and simultaneously to the Set terminal of the FF circuit 193 to set the circuit.

The AND circuit 192 includes a 256-base counter 1
Receiving the output of 91, the counter value “120” is decoded and output to the FF circuit 193. The FF circuit 193 converts the counter value “120” output from the AND circuit 192 into a Res
Input to et terminal to reset the circuit. As a result, the FF circuit 193 uses the used address 25 as a read stop signal.
It outputs a signal having an address of 5 and having a substantially intermediate value of 120 clocks.

Next, referring to FIGS. 1 and 3 in addition to FIGS. 4 and 5, the output pulse of the AND circuit 132 of the read address decode unit 13 and the AND circuits 142 to 144 of the write address decode unit 14 will be described. The relationship with the output pulse is described.

As shown in FIG. 4A, the AND circuit 132 of the read address decoder 13 outputs one pulse when the read address is at address 23. The AND circuit 142 of the write address decoding unit 14 outputs a continuous pulse when the write address is between addresses 16 and 31. Similarly, each of the AND circuits 143 and 144 outputs a continuous pulse between the write addresses 0 to 15 and the addresses 32 to 47.

Then, in the initial state, FIG.
As shown in (1), since the distance difference between the read address and the write address is set to be the maximum, the pulse of the read address and the pulse of the write address do not coincide with the time history.

4 (B) and FIGS. 5 (A) and 5 (B), each operation of writing and reading is repeated, and the distance difference between the two addresses changes due to the phase difference of the clock of each operation. At the position of the reference read address where the difference is set, the distance difference “−23” to “−8” and the distance difference “−”
7 ”to“ +8 ”and the distance difference“ +9 ”to“ +24 ”, the corresponding AND circuit 1
Two inputs of any one of the AND circuits 5 to 17 are temporally coincident and output one pulse signal.

Next, as shown in FIG. 4B, the distance difference between the read address and the write address is "-7" to "+".
When the output from the AND circuit 142 at addresses 16 to 31 of 8 "is output at the address 30 and the address from the AND circuit 132 at address 23, the AND circuit 15 initializes one pulse at this time. The initial setting signal initializes the read address generation circuit 11 and the write address generation circuit 12 to return the distance difference between the read address and the write address to the maximum initial value.

In FIG. 5A, at the address 0 to 15 of the distance difference “−23” to “−8” between the read address and the write address, and at the output of the AND circuit 143, at the address 2,
When the address of the address 23 is output from the AND circuit 132, the AND circuit 16 outputs one pulse to the write stop signal generation circuit 18 at this time. Write stop signal generation circuit 1
8 outputs a write stop signal having a length of 120 clocks by this pulse as described above. The write stop signal is input to the write address generation circuit 12, and stops the generation of the write address for 120 clocks. As a result, the distance difference between the approaching read address and write address can be separated to near the maximum value.

Similarly, FIG. 5 (B) shows that the distance difference between the read address and the write address is from “+9” to “+24” at addresses 32 to 47, and that the output from the AND circuit 144 is 33
At the address, when the output from the AND circuit 132 to the address 23 is received, the AND circuit 17 reads one pulse at this time and outputs it to the stop signal generation circuit 19. As described above, the read stop signal generation circuit 19 generates 120
A read stop signal of a length corresponding to the clock is output. The read stop signal is input to the read address generation circuit 11 and stops the generation of the read address for 120 clocks. As a result, the distance difference between the approaching read address and write address can be separated to near the maximum value.

As described above, one reference value is set for the read address and the overlap is detected by giving the write address a width. Conversely, one reference value is set for the write address and the read address is set for the read address. The overlap may be detected with a certain width.

In the above description, the functional blocks are illustrated and described. However, as described above, the logical product circuit may be a combination of other logical circuits, and the function can be freely separated and merged as long as the above function is satisfied. The description is not intended to limit the invention.

[0074]

As described above, according to the present invention, the following effects can be obtained.

The first effect is that the number of logic circuits for detecting a phase difference between a read address and a write address is small, and a simple circuit can be used.

The reason is that a logic circuit necessary for generating the initial setting signal outputs two values, an initial setting range and a center reference address value, in an address decoding unit for a read address and a write address, and the output of these outputs. This is because only one for matching and three in total are required.

The second effect is an opportunity for initial setting,
That is, the frequency can be suppressed.

The reason is that a stop control range having a predetermined width is provided on both sides of the initial setting range, and when the distance difference between the read address and the write address approaches the stop control range, the stop control range is set before approaching the initial setting range. This is because the output of the read address or the write address is stopped, and the distance difference between the read address and the write address is set to a predetermined maximum width.

[Brief description of the drawings]

FIG. 1 is a functional block diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example of a part of FIG. 1;

FIG. 3 is a circuit diagram showing one embodiment of a portion of FIG. 1 which is different from FIG. 2;

FIG. 4 is a time chart for explaining an output relationship of FIG. 2;

FIG. 5 is a time chart for explaining the output relationship of FIG. 2 and a portion different from FIG. 4;

FIG. 6 is a functional block diagram showing an example of the related art.

[Explanation of symbols]

Reference Signs List 10 2-port memory 11 Read address generator 12 Write address generator 13 Read address decoder 14 Write address decoder 15-17, 131, 142-144, 182, 192
AND circuit 18 Write stop signal generation circuit 19 Read stop signal generation circuit 131, 141 Register 181, 191 256-base counter 183, 193 Flip-flop circuit (FF circuit)

Claims (4)

(57) [Claims] The data written to a first port is transmitted to a second port.
In an elastic store circuit that uses a two-port memory that reads from a port and detects an approach between a read address and a write address and initializes both addresses to make corrections, a reference is made to either the read address or the write address. A value address is set, detected and output, while the other address value has an initial address value having a distance difference of an address of a predetermined width centered on the reference address, and both sides of the initial address value. If adjacent the outer set each stop control address value having a predetermined range outputs detect these, and receives the output of the initial setting address value upon receiving an output of said reference value address Sets the read address and the write address to the initial value of the maximum distance, while the reference value address Wherein generating a predetermined control signal when receiving the output of the stop control address value upon receiving the output, performs control of setting a predetermined distance to stop one of the read and write addresses An elastic store circuit comprising address detection and control means. 2. The data written to a first port is transmitted to a second port.
In an elastic store circuit that uses a two-port memory that reads from a port and detects when an approach between a read address and a write address is detected and corrects both addresses by initial setting, either one of the read address and the write address A first address having a first register for taking in and storing the constituent bits constituting the first and a first AND circuit for taking out the data stored in the register and outputting a pulse when the data coincides with the reference value address a decoding unit, the initial setting address value of the second register and the previous SL reference value address for storing captures configuration bits constituting the other address to the first address the address set by the decode unit and the median From the upper bits stored in the second register. A second address decoding unit having an AND circuit, and receiving the output of the reference value address from the first address decoding unit and outputting the output of the initial setting address value to the second address decoding unit.
If received from the address decode portion, and an initial setting means for setting a read address and a write address to an initial value of the maximum distance, the second address decode unit is further the initial setting A
Two stop systems that form a predetermined range on both sides outside the dress value
Control address values are stored in the second register.
AND operation of the two logical products generated and output by the selected upper bits
Three second AND circuits in conjunction with the path and
From the second address decoding unit, the initial set address value
Generated and output with stop control address values adjacent on both sides outside
Receiving a predetermined control signal to configure the two-port memory
The counter of the number of addresses and almost half of this counter
A fourth AND circuit for detecting, and receiving the control signal
Then, write until the detection output of the fourth AND circuit is received.
Or a reset signal that sends a stop signal to stop reading
Control signal having an FF (flip-flop) circuit with
Elastic store circuit, characterized in Rukoto provided by adding No. generating means. 3. The data written to a first port is transferred to a second port.
In an elastic store circuit that uses a two-port memory that reads from a port and detects the approach between a read address and a write address and initializes both addresses to make corrections, a reference is made to either the read address or the write address. A first address decoding unit for setting, detecting and outputting a value address, and a predetermined width centered on the reference value address by the other address value with respect to the address set by the first address decoding unit. A second address decoding unit that detects and outputs an initial setting address value having a distance difference between addresses and a stop control address value having a predetermined range adjacent to both sides outside the initial setting address value; The output of the value address is
Initial setting means for setting a read address and a write address to an initial value of a maximum distance when receiving the output of the initial setting address value from the second address decoding unit when receiving the output of the initial setting address value from the address decoding unit; When receiving the output of the reference value address from the first address decoding unit and receiving the output of the stop control address value from the second address decoding unit, a predetermined control signal is generated, and the read address is read. and by moving one of the write address and a control signal generating means for controlling to set a predetermined distance, the second address decode portion, Oyo read address
Constitute the Izu Re or the other of the address of fine writing address
A second register for capturing and storing the configuration bits;
Initial address value with the reference value address as the median value,
And a predetermined range on both sides outside this initial setting address value.
Each of the two stop control address values to be formed is
2 is generated and output based on the upper bits stored in the second register.
Elastic store circuit, characterized in Rukoto a three second AND circuit that. 4. The data written to a first port is transmitted to a second port.
In an elastic store circuit that uses a two-port memory that reads from a port and detects the approach between a read address and a write address and initializes both addresses to make corrections, a reference is made to either the read address or the write address. A first address decoding unit for setting, detecting and outputting a value address, and a predetermined width centered on the reference value address by the other address value with respect to the address set by the first address decoding unit. A second address decoding unit that detects and outputs an initial setting address value having a distance difference between addresses and a stop control address value having a predetermined range adjacent to both sides outside the initial setting address value; The output of the value address is
Initial setting means for setting a read address and a write address to an initial value of a maximum distance when receiving the output of the initial setting address value from the second address decoding unit when receiving the output of the initial setting address value from the address decoding unit; When receiving the output of the reference value address from the first address decoding unit and receiving the output of the stop control address value from the second address decoding unit, a predetermined control signal is generated, and the read address is read. And control signal generating means for performing control for moving one of the write addresses and setting the write address to a predetermined distance , wherein the control signal generating means comprises a second address decoder.
Stop system adjacent to both sides of the initial setting address value from the unit
Receives a predetermined control signal generated and output with the
A counter for the number of addresses constituting the two-port memory;
A fourth AND circuit for detecting approximately 1/2 of this counter
Detecting the fourth AND circuit after receiving the control signal
Stop signal that stops writing or reading until an output is received
Elastic store circuit, characterized in Rukoto a set-reset with FF circuit for delivering items.