JP2920698B2 - Microprocessor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor, and more particularly, to a microprocessor having a high-speed movement of a stack pointer.

[0002]

2. Description of the Related Art Conventionally, in a microprocessor, a stack pointer is moved one by one in a positive direction or a negative direction by referring to a stack.

FIG. 3 shows the configuration of such a conventional microprocessor. The microprocessor 11 includes an instruction fetch unit 12 that fetches an instruction from a main storage device (not shown). This instruction fetch unit 12
The instruction fetched from is input to the instruction decoder 13,
Will be decrypted. The decoded instruction is used to reference the stack 14, and then the stack pointer 15 is incremented or decremented by one. When the next instruction is similarly fetched and decoded by the instruction decoder 13, the stack 14 at the position indicated by the stack pointer 15 is referred to, and the stack pointer 15 is further incremented or decremented by one. . The same applies hereinafter.

[0004]

As described above, in the conventional microprocessor, the operation of the stack pointer and the reference of the stack are linked. This means that data can be stored sequentially in a stack as a shelf-structured memory,
This operation was necessary when data was taken out in order.

However, for example, when the stack pointer is moved so as to jump out of some data stored in the stack and read out the desired data, the operation of referring to the stack and moving the stack pointer is repeated. You have to get to the data. That is, in this case, the operation of referring to the stack is uselessly performed, so that there is a problem that the speed of moving the stack pointer cannot be sufficiently increased.

An object of the present invention is to provide a microprocessor which can move a stack pointer at a high speed when it is not necessary to refer to the stack.

[0007]

According to the present invention, a stack for storing data in a stacking manner by a last-in first-out method, a stack pointer indicating a position of data to be referred to in the stack, and, for example, fetching an instruction from a main storage device. An instruction fetch unit to execute, and a first instruction for decoding a portion belonging to the first field in the fetched instruction and outputting an instruction for performing a stack reference and a stack pointer moving operation once each A microprocessor and a second instruction decoder that decodes a portion belonging to the second field in the fetched instruction and outputs an instruction indicating whether or not to perform one more stack pointer moving operation are provided to the microprocessor. To equip it.

In other words, according to the present invention, at the time of the normal operation of moving the stack pointer one by one by referring to the stack, only the part belonging to the first field in the fetched instruction is used. In other cases, the portion belonging to the second field is also used to move the stack pointer by two for one fetched instruction.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to embodiments.

FIG. 1 shows a configuration of a microprocessor according to an embodiment of the present invention. The microprocessor 21 includes an instruction fetch unit 22 that fetches an instruction from a main storage device (not shown). The instruction fetched from the instruction fetch unit 22 includes a first field and a second field.
Field is composed of two fields.
The first field has the same configuration as that of the conventional instruction, and its contents are input to the first instruction decoder 23. The second field was added by increasing the bit length of the instruction from the previous one,
The contents are input to the second instruction decoder 24.

The first instruction decoder 23 is basically the same as the conventional instruction decoder 13 shown in FIG.
That is, the instruction decoded by the first instruction decoder 23 is
This is for incrementing or decrementing the reference of the stack 25 and the stack pointer 26 by one.

The second instruction decoder 24 is used for controlling only the stack pointer 26. That is, the instruction decoded by the second instruction decoder 24 is the stack pointer 26
Is incremented or decremented by one, or such a moving operation is not performed.

When these two types of instructions are combined, the following three operations can be performed.

(A) Operation of the stack pointer 26 in conjunction with reference to the stack 25.

(B) An operation of moving the stack pointer 26 without referring to the stack 25.

(C) An operation for simultaneously moving the stack pointer 26 by two in the positive or negative direction while referring to the stack 25 by simultaneously performing the above (a) and (b).

FIG. 2 shows a state of such control of the microprocessor of the present embodiment. This will be described with reference to FIG.

First, the instruction fetch unit 22 fetches an instruction from a main storage device or a cache memory (not shown) (step S101). The part of this instruction belonging to the first field is sent to the first instruction decoder 23 (step S102), and the part belonging to the second field is sent to the second instruction decoder 24 (step S10).
3).

The first instruction decoder 23 checks whether this instruction is a stack reference (step S).
104), if so (Y), the stack data is referenced (step S105). Then, it is checked whether an operation of incrementing or decrementing the stack pointer 26 is instructed (step S1).
06) If instructed (Y), the operation is performed (step S107), and the control is terminated. When the stack reference is not performed in the previous step S104, and when the operation of the stack pointer 26 is not performed in the step S106, the control is terminated as it is (end).

On the other hand, the second instruction decoder 24 checks whether or not the instruction instructs the operation of incrementing or decrementing the stack pointer 26 (step S108). Is performed (step S109), and the control is terminated. If not instructed (N), the control is terminated as it is (END).

As a result of the above control, when both the first and second instruction decoders 23 and 24 decode the operation instruction of the stack pointer 26, they move two at a time in the positive or negative direction. Will be.

[0022]

As described above, according to the present invention, a second instruction decoder is provided in addition to the conventionally provided first instruction decoder, and the second instruction decoder also decodes the instruction for operating the stack pointer. Therefore, the stack pointer can be incremented or decremented twice at a time. In this case, the number of execution steps can be reduced by the amount corresponding to the dummy stack reference.
Further, according to the present invention, it is possible to operate only the stack pointer without referring to the stack using only the decoding result of the second instruction decoder.

[Detailed description of drawings]

FIG. 1 is a block diagram illustrating a main part of a circuit configuration of a microprocessor according to an embodiment of the present invention.

FIG. 2 is a flowchart illustrating a state of control of a microprocessor.

FIG. 3 is a block diagram illustrating an example of a configuration of a conventional microprocessor.

[Explanation of symbols]

 21 Microprocessor 22 Instruction Fetch Unit 23 First Instruction Decoder 24 Second Instruction Decoder 25 Stack 26 Stack Pointer

Claims (1)

(57) [Claims] A stack for storing data in a last-in first-out manner; a stack pointer indicating a position of data to be referred to in the stack; an instruction fetch unit for fetching an instruction;
A first instruction decoder that decodes a portion belonging to the field of the first instruction and outputs an instruction for performing the reference of the stack and the operation of moving the stack pointer once each, and a second instruction decoder in the extracted instruction. A second instruction decoder which decodes a portion belonging to the field and outputs an instruction indicating whether or not the operation of moving the stack pointer is performed once more.