JP2918087B2 - Multilayer wiring board for mounting semiconductor chips - Google Patents
Multilayer wiring board for mounting semiconductor chipsInfo
- Publication number
- JP2918087B2 JP2918087B2 JP5292572A JP29257293A JP2918087B2 JP 2918087 B2 JP2918087 B2 JP 2918087B2 JP 5292572 A JP5292572 A JP 5292572A JP 29257293 A JP29257293 A JP 29257293A JP 2918087 B2 JP2918087 B2 JP 2918087B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- wiring board
- multilayer wiring
- island
- mounting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/494—Connecting portions
- H01L2224/4943—Connecting portions the connecting portions being staggered
- H01L2224/49433—Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01046—Palladium [Pd]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、高密度実装に適した半
導体チップ搭載用多層配線基板に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring board for mounting a semiconductor chip suitable for high-density mounting.
【０００２】[0002]
【従来の技術】従来、半導体チップから外部への接続
は、一般的に、半導体チップにリードフレームのインナ
ーリードを接近させ、半導体チップの周辺部に設けられ
た外部導通用の電極パッドとインナーリードの先端部と
をボンディングワイヤーで接続したり、バンプ接合した
りすることにより行われている。2. Description of the Related Art Conventionally, a connection from a semiconductor chip to the outside is generally made by bringing an inner lead of a lead frame close to the semiconductor chip, and connecting an outer conduction electrode pad provided on a peripheral portion of the semiconductor chip to an inner lead. or connecting the tip with bonding wires, it has been made by or van-flop bonding.
【０００３】ところで、近年、半導体チップの高集積化
が進展するにつれて、半導体チップ内の配線ピッチ及び
半導体チップの周辺部に形成された外部導通用の電極パ
ッドのピッチのファイン化が顕著となってきており、そ
れに応じてリードフレームのインナーリードのピッチも
ファイン化することが求められている。In recent years, as the degree of integration of semiconductor chips has increased, the pitch of wiring in the semiconductor chip and the pitch of electrode pads for external conduction formed in the peripheral portion of the semiconductor chip have become remarkable. Accordingly, the pitch of the inner leads of the lead frame is required to be finer.
【０００４】ところが、リードフレームはエッチング法
やスタンピング法などにより製造されており、この場合
リード強度の点からインナーリードのピッチはリードフ
レーム材料の厚み、即ち０．１ｍｍ程度が限界となって
いる。このため、半導体チップの外部導通用の電極パッ
ドのピッチが０．１ｍｍより小さい場合、半導体チップ
の外部導通用の電極パッドとインナーリードとをバンプ
接合することは非常に困難となり、一方、ワイヤーボン
ディング法により両者の接続を行うときには、インナー
リードを半導体チップから遠ざけ、インナーリードピッ
チを広げ且つボンディングワイヤーを長くして接続して
いた。However, the lead frame is manufactured by an etching method, a stamping method, or the like. In this case, the pitch of the inner leads is limited to the thickness of the lead frame material, that is, about 0.1 mm in terms of lead strength. For this reason, when the pitch of the external conduction electrode pads of the semiconductor chip is smaller than 0.1 mm, it is very difficult to perform bump bonding between the external conduction electrode pads of the semiconductor chip and the inner leads. when performing both connections by law, away the inner leads from the semiconductor chip and are connected by long and bonding wires spread inner lead pitch.
【０００５】しかしながら、インナーリードを半導体チ
ップから遠ざけて、ボンディングワイヤーを長くする
と、特に樹脂封止工程時にワイヤー同士の短絡やワイヤ
ーの切断が生じやすくなるという問題がある。また、ワ
イヤー材料として使用する金は非常に高価なため、半導
体装置の製造コストが増大するという問題もある。更
に、ワイヤー自体が有するＬ成分やＣ成分も無視できな
くなるという問題がある。加えて、半導体装置の実装密
度が低下するという問題もある。However, when the inner leads are moved away from the semiconductor chip and the bonding wires are lengthened, there is a problem that short-circuiting of the wires and cutting of the wires are liable to occur particularly during the resin sealing step. In addition, since gold used as a wire material is very expensive, there is a problem that the manufacturing cost of a semiconductor device increases. Further, there is a problem that the L component and the C component of the wire itself cannot be ignored. In addition, there is a problem that the mounting density of the semiconductor device is reduced.
【０００６】このため、ワイヤーボンディング法により
半導体チップを外部に導通させる際に、半導体チップの
外部導通用の電極パッドのピッチがファイン化してもボ
ンディングワイヤーを長くすることなく導通させようと
することが試みられており、例えば、図５に示すよう
に、基板５０上の半導体チップ５１とインナーリード５
２との間に、絶縁シート５３上にスクリーン印刷などに
より比較的狭ピッチの配線パターン５４が形成されてい
る中継配線部材５５を配し、その半導体チップ５１を配
線パターン５４の先端部にボンディングワイヤー５６で
接続し、また、配線パターン５４の末端部にインナーリ
ード５２を半田や導電性接着剤あるいはスルーホールを
介して接続することが提案されている（特開昭５８−１
２２７６３号公報）。Therefore, when the semiconductor chip is electrically connected to the outside by the wire bonding method, even if the pitch of the external conductive electrode pads of the semiconductor chip becomes fine, the bonding wire may be made conductive without lengthening. For example, as shown in FIG. 5, a semiconductor chip 51 on a substrate 50 and an inner lead 5 are formed.
2, a relay wiring member 55 in which a wiring pattern 54 having a relatively narrow pitch is formed on the insulating sheet 53 by screen printing or the like, and the semiconductor chip 51 is attached to the tip of the wiring pattern 54 with a bonding wire. 56, and connecting the inner lead 52 to the end of the wiring pattern 54 via solder, a conductive adhesive, or through holes (Japanese Patent Application Laid-Open No. 58-1).
No. 22766).
【０００７】また、図６に示すように、アルミナ基板６
１上に厚膜導電ペーストからなるリード状の内部電極６
２を形成し、更に、その上に絶縁ペースト層６３を形成
し、その上に厚膜導電ペーストからなるリード状の外部
電極６４を内部電極６２に対して千鳥状となるように形
成し、半導体チップ５１と、内部電極６２又は外部電極
６４とをボンディングワイヤー６５で接続することも提
案されている（特開平４−３５４１４３号公報）。図５
もしくは図６に示したような構成とすることにより、半
導体チップの電極パッドに接続するボンディングワイヤ
ーを長くしなくても、その電極パッドに接続するリード
を電極パッドピッチのファイン化に対応させることが可
能となる。[0007] As shown in FIG.
1 is a lead-shaped internal electrode 6 made of a thick film conductive paste.
2, an insulating paste layer 63 is formed thereon, and a lead-shaped external electrode 64 made of a thick-film conductive paste is formed thereon so as to be staggered with respect to the internal electrode 62. It has also been proposed to connect the chip 51 to the internal electrode 62 or the external electrode 64 with a bonding wire 65 (Japanese Patent Application Laid-Open No. 4-354143). FIG.
Alternatively, by adopting the configuration shown in FIG. 6, the lead connected to the electrode pad can be made to correspond to the finer electrode pad pitch without lengthening the bonding wire connected to the electrode pad of the semiconductor chip. It becomes possible.
【０００８】[0008]
【発明が解決しようとする課題】しかしながら、特開昭
５８−１２２７６３号公報に記載された技術において
は、配線パターン５４が横並びとなっているので、配線
パターン５４のパターンピッチは、配線パターン５４の
幅とパターン間を絶縁するためのパターン間距離との和
となる。そのため配線パターン５４のパターンピッチは
そのパターン幅とパターン間距離に制約されてしまうと
いう問題があった。However, in the technique described in Japanese Patent Application Laid-Open No. 58-122763, since the wiring patterns 54 are arranged side by side, the pattern pitch of the wiring patterns 54 is It is the sum of the width and the distance between the patterns for insulating the patterns. Therefore, there is a problem that the pattern pitch of the wiring pattern 54 is restricted by the pattern width and the distance between the patterns.
【０００９】一方、特開平４−３５４１４３号公報に記
載された技術の場合には、内部電極６２と外部電極６４
との間に絶縁ペースト層６３が存在するために、内部電
極６２と外部電極６４とを千鳥状に配することができる
ので、特開昭５８−１２２７６３号公報に記載された技
術の場合に比べ、電極ピッチをファイン化させることが
可能となる。しかし、外部電極６４を形成する絶縁ペー
スト層６３の表面は、その下に内部電極６２が形成され
ているので平坦ではなく、従って外部電極６４をファイ
ンピッチで形成することは非常に困難であるという問題
があった。しかも、内部電極６２と外部電極６４との間
には段差があるために、バンプを利用してフリップチッ
プボンディング接続する場合にはその段差が障害とな
り、バンプの大きさを変化させなければならない等の問
題があった。On the other hand, in the case of the technique described in Japanese Patent Application Laid-Open No. 4-354143, an internal electrode 62 and an external electrode 64 are used.
Since the insulating paste layer 63 exists between the electrodes, the internal electrodes 62 and the external electrodes 64 can be arranged in a staggered manner, so that compared to the technique described in Japanese Patent Application Laid-Open No. 58-122763. In addition, the electrode pitch can be made finer. However, the surface of the insulating paste layer 63 forming the external electrodes 64 is not flat because the internal electrodes 62 are formed therebelow, and therefore, it is very difficult to form the external electrodes 64 at a fine pitch. There was a problem. In addition, since there is a step between the internal electrode 62 and the external electrode 64, the flip chip is formed using bumps.
In the case of pre-bonding connection, there is a problem that the step becomes an obstacle and the size of the bump must be changed.
【００１０】本発明は以上のような従来技術の問題点を
解決しようとするものであり、半導体チップと半導体チ
ップを搭載するための基板とを接続する際に、半導体チ
ップの周辺部に設けられた外部導通用の電極パッドピッ
チをファイン化し、且つバンプを利用してフリップチッ
プボンディングにより接続できるようにすることを目的
とする。An object of the present invention is to solve the above-mentioned problems of the prior art. When connecting a semiconductor chip to a substrate on which the semiconductor chip is mounted, a semiconductor chip is used.
Electrode pad for external conduction provided around the
The flip chip using bumps.
It is an object of the present invention to enable connection by bonding .
【００１１】[0011]
【課題を解決するための手段】本発明者は、半導体チッ
プを搭載する多層配線板表面に半導体チップ接続用端子
として島状端子を、半導体チップ搭載部に近接させて環
状に配し、且つその各島状端子にバイアホールを形成
し、そのバイアホールを介して各島状端子を多層配線板
の内層又は裏面の導電層に導通させ、且つ各島状端子同
士をそれらの間に実質的に段差が生じないように形成す
ることにより上述の目的が達成できることを見出し、本
発明を完成させるに至った。The inventor of the present invention has arranged island-shaped terminals as semiconductor chip connection terminals on the surface of a multilayer wiring board on which a semiconductor chip is mounted, in an annular shape close to the semiconductor chip mounting portion, and provided the same. A via hole is formed in each of the island-shaped terminals , and each of the island-shaped terminals is electrically connected to the inner layer or the conductive layer on the back surface of the multilayer wiring board via the via-hole.
The inventors have found that the above-mentioned object can be achieved by forming the layers so that there is substantially no step between them, and have completed the present invention.
【００１２】即ち、本発明は、半導体チップ搭載部及び
該半導体チップ搭載部の周囲に二列以上の環状に配され
た半導体チップ接続用端子群を表面に有する多層配線板
からなり、半導体チップをフリップチップボンディング
により実装するための半導体チップ搭載用多層配線基板
において、半導体チップ搭載部に最も近接して配された
環状の半導体チップ接続用端子群が島状端子からなり、
該島状端子にバイアホールが形成され、そのバイアホー
ルを介して各島状端子が多層配線板の内層又は裏面の導
電層に電気的に接続されており、該島状端子同士が実質
的に段差が存在しないように配されていることを特徴と
する半導体チップ搭載用多層配線基板を提供する。Namely, the present invention is a multilayer wiring board having a semiconductor chip mounting portion and the semiconductor chip connecting terminals arranged in two or more rows of annular around said semiconductor chip mounting portion on the surface, the semiconductor chip Flip chip bonding
In the multilayer wiring board for mounting a semiconductor chip for mounting according to the present invention, the ring-shaped semiconductor chip connection terminal group arranged closest to the semiconductor chip mounting portion is composed of island-shaped terminals,
Island-like terminal via hole is formed, the through via holes each island terminals are electrically connected to the inner layer or the back surface of the conductive layer of the multilayer wiring board, the island-like terminals to each other substantially
Provided is a multi-layer wiring board for mounting a semiconductor chip, wherein the multi-layer wiring board is arranged so that there is no step .
【００１３】[0013]
【作用】本発明のフリップチップボンディングにより実
装するための半導体チップ搭載用多層配線基板において
は、半導体チップ搭載部の周囲に最も近接して配されて
いる環状の半導体チップ接続用端子群が島状端子からな
り、その各島状端子にバイアホールが形成されている。
従って、その島状端子をバイアホールを介して多層配線
板の内層又は裏面の導電層に接続することが可能とな
る。このため、この島状端子は、バイアホールが形成で
きる程度の大きさとすれば足り、それらの大きさが、リ
ード状パターンの接続用端子を並列させるときのよう
に、パターン幅やパターン間距離に制約されることはな
い。よって、半導体チップ搭載部の周囲に高密度で島状
の半導体チップ接続用端子を配設することが可能とな
る。According to the present invention, the flip chip bonding of the present invention
In a multi-layer wiring board for mounting a semiconductor chip for mounting, a ring-shaped semiconductor chip connection terminal group arranged closest to the periphery of the semiconductor chip mounting portion is composed of island terminals, and each of the island terminals is Via holes are formed.
Therefore, the island-shaped terminal can be connected to the inner layer or the conductive layer on the back surface of the multilayer wiring board via the via hole. For this reason, it is sufficient that these island-shaped terminals are large enough to form via holes, and the size of the island-shaped terminals is limited to the pattern width and the distance between the patterns, such as when connecting the connection terminals of the lead-shaped pattern. You are not restricted. Therefore, it is possible to arrange high-density island-shaped semiconductor chip connection terminals around the semiconductor chip mounting portion.
【００１４】また、本発明の半導体チップ搭載用多層配
線基板においては、バイアホールが形成された半導体チ
ップ接続用の島状端子を二列以上の環状に設け、更に半
導体チップ接続用のリード状端子を設けることができる
が、この場合に、それぞれの端子を同一表面に形成して
それらの間に実質的に段差がないようにする。従って、
半導体チップをバンプを介して容易にフリップチップボ
ンディングできる。 In the multi-layer wiring board for mounting a semiconductor chip according to the present invention, two or more rows of island-shaped terminals for connecting a semiconductor chip having via holes are provided in a ring shape, and further, lead-shaped terminals for connecting a semiconductor chip are provided. can be provided, in this case, you as no substantial difference in level respectively between to <br/> thereof formed on the same surface terminal. Therefore,
The semiconductor chip can be easily flip-chip bonded via the bump .
【００１５】しかも、バイアホールが形成された半導体
チップ接続用の島状端子の周囲に、半導体チップ接続用
のリード状端子を、島状端子に対して千鳥状となるよう
に形成することにより、多層配線板の表面も有効に利用
し、スルーホールの開孔の手間や、多層配線板の多層度
を軽減し、製造コストを低減させることが可能となる。Further , by forming lead-shaped terminals for connecting a semiconductor chip around the island-shaped terminals for connecting a semiconductor chip having via holes formed therein, the lead-shaped terminals for connecting the semiconductor chips are formed in a zigzag manner with respect to the island-shaped terminals. The surface of the multilayer wiring board can also be effectively used, and the labor required for opening through holes and the degree of multilayering of the multilayer wiring board can be reduced, and the manufacturing cost can be reduced.
【００１６】[0016]
【実施例】以下、本発明を図面に基づいて詳細に説明す
る。なお、各図において同じ符号は同一又は同等の構成
要素を示している。なお、図４（ａ）は、本発明の半導
体チップ搭載用配線基板の断面図であり、図４（ｂ）は
その平面図である。また、図１〜図３は、本発明の半導
体チップ搭載用配線基板の特徴を説明するための参考図
である。 DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings. In each of the drawings, the same reference numerals indicate the same or equivalent components. FIG. 4A shows a semiconductor device according to the present invention.
FIG. 4B is a cross-sectional view of the wiring board for mounting the body chip, and FIG.
It is the top view. 1 to 3 show a semiconductor device according to the present invention.
Reference diagram for explaining the features of the wiring board for mounting the body chip
It is.
【００１７】まず、参考のための半導体チップ搭載用多
層配線基板に半導体チップを搭載した場合の断面図を図
１（ａ）に、そして平面図を図１（ｂ）に示す。同図に
あるように、半導体チップ搭載用多層配線基板は、半導
体チップ搭載部１及び該半導体チップ搭載部１の周囲に
環状に配された複数の半導体チップ接続用の島状端子２
を表面に有する多層配線板３から構成されている。Firstly, the cross-sectional view of a case of mounting a semiconductor chip on a semiconductor chip mounting multilayer wiring board for reference in FIG. 1 (a), and shows a plan view in FIG. 1 (b). As shown in the figure, a multilayer wiring board for mounting a semiconductor chip comprises a semiconductor chip mounting portion 1 and a plurality of island-shaped terminals 2 for connecting semiconductor chips arranged in a ring around the semiconductor chip mounting portion 1.
On the surface of the multilayer wiring board 3.
【００１８】ここで、島状端子２には、多層配線板３の
裏面にまでスルーホールｔｈ１が形成されており、その
スルーホールｔｈ１を介して島状端子２が裏面の導電層
４に接続されている。これにより、この島状端子２の近
傍に別の半導体チップ接続用端子群、例えば、島状端子
や後述するリード状端子７を形成することができ、従っ
て、半導体チップ接続用の島状端子２だけではなく他の
半導体チップ接続用端子も短いボンディングワイヤー５
で半導体チップ６の電極パッドと接続することができ
る。Here, a through hole th1 is formed in the island-shaped terminal 2 to the back surface of the multilayer wiring board 3, and the island-shaped terminal 2 is connected to the conductive layer 4 on the back surface through the through hole th1. ing. Thus, another terminal group for connecting a semiconductor chip, for example, an island terminal or a lead terminal 7 described later can be formed in the vicinity of the island terminal 2. Bonding wire 5 that is not only short but also has other semiconductor chip connection terminals
Can be connected to the electrode pads of the semiconductor chip 6.
【００１９】また、島状端子２には、基板表面で配線パ
ターンを直接接続する必要がないので、この島状端子の
大きさとしてはスルーホールが形成できるだけの大きさ
とすれば足りる。Since there is no need to directly connect a wiring pattern to the island-shaped terminals 2 on the surface of the substrate, the size of the island-shaped terminals is only required to be large enough to form a through hole.
【００２０】島状端子２の形状としては、図２に示すよ
うに、スルーホールｔｈ１の開口部の周囲にボンディン
グエリア２ｃを拡大させた形状とすることができる。ま
た、必要に応じて、スルーホール内に硬化型樹脂をスク
リーン印刷などで充填し、それを覆うようにメッキ法な
どで形成しアイランド形状としてもよい。As shown in FIG. 2, the shape of the island-shaped terminal 2 can be such that the bonding area 2c is enlarged around the opening of the through hole th1. If necessary, the through-hole may be filled with a curable resin by screen printing or the like, and may be formed by plating or the like so as to cover the through-hole to form an island shape.
【００２１】なお、スルーホールｔｈ１の代わりにブラ
インドバイアホールを形成し、多層配線板の内層に接続
してもよい。Note that a blind via hole may be formed in place of the through hole th1 and connected to the inner layer of the multilayer wiring board.
【００２２】また、図１の参考例においては、島状端子
２の周囲に、他の半導体チップ接続用のリード状端子７
が形成されており、その末端部はスルーホールｔｈ２で
多層配線板３の裏面に導通されている。この場合、図１
（ｂ）に示すように、島状端子２とリード状端子７とを
千鳥状に配することが好ましい。これにより、ボンディ
ングワイヤーの短絡を防止し、更により高密度実装が可
能となる。なお、リード状端子７は必要に応じて省略す
ることもできる。In the reference example shown in FIG. 1, a lead-like terminal 7 for connecting another semiconductor chip is provided around the island-like terminal 2.
Is formed, and the end is electrically connected to the back surface of the multilayer wiring board 3 through the through hole th2. In this case, FIG.
As shown in (b), it is preferable to arrange the island-shaped terminals 2 and the lead-shaped terminals 7 in a staggered manner. As a result, short-circuiting of the bonding wires can be prevented, and higher-density mounting can be achieved. Note that the lead terminals 7 can be omitted as necessary.
【００２３】図１に従って説明した半導体チップ搭載用
多層配線基板は、裏面で半田バンプなどを介してマザー
ボードに接続される。The multilayer wiring board for mounting a semiconductor chip described with reference to FIG. 1 is connected to the motherboard via solder bumps or the like on the back surface.
【００２４】次に、半導体チップ搭載用多層配線基板の
別の参考例に半導体チップを搭載した場合の断面図を図
３（ａ）に、そして平面図を図３（ｂ）に示す。この参
考例は、多層配線板３の周縁部に外部導通用リード８
が、熱圧着法などにより接続された例であり、図１の参
考例の場合に比べ、リード状端子７にスルーホールを設
けず、且つ島状端子２と外部接続用リード８とを二つの
スルーホールｔｈ１及びｔｈ３を介して接続したもので
ある。この半導体チップ搭載用多層配線基板は、外部導
通用リード８を介してマザーボードに接続される。 [0024] Next, a cross-sectional view in the case of mounting the semiconductor chip to another reference example of a semi-conductor chip mounting multilayer wiring board in FIG. 3 (a), and shows a plan view in FIG. 3 (b). This ginseng
The example is that the external conduction leads 8 are provided on the periphery of the multilayer wiring board 3.
There is an example that is connected by thermal compression bonding method, participation in Fig 1
Compared with the case of the example, the through terminal is not provided in the lead terminal 7, and the island terminal 2 and the external connection lead 8 are connected via two through holes th1 and th3. This multilayer wiring board for mounting a semiconductor chip is connected to a motherboard via external conduction leads 8.
【００２５】以上、説明した半導体チップ搭載用多層配
線基板の参考例は、いずれも島状端子が一列の環状とな
っているが、本発明においては二列以上の環状になるよ
うに設ける。この場合には、外側の半導体チップ接続用
の島状端子群にもそれぞれバイアホールを形成すること
が好ましい。また、より高密度の実装を実現するため
に、各環状の半導体チップ接続用端子を千鳥状に配する
ことが好ましい。The above reference example of semiconductor chip mounting multilayer wiring substrate described is either an island-shaped terminal has a circular single row, Ru provided so that two or more rows of annular in the present invention. In this case, it is preferable to form a via hole in each of the outer island-shaped terminal groups for connecting the semiconductor chip. In addition, in order to realize higher-density mounting, it is preferable to arrange the annular semiconductor chip connection terminals in a staggered manner.
【００２６】本発明の半導体チップ搭載用多層配線基板
においては、半導体チップ接続用の島状端子２同士又は
半導体チップ接続用島状端子２とリード状端子７とを、
実質的に段差が存在しないように配する。従って、半導
体チップをワイヤーボンディング法ではなく、バンプを
介して容易にフリップチップボンディングすることがで
きる。例えば、半導体チップ接続用の島状端子を二列環
状に配し、その外側にリード状端子を配した場合、その
部分断面図である図４（ａ）及び部分平面図である図４
（ｂ）に示すように、島状端子２ａ、２ｂ及びリード状
端子７を互いに千鳥状に配し、バンプ９を介して半導体
チップ６を島状端子２ａ、２ｂ及びリード状端子７に接
続すればよい。このとき、内側の島状端子２ａは多層配
線板３の裏面にスルーホールｔｈ１を介して接続し、外
側の島状端子２ｂは、ブラインドバイアホールｂｈで多
層配線板３の内層の導電層に接続することにより、より
高密度実装を実現することができる。なお、図４（ｂ）
において半導体チップ６は点線で示されている。[0026] In the semiconductor chip multilayer wiring board for mounting of the present invention, the island-shaped terminals 2 or between the semiconductor chip connecting island terminals 2 and lead-shaped terminals 7 for the semiconductor chip connection,
That substantially HSS so there is no difference in level. Therefore, the semiconductor chip can be easily flip-chip bonded via the bumps instead of the wire bonding method. For example, when island-shaped terminals for connecting a semiconductor chip are arranged in two rows and annularly arranged, and lead-shaped terminals are arranged outside thereof, FIG. 4A which is a partial cross-sectional view and FIG.
As shown in (b), the island-shaped terminals 2a, 2b and the lead-shaped terminals 7 are arranged in a zigzag pattern, and the semiconductor chip 6 is connected to the island-shaped terminals 2a, 2b and the lead-shaped terminals 7 via bumps 9. I just need. At this time, the inner island terminals 2a are connected to the back surface of the multilayer wiring board 3 via the through holes th1, and the outer island terminals 2b are connected to the inner conductive layers of the multilayer wiring board 3 through blind via holes bh. By doing so, higher density mounting can be realized. FIG. 4 (b)
5, the semiconductor chip 6 is indicated by a dotted line.
【００２７】また、本発明の半導体チップ搭載用多層配
線基板の半導体チップ搭載部は一つに限られず、二つ以
上の半導体チップを搭載するように複数の半導体チップ
搭載部を設けてもよい。この場合、少なくとも一つの半
導体チップ搭載部の周囲の半導体チップ搭載用端子群を
上述のように、バイアホールを有する島状端子から構成
すればよい。The semiconductor chip mounting portion of the multilayer wiring board for mounting a semiconductor chip of the present invention is not limited to one, and a plurality of semiconductor chip mounting portions may be provided so as to mount two or more semiconductor chips. In this case, the terminal group for mounting the semiconductor chip around at least one semiconductor chip mounting portion may be composed of island-shaped terminals having via holes as described above.
【００２８】半導体チップをフリップチップボンディン
グにより実装するための本発明の半導体チップ搭載用多
層配線基板は、公知の材料と方法を利用することにより
製造することができる。例えば、以下に説明する図１に
示した半導体チップ搭載用多層配線基板と同様に製造す
ることができる。A semiconductor chip is flip-chip bonded.
The multi-layer wiring board for mounting a semiconductor chip of the present invention for mounting by means of mounting can be manufactured by using known materials and methods. For example, it can be manufactured similarly to the multilayer wiring board for mounting a semiconductor chip shown in FIG. 1 described below .
【００２９】まず、ＢＴ樹脂含浸ガラスクロス、ガラス
エポキシ、ポリイミド、セラミック、ガラスなどの絶縁
基板の両面に銅箔を貼り合わせた多層配線板３の半導体
チップ搭載部１の周囲にドリルで開孔し、孔内に銅メッ
キを施しスルーホールｔｈ１及びｔｈ２を形成する。First, holes are drilled around the semiconductor chip mounting portion 1 of the multilayer wiring board 3 in which copper foil is bonded to both surfaces of an insulating substrate made of BT resin impregnated glass cloth, glass epoxy, polyimide, ceramic, glass, or the like. Then, copper plating is performed in the holes to form through holes th1 and th2.
【００３０】次に、フォトリソグラフ法により多層配線
板の両面の銅箔をパターニングしてリード状端子７、導
電層４、島状端子２を形成する。リード状端子７の半導
体チップ搭載部１側の先端部は、ボンディングワイヤー
あるいはバンプが接続されるので、通常、その表面に３
〜５μｍ厚のニッケルメッキ層を形成した後、更に約
０．３〜０．５μｍ厚の金やパラジウムなどの貴金属メ
ッキ層を形成することが好ましい。Next, the copper foil on both sides of the multilayer wiring board is patterned by photolithography to form the lead-like terminal 7, the conductive layer 4, and the island-like terminal 2. Since a bonding wire or a bump is connected to the tip of the lead terminal 7 on the side of the semiconductor chip mounting portion 1, usually 3
After forming a nickel plating layer having a thickness of about 5 μm, it is preferable to further form a noble metal plating layer such as gold or palladium having a thickness of about 0.3 to 0.5 μm.
【００３１】なお、島状端子２に図２に示したようなボ
ンディングエリア２ａを形成しないような場合には、ス
ルーホールｔｈ１の開孔部をスクリーン印刷法などを利
用して熱硬化性樹脂で塞ぎ、その上にメッキ層を形成し
てボンディングエリアとすることが好ましい。これによ
り、島状端子をより小さくすることができ、高密度化が
可能となる。この場合、ボンディングエリアを確保する
ことが目的なので、スルーホールｔｈ１の内部すべてに
熱硬化性樹脂を充填する必要はない。スルーホールｔｈ
１を熱硬化性樹脂で塞いだ場合には、硬化後に表面研磨
を行って、樹脂面を平滑にしてメッキ層を形成しやすく
することが好ましい。また、このようなメッキ層は、通
常、樹脂面に銅メッキ層、ニッケルメッキ層及び金メッ
キ層を順次形成した多層メッキ層とすることが好まし
い。In the case where the bonding area 2a as shown in FIG. 2 is not formed in the island-shaped terminal 2, the opening of the through hole th1 is made of a thermosetting resin by using a screen printing method or the like. It is preferable to close and form a plating layer thereon to form a bonding area. As a result, the size of the island-shaped terminals can be reduced, and the density can be increased. In this case, since the purpose is to secure a bonding area, it is not necessary to fill the entire inside of the through hole th1 with a thermosetting resin. Through hole th
When 1 is covered with a thermosetting resin, it is preferable to polish the surface after curing to smooth the resin surface and facilitate the formation of a plating layer. Further, it is preferable that such a plating layer is usually a multilayer plating layer in which a copper plating layer, a nickel plating layer, and a gold plating layer are sequentially formed on a resin surface.
【００３２】なお、スルーホールｔｈ１の代わりにブラ
インドバイアホールを利用する場合には、一般に、積層
工程においてプリプレグによりホール内部が塞がれるの
で、改めて熱硬化性樹脂の充填操作を行わなくてもその
上にメッキ層を形成し、ボンディングエリアを形成する
ことができる。ホールの開孔部表面からプリプレグがは
み出した場合には、上述した場合と同様に、表面研磨を
行うことが好ましい。When a blind via hole is used in place of the through hole th1, the inside of the hole is generally closed by a prepreg in the laminating step. A bonding area can be formed by forming a plating layer thereon. When the prepreg protrudes from the surface of the hole, it is preferable to polish the surface as in the case described above.
【００３３】以上説明したような製造方法に準じ、半導
体チップをフリップチップボンディングにより実装する
ための本発明の半導体チップ搭載用多層配線基板を製造
することができる。According to the manufacturing method described above, the semiconductor
Mounting the body chip by flip chip bonding
Of the present invention can be manufactured.
【００３４】[0034]
【発明の効果】本発明の半導体チップ搭載用多層配線基
板によれば、半導体チップの周辺部に設けられた外部導
通用の電極パッドのピッチがファイン化した場合でも、
半導体チップを容易にバンプ接続することができる。従
って、本発明の半導体チップ搭載用多層配線基板を使用
することにより高密度実装の半導体装置を提供すること
ができる。According to the multilayer wiring board for mounting a semiconductor chip of the present invention, even when the pitch of the electrode pads for external conduction provided in the peripheral portion of the semiconductor chip becomes fine ,
The semi-conductor chip can be easily bump connection. Therefore, by using the multilayer wiring board for mounting a semiconductor chip of the present invention, it is possible to provide a high-density mounting semiconductor device.
【図１】半導体チップ搭載用多層配線基板に半導体チッ
プを搭載した場合の断面図（図１（ａ））と平面図（図
１（ｂ））である。FIG. 1 is a cross-sectional view (FIG. 1A) and a plan view (FIG. 1B) when a semiconductor chip is mounted on a multilayer wiring board for mounting a semiconductor chip.
【図２】半導体チップ接続用の島状端子の拡大平面図で
ある。FIG. 2 is an enlarged plan view of an island-shaped terminal for connecting a semiconductor chip.
【図３】半導体チップ搭載用多層配線基板に半導体チッ
プを搭載した場合の断面図（図３（ａ））と平面図（図
３（ｂ））である。3A and 3B are a cross-sectional view (FIG. 3A) and a plan view (FIG. 3B) when a semiconductor chip is mounted on a multilayer wiring board for mounting a semiconductor chip.
【図４】本発明の半導体チップ搭載用多層配線基板の断
面図（図４（ａ））と平面図（図４（ｂ））である。FIG. 4 is a cross-sectional view (FIG. 4A) and a plan view (FIG. 4B) of the multilayer wiring board for mounting a semiconductor chip of the present invention.
【図５】従来の半導体チップ搭載用配線基板の説明図で
ある。FIG. 5 is an explanatory view of a conventional wiring board for mounting a semiconductor chip.
【図６】従来の半導体チップ搭載用配線基板の説明図で
ある。FIG. 6 is an explanatory view of a conventional wiring board for mounting a semiconductor chip.
１ 半導体チップ搭載部 ２、２ａ、２ｂ 半導体チップ接続用の島状端子 ２ｃ ボンディングエリア ３ 多層配線板 ４ 導電層 ５ ボンディングワイヤー ６ 半導体チップ ７ リード状端子 ８ 外部導通用リード ９ バンプ ｔｈ１、ｔｈ２、ｔｈ３ スルーホール、 ｂｈ ブラインドバイアホール DESCRIPTION OF SYMBOLS 1 Semiconductor chip mounting part 2, 2a, 2b Island terminal for semiconductor chip connection 2c Bonding area 3 Multilayer wiring board 4 Conductive layer 5 Bonding wire 6 Semiconductor chip 7 Lead terminal 8 External conduction lead 9 Bump th1, th2, th3 Through hole, bh blind via hole
Claims (3)
搭載部の周囲に二列以上の環状に配された半導体チップ
接続用端子群を表面に有する多層配線板からなり、半導
体チップをフリップチップボンディングにより実装する
ための半導体チップ搭載用多層配線基板において、半導
体チップ搭載部に最も近接して配された環状の半導体チ
ップ接続用端子群が島状端子からなり、該島状端子にバ
イアホールが形成され、そのバイアホールを介して各島
状端子が多層配線板の内層又は裏面の導電層に電気的に
接続されており、該島状端子同士が実質的に段差が存在
しないように配されていることを特徴とする半導体チッ
プ搭載用多層配線基板。1. A a multilayer wiring board having a semiconductor chip mounting portion and the semiconductor chip mounting portion surface of the semiconductor chip connecting terminals arranged in two or more rows of annular around, semiconductors
Mounting the body chip by flip chip bonding
In the semiconductor chip mounting multilayer wiring board, a ring-shaped semiconductor chip connection terminal group disposed closest to the semiconductor chip mounting portion is formed of island-shaped terminals, and a via hole is formed in the island-shaped terminals. Each island-shaped terminal is electrically connected to the inner layer or the conductive layer on the back surface of the multilayer wiring board through the via hole, and the island-shaped terminals have substantially steps.
A multilayer wiring board for mounting a semiconductor chip, wherein the multilayer wiring board is arranged so as not to be disposed .
周囲に、半導体チップ接続用のリード状端子が該島状端
子に対して千鳥状となるように形成されており、該リー
ド状端子も該島状端子に対して実質的に段差が存在しな
いように配されている請求項１記載の半導体チップ搭載
用多層配線基板。Around 2. A via hole islands terminal group formed, lead-shaped terminals for the semiconductor chip connection are formed so as to be staggered with respect to the island-shaped terminal, said Lee
The terminal has substantially no step with respect to the island terminal.
The multilayer wiring board for mounting a semiconductor chip according to claim 1, wherein
が接続された請求項１又は２記載の半導体チップ搭載用
多層配線基板。3. A lead for external conduction is provided on a peripheral portion of a multilayer wiring board.
3. The multilayer wiring board for mounting a semiconductor chip according to claim 1 , wherein
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5292572A JP2918087B2 (en) | 1993-10-27 | 1993-10-27 | Multilayer wiring board for mounting semiconductor chips |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5292572A JP2918087B2 (en) | 1993-10-27 | 1993-10-27 | Multilayer wiring board for mounting semiconductor chips |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH07122700A JPH07122700A (en) | 1995-05-12 |
| JP2918087B2 true JP2918087B2 (en) | 1999-07-12 |
Family
ID=17783513
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5292572A Expired - Lifetime JP2918087B2 (en) | 1993-10-27 | 1993-10-27 | Multilayer wiring board for mounting semiconductor chips |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2918087B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4305667B2 (en) | 2005-11-07 | 2009-07-29 | セイコーエプソン株式会社 | Semiconductor device |
-
1993
- 1993-10-27 JP JP5292572A patent/JP2918087B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH07122700A (en) | 1995-05-12 |
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