JP2917530B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device using two-dimensional conduction in a heterojunction of semiconductors having different electron affinities or semiconductors having different sums of an electron affinity and a forbidden band.

[0002]

2. Description of the Related Art A field effect transistor (FET) using two-dimensional electrons or holes stored in a heterojunction of a semiconductor having a different electron affinity or a semiconductor having a different sum of the electron affinity and the forbidden band is used for the stored electrons or Holes are of increasing interest because of their high mobility, especially at low temperatures. For example, gallium arsenide (hereinafter referred to as Ga
As) and a two-dimensional electron channel accumulated on the GaAs layer side of the heterojunction interface of a semiconductor layer having a smaller electron affinity than the n-type doped GaAs layer, for example, an aluminum gallium arsenide (hereinafter, AlGaAs) layer, by the voltage of the gate electrode. Operate by controlling.

[0003] In recent years, indium phosphide (hereinafter referred to as In
P) Heterojunction using indium gallium arsenide (hereinafter, InGaAs) and aluminum indium arsenide (hereinafter, AlInAs) having lattice constants matching on a substrate has attracted attention. InGaAs has a smaller effective mass of electrons and holes than GaAs. Therefore, for example, electrons traveling in InGaAs are expected to have a higher moving speed than electrons in GaAs. Also, InGaAs and Al
The conduction band and valence band discontinuity of InAs are GaAs and A
In comparison with the case of lGaAs, it is larger than that of InGaAs.
It is expected that the dimensional electron concentration will be higher than GaAs.

[0004]

SUMMARY OF THE INVENTION Incidentally, InGaAs
The mobility of electrons in s is up to 12,000 c at room temperature
m ² / Vs, 8,000 cm ^{2 for} GaAs
/ Vs is certainly larger. However, GaAs has a higher mobility at low temperatures. This is InGa
Alloy (A) caused by the mixture of In and Ga in As
lloy) scattering. The In composition of InGaAs whose lattice constant matches that of the InP substrate is 0.53, and the number of In atoms and Ga atoms is almost half. InG
In aAs, In and Ga are arranged randomly. As a result, when viewed microscopically, a portion containing a large amount of In atoms or G
A portion having a large number of a atoms is generated, the energy fluctuation of electrons occurs, and the electrons are scattered.

An object of the present invention is to provide a semiconductor device that suppresses such scattering of electrons and holes, increases the moving speed of electrons, and uses higher-speed two-dimensional conduction.

[0006]

According to the present invention, a second semiconductor comprising a group III-V compound comprising two group III elements is provided on a first semiconductor, and each of the group III elements is provided on a crystal surface. Arranged in parallel and ordered, and
A third semiconductor layer having a smaller electron affinity than the third semiconductor layer, and a second semiconductor layer at the interface between the second and third semiconductor layers.
An electron channel is formed on the semiconductor side of the semiconductor device, and a Schottky electrode is formed at an angle larger than 45 degrees in the ordered arrangement of the second semiconductor.

Further, according to the present invention, a second semiconductor comprising a III-V compound composed of two group III elements is provided on the first semiconductor, and the group III elements are arranged in parallel and ordered in parallel with the crystal surface. Further, a third semiconductor layer having a larger sum of the electron affinity and the forbidden band is provided on the second semiconductor layer, and the third semiconductor layer at the interface between the second and third semiconductor layers has a positive polarity. A field effect semiconductor device, wherein a hole channel is formed, and a Schottky electrode is formed at an angle exceeding 45 degrees in the ordered arrangement of the second semiconductor.

[0008] Further, the second semiconductor layer is made of indium gallium arsenide, and the third semiconductor layer is made of aluminum indium arsenide.

[0009]

According to the present invention, InGaAs, which is a mixed crystal, depends on the growth conditions.
It is known that n atoms and Ga atoms are ordered in a long period, and a so-called “superstructure” is formed. Applied Physics Letters, Applied Physics Letters, published July 6, 1987.
s ") on page 51, InGaAs on (110) substrate was CuA by molecular beam epitaxy.
A u-I type crystal structure is obtained. Here, In and Ga atoms are alternately deposited on the substrate surface to form a row. In a crystal formed in such a state, In and Ga
Are linearly arranged parallel to the crystal plane, and when the electrons in the crystal travel parallel to this row, there is no change in energy. However, for example, when traveling in a vertical direction, InAs
The traveling of electrons is remarkably hindered because the energy potential of GaAs and the energy potential of GaAs are alternately received. Therefore, InG having such a crystal structure
In the case of aAs, a field effect transistor in which electrons travel along a Ga or In column is used, so that a normal I
It is possible to improve performance such as an increase in mutual conductance as compared with the conventional case using an InGaAs layer in which n and Ga are randomly arranged. Note that if the carriers are run at an angle smaller than 45 degrees even if they are not parallel to the ordered arrangement direction of Ga or In, the mobility of the carriers is improved as compared with the conventional example.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings by using an embodiment of a field-effect transistor composed of InGaAs and n-type AlInAs arranged on an InP substrate.
FIG. 1 shows a high-purity AlInAs layer 1 as a first semiconductor layer and Ga as a second semiconductor layer on a semi-insulating InP substrate 8 having a plane orientation of about (110) and tilting 6 degrees in the <00 1 > direction. InGaAs which in is arranged in each <1 10> direction
Layer channel layer 2, n-type AlInAs as third semiconductor
The layer 3 and the high-concentration n-type InGaAs layer 4 are shown. Further, a part of the high-concentration n-type InGaAs layer 4 is etched to form a recess structure, the Schottky gate electrode 5 is located inside the recess, and an ohmic source electrode 6 and a drain electrode are formed on the high-concentration n-type InGaAs layer 4. 7 are provided. Here the gate electrode 5 are vertically installed <1 10> direction. Therefore the electron travels to the <1 10> direction. The high-purity AlInAs layer 1 is 5000 angstrom by molecular beam epitaxy.
The nGaAs layer 2 is 2,000 angstroms, and the AlInAs layer 3 is doped with silicon at 2 × 10 ¹⁸ cm ^−3.
300 Å and high concentration n-type InGaAs
An s layer 4 is grown, and a gate electrode 5 is formed of aluminum.
Further, ohmic electrodes 6 and 7 are formed of gold, germanium and nickel.

[0011] Observation of the channel layer of the epitaxial layer to be used for such a semiconductor device by a transmission electron microscope, superstructure is observed, it was found that the <1 10> direction Ga and In are arranged respectively .

On the other hand, as a conventional semiconductor device, (10)
0) forming a similar epitaxial layer on the substrate,
A gate electrode and an ohmic electrode were formed. Here, although the channel layer was observed with a transmission electron microscope, no superstructure was observed, and it is considered that Ga and In were randomly arranged.

For comparison, a semiconductor device having a gate whose direction was changed by 90 ° was formed on the epitaxial crystal used in the embodiment of the present invention. Here, the gate is located parallel to Ga or In in the channel layer.

The transconductance of the semiconductor device of the present invention has a larger value than that of the conventional example. Also, in the case of a semiconductor device in which the gate is different from that of the present invention by 90 °, the transconductance was almost the same as that of the conventional example. Therefore, scattering of carriers can be suppressed by forming a gate perpendicular to the direction in which Ga or In is arranged. If the angle between the arrangement direction and the gate is larger than 45 degrees, an improved effect as compared with the conventional example can be obtained.

Next, a second embodiment of the present invention will be described.
In this embodiment, the case where the carriers are electrons has been described.
The present invention can be similarly applied to the case where the carrier is a hole. The following are AlInAs, InGaAs, AlInA
This will be described using an example of a semiconductor device made of s. The structure is basically the same as FIG.

In this embodiment, the first case where the carrier is an electron is
Unlike the Example, the holes were holes, and AlInAs of the third layer was a p-type semiconductor and used beryllium as a dopant. High purity AlInAs as the first semiconductor layer,
High purity InGaAs and p-type Al
Epitaxial growth was performed on a semi-insulating InP substrate using InAs. Unlike the case of the first embodiment, the ohmic electrode for holes uses a gold or zinc alloy. Such changes did not affect the presence or absence of the superstructure.

As in the first embodiment, the transconductance of the semiconductor device of the present invention has a larger value than that of the conventional example. Also, in the case of a semiconductor device in which the gate is different from that of the present invention by 90 °, the transconductance was almost the same as that of the conventional example.

In this embodiment, the gate metal is provided perpendicular to the arrangement of Ga and In in the crystal. However, the gate metal is not necessarily required to be perpendicular and may be larger than 45 °. The materials of the gate electrode, the source electrode, and the drain electrode can be arbitrarily changed.

[0019]

As is apparent from the above description, the present invention suppresses the scattering of electrons due to the mixture of In and Ga in the InGaAs crystal, increases the electron moving speed, and increases the two-dimensional electron speed. It is possible to form a semiconductor device using a semiconductor device, and the effect of improving the performance of a semiconductor element is remarkable as compared with the related art.

[Brief description of the drawings]

FIG. 1 is a schematic diagram showing a structure of a semiconductor device according to the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 high-purity AlInAs 2 InGaAs 3 n-type AlInAs 4 n-type InGaAs 5 gate electrode 6 source electrode 7 drain electrode 8 semi-insulating InP substrate

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 21/337-21/338 H01L 27/095 H01L 27/098 H01L 29/775-29/778 H01L 29 / 80-29/812

Claims (3)

(57) [Claims] A second semiconductor of a group III-V compound comprising two kinds of group III elements is provided on a first semiconductor, and the group III elements are respectively arranged and arranged in parallel to a crystal surface. A third semiconductor layer having a smaller electron affinity than the second semiconductor layer is provided on the second semiconductor layer;
An electron channel is formed on the second semiconductor side at the interface between the second and third semiconductor layers, and a Schottky electrode is formed at an angle exceeding 45 degrees in the ordered arrangement of the second semiconductor. A field-effect type semiconductor device, characterized in that: 2. A second semiconductor of a group III-V compound comprising two kinds of group III elements is provided on the first semiconductor, and the group III elements are respectively arranged and arranged in parallel to the crystal surface. A third semiconductor layer having a larger sum of electron affinity and forbidden band than the second semiconductor layer is provided on the second semiconductor layer, and a second semiconductor side of an interface between the second and third semiconductor layers is provided. A field effect semiconductor device, wherein a Schottky electrode is formed at an angle exceeding 45 degrees in the ordered arrangement of the second semiconductor. 3. The semiconductor device according to claim 1, wherein said second semiconductor layer is made of indium gallium arsenide, and said third semiconductor layer is made of aluminum indium arsenide.