JP2915445B2 - Image processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus, and more particularly, to a method of adding a random number component to an input multi-valued image signal and disturbing periodicity in pseudo halftone processing. The present invention relates to an image processing device that can be used.

[Related Art] In recent years, as a typical binarization method of the conditional decision type dither method, there is an average error minimum method (also referred to as an error diffusion method ED method). Unexamined Japanese Patent Application Publication No. Hei.
The average concentration preservation method disclosed in US Pat.
It is classified into a binarization method. In the binarization method such as the ED method, in principle, the binary determination of a target pixel strongly depends on peripheral pixel data. In particular, when a CG (computer graphics) image is represented in a pseudo halftone, a regular low-frequency texture is generated due to the periodicity of the binarization processing, and the image quality is degraded. I will. To solve this problem, a method is known in which a dither signal that is sufficiently smaller than the image signal is added to the image signal to be processed to disturb the periodicity.

[Problems to be Solved by the Invention] However, the above-described dither signal providing means generally uses an image data width (for example, image data is 0 to 255 in accordance with the density), even though the value to be provided is sufficiently small. Width of 8 bits or more in the case of a value of 0, that is, 0 to 255
The disadvantage of adding a dither signal (+1, 0, -1) to the image of (1) is that an adder / subtractor having a 10-bit width of -1 to +256, which is generated when adding a dither signal, is required, so that the hardware burden cannot be overlooked. There was.

The present invention has been made in view of the above-described problems, and performs a logical operation on a bit signal at a predetermined position of an input image signal and a random number generated by a random number generation unit, and outputs an image signal having a predetermined number of input bits. An image signal having the same number of bits as the input image signal is obtained by replacing the bit signal at the predetermined position with the result of the operation by the operation means, using the input image signal as a bit signal not used for the operation in the operation means. It is an object of the present invention to provide an image processing apparatus which can output an image signal and can add a random number component to an input image signal with an inexpensive and simple configuration.

[Means for Solving the Problems] In order to achieve the above object, an image processing apparatus according to the present invention employs a predetermined number of bits per pixel. Input means for inputting a multi-valued image signal consisting of: a random number generating means for generating a random number in synchronization with the image signal input by the input means; and a bit signal at a predetermined position of the image signal input by the input means Calculating means for performing a logical operation on the random number generated by the random number generating means; and a bit signal which is not used in the calculation by the calculating means among image signals consisting of a predetermined number of bits input by the input means. An output unit that outputs an image signal having the same number of bits as an input image signal by replacing the bit signal at the predetermined position with the operation result of the operation unit, using the signal as it is, and converting the image signal output from the output unit. Processing means for performing pseudo halftone processing.

[Operation] In such a configuration, a logical operation is performed between a bit signal at a predetermined position of an input image signal and a random number generated by a random number generation unit, and is used for a logical operation of an image signal having the input predetermined number of bits. An input image signal is used as it is, and the bit signal at the predetermined position is replaced with a result of a logical operation, thereby outputting an image signal having the same number of bits as the input image signal.

Embodiments Preferred embodiments according to the present invention will be described below in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention. Referring to FIG. 1, reference numeral 100 denotes an image reading unit for reading a document image; 101, an analog image signal read by the image reading unit 100 is converted into a digital signal, and thereafter, known corrections such as logarithmic conversion and shading correction are performed. 5 shows a quantization unit that performs processing. Reference numeral 102 denotes a binarization processing unit that performs binarization processing of the image data from the quantization unit 101 according to the present method. Reference numeral 103 denotes an image output unit that generates a visible image based on the binary image signal in the binarization processing unit 102.

Next, the binarization processing of this method will be described. In the present embodiment, only the position of 2 ⁿ bits of the 8-bit input image data is logically operated with a small dither signal. In this way, after adding a small dither signal to the input data, pseudo gradation conversion is performed. Use a method that

FIG. 2 is a block diagram showing the internal configuration of the binarization processing section 102 of the present embodiment. In the figure, 4-1 to 4-25
1 shows a D-type flip-flop (DF / F) that holds 1-bit data with a delay of each image clock (not shown). Reference numerals 5-1 to 5-3 denote EX-OR gates for inputting 1-bit data delayed and held to the DF / Fs 4-1 to 4-25, respectively, and performing an exclusive OR operation. 3 is M
4 shows a pseudorandom number generation circuit of a series, and a small dither signal given by one bit by DF / F 4-1 to 4-25 and EX-OR gates 5-1 to 5-2, 5-3, that is, Generate a random number PN.
1 and 2 show a DF / F that holds 8 bits data, respectively before and after the logical operation in the pseudo-random number generator 3, 6 bit data and the pseudo-random number generator of the bit positions of 2 ¹ output from the DF / F1 7 shows an EX-OR gate that performs an exclusive OR operation with the random number PN from the device 3. 2 output from the EX-OR gate 6
The value data is output data to a pseudo gradation processing unit 7 described later. Reference numeral 7 denotes a pseudo halftone processing unit for converting 8-bit data output from the DF / F2 into pseudo halftone. The 8-bit data output from the pseudo halftone processing unit 7 is output to the image output unit 103 as output image data.

Next, the operation of the binarization processing unit 102 will be described.

In the upper pseudorandom number generator 3, DF / F4-1,4-2,4-3,4
The exclusive OR output from -4 is fed back to the input of DF / F4-25, whereby a random number PN for one bit having one cycle of 2 ²⁵ -1 is output from the output terminal of DF / F4-1. can get. Since the cycle of the random number PN is equivalent to the total number of image data of the A4 document at 400 dpi, the random number PN is a value having no periodicity in the A4 document. Random number PN is made the exclusive OR operation with 2 ¹ of an image signal bit position and EX-OR gate 6 in the image data of the input 8-bit width, randomly dither signal (random number PN of the operation result
The say) is connected to an input terminal of the 2 ¹ bit position of the DF / F2 as the output image data of the second ^1-bit position of the image data attached.

Here, when the input image 2 ¹ if data bit position of the data "1" and the random number PN is 1, the data of the bit positions of 2 ¹ output is "0". In this case, 2 ^{1 of the} input image data
Is given a PN value of "-2". In contrast, when the 2 ¹ or data bit position "0" and the random number PN is "1", 2 ¹ data bit position is "1" to "0". In this case, 2 ^{1 of the} input image data
The PN value of "+2" is given to the data at the bit position of "1". In the case of PN = 0, the input image data is output as it is, that is, in the state of the assigned PN value (assigned value) “0”.

FIG. 3 is a diagram for explaining the relationship between random numbers PN (given values) and input data according to the present embodiment.

As shown in FIG. 3, when the input image data is 13, 13 + 2 = 15 if PN = 1, and 13 + 0 if PN = 0.
= 13. When the input image data is 14, if PN = 1, 14-2 = 12, if PN = 0, 14+
It is dithered to 0 = 14. Similarly, if the input image data is 15
When the, granted value determined in the same manner (2 ¹ bit position of the data are the same) and when the input image data 14, also when the input image data is 15, and when the input image data is 13 similar (data of two ¹ bit position is the same) grant value is determined. In the present embodiment, since it is using the M-sequence random number, the number of 0 and 1 which is generated is guaranteed to the same number, the data of two ^1-bit position of the input image data 0
It can be said that dithering is achieved with a simple configuration without a large deviation in the probabilities that can be taken.

As described above, according to the present embodiment, a circuit for applying a small dither signal can be realized at a lower cost and with a simple configuration.

<Other embodiments> Now, in the embodiment described above, against 2 ¹ of the bit positions have been granted dither signal (random number PN), in order to obtain a finer application data, 2 ⁰ image signal of bit positions of Alternatively, a minute dither signal may be added.

Therefore, another embodiment will be described. Note that the same components as those in the above-described embodiment are denoted by the same reference numerals, and description thereof will be omitted.

FIG. 4 is a block diagram showing the internal configuration of a binarization processing unit according to another embodiment. In the figure, EX-OR gate 8 is
In the M-sequence pseudorandom number generator 3 ', a random number PN2 having a phase shifted from the output signal (random number PN1) of DF / F4-1 is obtained from the output of DF / F4-3. exclusive-ORs the 2 ⁰ signal bit positions of the arithmetic result 2 ⁰
It is assumed that the input image data at the bit position is a small dither signal or is added to the image data.

FIG. 5 is a view for explaining the relationship between random numbers PN1 and PN2 (assigned values) and input data according to another embodiment.

In the figure, for example, when the lower 2 bits are 00 _B (B: means a binary number) as in the input image data “16”,
For (PN1, PN2) = (1, 1), the value given by the random numbers PN1 and PN2 is +3, and for (PN1, PN2) = (0, 1), the value given is +
1, (PN1, PN2) = (1, 0), the assigned value is +2, (PN
The assigned value is 0 for (1, PN2) = (0, 0). In this way, the values of 0 to +3 are randomly assigned. Similarly, the lower two bits are 01 _B like the input image data “13”.
In the case of (1), a value of -1 to +2 is randomly added, and when the lower two bits are 10 _B as in the input image data "14", -2 to
Value of +1 is random granted, if the lower 2 bits of 11 _B as the input image data "15", the value of -3～0 are random granted.

As described above, even if a small dither signal is applied to the lower two bits of the input image number, the same effect as that of the above-described embodiment can be obtained.

In the case of binarization by the error diffusion method, the pseudo-random number generator used in the above-described two embodiments also adds the LSB or lower bits of the multi-valued data after performing error correction on the target pixel. Even if a small dither signal is added, the same random number effect as in the above-described embodiment can be obtained.

Further, in the two embodiments described above, the exclusive OR of the input image data and the random number PN is performed by using the EX-OR gate, respectively. However, the present invention is not limited to this. − AND, NAND, NOR, OR, EX − regardless of OR operation
It goes without saying that the same result as in the above-described two embodiments can be obtained even if a circuit such as NOR is used.

[Effects] As described above, according to the present invention, a logical operation is performed on a bit signal at a predetermined position of an input image signal and a random number generated by random number generation means, and an image signal having a predetermined number of input bits is calculated. Of these, the input image signal is used as it is for the bit signal not used for the operation in the operation means, and the bit signal at the predetermined position is replaced by the operation result of the operation means, so that the image signal having the same number of bits as the input image signal is obtained. A signal can be output, and a random number component can be added to an input image signal with an inexpensive and simple configuration.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention, FIG. 2 is a block diagram showing the internal configuration of a binarization processing section 102 of this embodiment, and FIG. 3 is a random number PN ( FIG. 4 is a block diagram showing an internal configuration of a binarization processing unit according to another embodiment, and FIG. 5 is a block diagram showing random numbers PN1 and PN2 (others) according to another embodiment. FIG. 4 is a diagram for explaining the relationship between input values and input data. In the figure, 1,2,4-1 to 4-25 DF / F, 3,3 'pseudorandom number generator, 5-1 to 5-3,6,8 EX-OR gate, 7 ......
..., 9, 10, 100,..., Image reading unit, 101, quantization unit, 102, binarization processing unit, 103.
An image output unit.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H04N 1/40-1/409 H04N 1/46 H04N 1/60

Claims (1)

(57) [Claims] An input unit for inputting a multi-valued image signal having a predetermined number of bits per pixel; a random number generating unit for generating a random number in synchronization with the image signal input by the input unit; Calculating means for performing a logical operation on a bit signal at a predetermined position of the input image signal and a random number generated by the random number generating means; An output means for outputting an image signal having the same number of bits as the input image signal by replacing the bit signal at the predetermined position with the operation result of the operation means, using the input image signal as it is for the bit signal not used for An image processing apparatus comprising: a processing unit that performs pseudo halftone processing on an image signal output from the output unit.