JP2914322B2 - Operation test equipment for superconducting elements - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a superconducting element operation test apparatus, and more particularly to a superconducting element operation test apparatus for performing a high-speed clock operation test of a superconducting latch circuit.

[0002]

2. Description of the Related Art Superconducting elements are said to be excellent in high-speed operation characteristics. For a high-speed evaluation of a logic circuit using a superconducting element, a method of evaluating an operation limit of an AND logic circuit and an OR logic circuit by a method such as a delay time measurement using a fast rising pulse has been adopted. However, a latch circuit composed of a superconducting element can evaluate normal operation only with a pulse pattern of two clock cycles or more including a bias reset sequence peculiar to the superconducting element, and can evaluate operation by a delay time. Test must be performed using a clock. In addition, there are two outputs, a true output and an auxiliary output, and it must be confirmed that both of them are operating normally.

FIG. 10 is a block diagram showing an example of a conventional superconducting element operation test apparatus. This operation test device is a device for performing a high-speed operation characteristic test of a superconducting latch circuit. A method of testing the operation of a superconducting element of this type under a high-speed clock has been conventionally known, for example, on May 1, 1986,
Applied Physics, Vol. 59, No. 9, 3202
3207 (Applied Physics, vol. 59 (9), 1)
May 1986).

FIG. 10 shows a pulse generator 10.
Reference numeral 1 denotes a circuit under test 102 which separately receives a driving bias clock and a data signal (test input) for checking normal operation.
Send to The circuit under test 102 is a superconducting latch circuit whose characteristics are to be evaluated, and has a bias clock signal input terminal, a data input terminal, a true output terminal, and an auxiliary output terminal. The oscilloscope 103 extracts and monitors both the output of the true signal and the output of the complementary signal.

Next, the operation will be described. The superconducting latch circuit is a circuit that outputs a data signal input to a certain clock and both a true signal and a complementary signal at the next clock. Therefore, the data input pulse train is generated by the pulse generator 101, and the output of the next clock is monitored by the oscilloscope 103. If the pulse train same as the input is the same as the true output, and if the complementary output is opposite to the true output, the operation is normal. Can be evaluated.

In this test, the frequency of the bias clock and the data input pulse in the pulse generator 101 are the same, and the rise of the data input needs to be delayed from the rise of the bias clock due to the characteristic of the superconducting element. Is done. Under these conditions, the frequencies of the bias clock and the data input pulse are increased, and the malfunctioning frequency is evaluated as giving the upper limit of the operation of this circuit.

[0007]

However, in the above-described conventional operation test apparatus, when a malfunction occurs, it is difficult to determine whether the malfunction is from the circuit under test 102 or a problem in the measurement system. . The reason is that in the conventional operation test apparatus, the input of the bias clock and the input of the data are separate, and the rise order is determined. As the clock frequency increases, the wavelength decreases. In the evaluation of a superconducting element in which a measuring cable must be introduced into a cryogenic part, errors in the timing sequence of bias clock input and data input are likely to occur due to a slight difference in cable length or the like. This is not a problem of the circuit under test 102. However, it is difficult to determine whether the problem is a measurement system problem or the upper limit of the operation of the circuit under test 102, which impairs the credibility of the element test.

Also, the conventional operation test apparatus has a problem that the upper limit of the normal operation frequency of the circuit under test 102 cannot be measured. The reason is that the upper limit clock frequency of the pulse generator 101 that can generate an arbitrary pulse waveform is lower than the expected upper limit of the normal operating frequency of the circuit under test 102. This is due to the difference in the operation range between the superconductor that is the circuit under test 102 and the semiconductor circuit that constitutes the pulse generator 101.

[0009] The present invention has been made in view of the above points,
Provided is an operation test apparatus for a superconducting element which enables a test method for giving an upper limit of the clock operation of a latch logic circuit, an AND logic circuit, and an OR logic circuit composed of a superconductor with only one sine wave input. With the goal.

[0010]

In order to achieve the above object, the present invention has a clock input terminal, a data input terminal, a true output terminal and an auxiliary output terminal, and the auxiliary output terminal and the data input terminal are connected. Clock signal input means for inputting a sine wave of a desired frequency or a pulse obtained by shaping a sine wave into a clock input terminal of a superconducting latch circuit to be tested, and both a true output terminal and an auxiliary output terminal of the superconducting latch circuit. An operation determination circuit that performs a logical operation on an output signal to output two operation determination signals, and evaluates and measures whether the superconducting latch circuit operation is normal based on a combination of logics of the two operation determination signals from the operation determination circuit. And a measuring means for performing the measurement.

The clock signal input means may directly input a sine wave of a desired frequency to a clock input terminal of the superconducting latch circuit to be tested, or may output a sine wave of a sine wave of a desired frequency. And a clock signal supply circuit for converting a sine wave from the sine wave oscillator into a pulse and inputting the pulse to the clock input terminal of the superconducting latch circuit. The clock signal supply circuit is a clock input terminal of the superconducting latch circuit. And a series circuit of a plurality of Josephson junctions connected between the ground and the ground.

According to another aspect of the present invention, there is provided a Josephson junction as an operation judging circuit which divides a composite signal of both output signals of a true output terminal and an auxiliary output terminal of a superconducting latch circuit and outputs one operation judgment signal. It is characterized in that the used frequency dividing circuit is used.

The superconducting latch circuit to be tested includes first and second superconducting latch circuits whose clock input terminals are commonly connected to each other, and the auxiliary output terminal of the first superconducting latch circuit is a second superconducting latch circuit. The true output terminal of the second superconducting latch circuit is connected to the data input terminal of the first superconducting latch circuit, and the true output terminal of the first superconducting latch circuit. A signal is output from the terminal and the complementary output terminal of the second superconducting latch circuit to the operation determination circuit.

In the present invention, the superconducting latch circuit to be tested is connected to another operation determining circuit using a small number of Josephson junctions, and only one external input is used as a clock input.
The clock is supplied as a sine wave, and the output of the superconducting latch circuit is input to the operation determination circuit, so that the output can be converted into a rectangular signal whose output is low or a signal whose repetitive waveform is easily observed. Sine wave oscillators exist up to the tens of gigahertz band, and the frequency required for evaluation can be supplied without any problem.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing an embodiment of a superconducting element operation test apparatus according to the present invention. In the figure, only the sine wave signal oscillated and output by the sine wave oscillator 10 is input to the circuit under test 20. The output signal of the circuit under test 20 is input to the oscilloscope 30 and monitored, and the operation state is evaluated and measured.

FIG. 2 is a block diagram showing one embodiment of the circuit under test 20 in FIG. The circuit under test 20 includes a clock signal supply circuit 21, a Josephson latch circuit (superconducting latch circuit) 22 to be measured, and a normal operation determination circuit 23. In the circuit under test 20, the sine wave signal input from the outside is input to the clock signal supply circuit 21 and converted into a clock signal suitable for the Josephson latch circuit 22 to be measured. The measured Josephson latch circuit 22 operates in synchronization with this clock signal, and its output signal is input to the normal operation determination circuit 23 and converted into an operation determination signal, which becomes an output signal to the oscilloscope 30 in FIG. .

Next, an operation test method will be described with reference to FIGS. First, the sine wave oscillator 1
Introduce a sine wave input from zero. The sine wave oscillator 10 is commercially available up to several tens of gigahertz bands, and has a sufficient band for knowing the upper limit of operation of the superconducting element. The circuit under test 20 inputs the input sine wave to the clock signal supply circuit 21 shown in FIG. 2 and converts it into a clock suitable for the operation of the Josephson latch circuit 22 under test. The clock signal supply circuit 21 is not always necessary.

The output signal of the clock signal supply circuit 21 is
The signal is input to the clock input terminal of the Josephson latch circuit 22 to be measured. The measured Josephson latch circuit 22 connects the data input terminal and the data output terminal of the latch circuit. Although the connection method will be described later, the complementary output signal of the latch circuit is connected to the input signal, or the latch circuit is arranged in parallel and the output signals of each other are connected to the input signal of the other party. With this connection, the input signal of the measured superconducting latch circuit uses the output signal that occurs later than the clock signal, so the input signal always comes after the clock input, and the timing between the input and the clock No sequencing issues. In this manner, a normal logic operation can be tested without introducing a data input from outside.

The output signal of the measured Josephson latch circuit 22 is input to a normal operation determination circuit 23. As will be described later, this circuit 23 moves to change the frequency of the input, or creates a set of two types of easily observable waveforms. The number of Josephson junctions used is smaller than that of the latch circuit to be measured, and the operation of the latch to be measured is not affected.

The output signal from the normal operation judging circuit 23 to the oscilloscope 30 is a combination of a continuous rectangular wave and no output, or a rectangular wave having a longer cycle than the clock, as described later, which is easy to observe and evaluate. Become. In general, the higher the frequency, the more difficult it is to observe a rectangular wave. With such a connection, the reliability of the evaluation is increased. Thus, the input side can know the upper limit of the normal operation of the measured Josephson latch circuit 22 without any problem of the timing sequence of the clock input and the data input with only one input of the sine wave with little attenuation of the waveform.

FIG. 3 is a circuit diagram of a first example of the circuit under test in FIG. In this example, the clock signal supply circuit 21 does not exist, and the circuit under test 20 includes a Josephson latch circuit 220 corresponding to the Josephson latch circuit 22 under test and a normal operation determination circuit 23. 23 includes a Josephson OR circuit 231 and a Josephson and circuit 232. The Josephson latch circuit 220 has a data input terminal, a clock input terminal, a true output terminal, and an auxiliary output terminal, and the auxiliary output terminal is connected to the data input terminal.

Thus, as described above, the complementary output signal generated later than the clock signal is used as the data input signal of the Josephson latch circuit 220.
Since the data input signal always comes after the clock input, the problem of the timing sequence between the input and the clock does not occur.

Next, the operation of this example will be described with reference to the signal waveform diagram of FIG. The sine wave shown in FIG. 4A is directly input from the sine wave oscillator 10 to the clock input terminal of the Josephson latch circuit 220, whereby the Josephson latch circuit 220 operates, and the true output signal and the true output signal at that time are output. The complementary output signal is input to the Josephson OR circuit 231 and the Josephson and circuit 232, respectively.

When the Josephson latch circuit 220 operates normally, the Josephson OR circuit 231 outputs the signal from FIG.
As shown in FIG. 4 (a), a train of rectangular waves having the same cycle as the clock (sine wave) shown in FIG. 4 (a) is extracted, and the Josephson and circuit 232 keeps zero output as shown in FIG. 4 (c). That is, a signal of a constant low level is extracted.

If the amplitude of the sine wave from the outside to the clock input terminal of the Josephson latch circuit 220 is gradually increased, a malfunction occurs when the amplitude is small.
The output signals as shown in (b) and (c) do not appear in the outputs of the Josephson OR circuit 231 and the Josephson and circuit 232, and there is no output.

Subsequently, the amplitude of the sine wave is gradually increased, and when the sine wave reaches the normal operation region, the output waveform from the Josephson OR circuit 231 becomes a rectangular wave train shown in FIG. . This is the amplitude of the clock at which normal operation starts at a certain frequency. In this way, an amplitude margin for normal operation is obtained first.

Next, the frequency is further increased within the range of the amplitude for normal operation, and it is checked whether this waveform is maintained. In this case, of the two outputs, only the output signal of the Josephson OR circuit 231 is a rectangular wave train, and the Josephson and circuit 2
If there is no output signal from 32, the operation is normal and it is easy to determine normal / abnormal operation. While adjusting the amplitude of the sine wave from the outside, increase the frequency to know the final upper limit of normal operation. As described above, in this case, problems in the measurement system such as the timing sequence between the data input and the clock input can be ignored, and accurate characteristics of the circuit under test can be obtained.

FIG. 5 is a circuit diagram of a second example of the circuit under test in FIG. 3, the same components as those of FIG. 3 are denoted by the same reference numerals, and the description thereof will be omitted. The circuit under test 20 of the second example shown in FIG. 5 is characterized in that it has a clock signal supply circuit 21 using a Josephson junction. The clock signal supply circuit 21 includes a Josephson latch circuit 22
It consists of a series circuit of four Josephson junctions 211 to 214 connected between a clock input terminal of 0 and ground.

The clock signal supply circuit 21 having this configuration is
It can be created on the same chip as the Josephson latch circuit 220 to be measured. For this reason, the waveform is less rounded and the influence on the evaluation of the measured Josephson latch circuit 220 is small. When the clock signal supply circuit 21 having this configuration is added, the sine wave input from the outside is converted into a rectangular wave and input to the clock terminal of the Josephson latch circuit 220 as a clock signal. For this reason, there is also an advantage that the active time of the clock is longer than the sine wave, the operation margin of the entire circuit is increased, and the observation is easy. Note that the number of Josephson junctions is not limited to four.

FIG. 6 is a circuit diagram of a third example of the circuit under test in FIG. The circuit under test 20 of the third example includes first and second Josephson latch circuits 221 and 222.
Josephson latch circuit 22 consisting of: a normal operation determining circuit 233 corresponding to the normal operation determining circuit 23
Consisting of Note that the clock signal supply circuit 21 may or may not be present.

In the measured Josephson latch circuit 22,
First and second Josephson latch circuits 221 and 22
2 are used in parallel, the clock terminals of the Josephson latch circuits 221 and 222 are connected in common, and the auxiliary output terminal (auxiliary output 1) of the Josephson latch circuit 221 is connected to the data input of the Josephson latch circuit 222. A true output terminal (true output 2) of the Josephson latch circuit 222 is connected to a data input terminal (input 1) of the Josephson latch circuit 221;
In this configuration, signals are output from the true output terminal (true output 1) of the Josephson latch circuit 221 and the complementary output terminal (complementary output 2) of the Josephson latch circuit 222 to the normal operation determination circuit 233, respectively.

The normal operation judging circuit 233 includes a Josephson junction J connected between the true output 1 and the complementary output 2 and the ground.
in, resistors R1 and R2, Josephson junctions J1-J
4, Jsq1 and Jsq2, inductance Lin1,
It is composed of Lin2, Lcirc, Lsq, etc., and constitutes a frequency dividing circuit. In addition, the numerical value beside each circuit element is the value of the circuit element, and the Josephson junctions Jin, J1 to J1
4. The unit of the value of Jsq1 and Jsq2 is milliampere,
The units of the values of the resistors R1 and R2 are ohms, and the units of the values of the inductances Lin1, Lin2, Lcirc and Lsq are picohenry.

Next, the operation of FIG. 6 will be described with reference to a time chart of FIG. In FIG. 6, it is assumed that the Josephson latch circuits 221 and 222 are reset (input 1 and input 2 are zero) in an initial state. Josephson latch circuits 221 and 22
In 2, in the next clock cycle, for a certain input, the same output appears on the true output, and the opposite output appears on the complementary output. In this example, the input 1 has the same waveform as the true output 2 and the input 2 has the same waveform as the complementary output 1 in a certain clock cycle.

The data input signal is input in a form in which the output signals of the Josephson latch circuits 221 and 222 are fed back. Since the data input signal is input at a later rising edge than the rising edge of the clock, the timing sequence between the clock and the input signal is completely completed. Guaranteed to be normal.

A pulse shown in FIG. 7A obtained by shaping a sine wave from the outside into a clock input terminal is input as a clock signal, so that the Josephson latch circuit 22
1 and 222 operate and the resulting true output 1,
The auxiliary output 1, the true output 2, and the auxiliary output 2 are shown in FIG.
(C), (d), and (e), and input 1
7 has the same waveform as the true output 2 and is as shown in FIG. 7F.
(G).

Of these, the true output 1 and the complementary output 2 are input to the Josephson junction Jin in the normal operation determination circuit 233 and are logically ANDed. Therefore, the current Iinput flowing through the resistor R1 connected in parallel via the inductance to the Josephson junction Jin in the normal operation determination circuit 233 of FIG.
Is obtained as shown in FIG. 7 (h). In the normal operation determination circuit 233, when the current Iinput flows into the inductances Lin1 and Lin2, the normal operation determination circuit 23
Assuming that the output current of I.3 is Idetect, the normal operation determination circuit 2
Finally, an output current Idetect having a waveform as shown in FIG. As can be seen from FIGS. 7A and 7I, the output current Idetec
It can be seen that t is eight times the cycle of the input clock signal (the repetition frequency is divided by ８).

For example, it is very difficult to observe a clock at the 10 GHz level, but it is easy to observe a frequency that is one eighth of that. In other words, in this example, even if the clock has a high frequency that is difficult to observe, the operation can be performed on a waveform having a frequency of 1/8, so that the operation is easily evaluated.

The current Iinput shown in FIG.
FIG. 8 shows a dynamic simulation of the normal operation determination circuit for the situation shown in FIG. The waveform of the current Iinput shown in FIG. 8A corresponds to the output current Id shown in FIG.
The reason for the waveform of the eject signal will be described with reference to FIG.
A DC current bias Idc1 as shown in FIG.
, Idc2, Idc3. Where I
dc1 = −Idc3. This DC current bias causes Josephson junctions J1 and J2 to
In (b) and (c), current flows at points A and B, respectively.

When the current Iinput is inputted (FIG. 8)
(First input of (a)), the input current is divided into the inductances Lin1 and Lin2. This shunt current first flows through Josephson junctions J3 and J4. J3 and J4 are designed to be smaller than the input current Iinput. When the input current flows, the state changes to the voltage state, and J3 becomes J1 and J1 becomes J1.
4 functions to send a pulse current to J2. Finally, the current Iinput flows into the resistor R1.

The pulses flowing into J1 and J2 respectively cause the following effects. Since the direction of the current flowing in J1 and the direction of the current flowing by the DC current bias idc1 are the same, the Josephson junction J1 switches to the voltage state. On the other hand, the current flowing into the Josephson junction J2 is not in a voltage state because the direction of the current flowing through the DC bias idc3 is opposite to that of the current flowing therethrough.

The switching of the Josephson junction J1 causes a DC current bias to flow from the Josephson junction J1 to the ground, and the current flowing backward through the Josephson junction J2 to the connection point between the Josephson junctions J1 and J3. The current flows through the inductance Lcirc, which is connected in series between the connection points of the Josephson junctions J4 and J2.
The switch of this Josephson junction J1 corresponds to one flux quantum entering from this junction, and J1-Lcirc-
A permanent current of one flux quantum flows through the superconducting loop of J2. This corresponds to C in FIG.

Thereafter, when the current Iinput is input again (the second input in FIG. 8A), contrary to the first input, the Josephson junction J1 does not switch to the voltage state. The son junction J2 switches. As a result, the flux quanta that has entered at the first input goes out of the superconducting loop through the Josephson junction J2, the persistent current C disappears, and returns to the state before the first input.

As described above, the current flowing through the inductance Lcirc changes the output state in synchronization with the input of a certain input. This is detected by a superconducting loop circuit composed of Lsq, Jsq1, and Jsq2. By using this circuit, the current I shown in FIG.
Instead of observing a short cycle such as an input waveform to determine whether the operation is normal, observe a waveform converted into a long cycle such as the output current Idetect shown in FIG. However, since a method of evaluating the normal operation can be adopted from the cycle, the reliability of the evaluation is improved.

FIG. 9 is a circuit diagram of a fourth example of the circuit under test in FIG. The circuit under test 20 of the fourth example includes first and second Josephson latch circuits 221 and 222.
A measured Josephson latch circuit 22 comprising: a normal operation determining circuit 234 corresponding to the normal operation determining circuit 23;
Consisting of Note that the clock signal supply circuit 21 may or may not be present.

The normal operation judging circuit 234 connects a resistor in parallel to each of the Josephson junctions J3 and J4, sets the direct current bias idc1 and Idc2 in the same direction, and sets the Josephson junction Jsq2 and the inductance Lsq.
Output current Idetec from the connection point with
t is taken out, and even in such a configuration, FIG.
As shown in (e), a detection current Idetect obtained by dividing the input current Iinput is obtained.

The present invention is not limited to the above embodiment. For example, the clock signal supply circuit 21 shown in FIG. 5 may be added to the clock input unit having the configuration shown in FIG. In this case, there is an advantage that the supplied clock has a rectangular wave, the active time of the clock is longer than the sine wave, the operation margin of the whole circuit under test is increased, and the observation is easy. Further, the clock signal supply circuit 21 shown in FIG. 5 may be added to the clock input unit shown in FIG. In this case, there is an advantage that the supplied clock has a rectangular wave, the active time of the clock is longer than the sine wave, the operation margin of the whole circuit under test is increased, and the observation is easy.

That is, assuming that the operating range of the clock bias of the circuit to be measured (in the case of a superconducting circuit, the clock and the bias are the same) is 10 mV to 12 mV, if this clock is supplied as a sine wave, Must be supplied so that the amplitude of the clock signal does not exceed 12 mV and falls within the range of 10 mV to 12 mV. The clock signal supply circuit 21 shown in FIG. 5 is composed of four Josephson junctions. Therefore, the sine wave operates as a constant voltage source of 11.2 mV, and when this operates normally as a constant voltage source, the amplitude of the sine wave input from the outside can be from 7 mV to about 15 mV. That is, by using the clock signal supply circuit 21, the range in which the amplitude of the sine wave can be changed (operation margin) increases.

[0048]

As described above, according to the present invention,
The superconducting latch circuit to be tested is connected to a small number of other operation decision circuits using Josephson junctions, the only external input is a single clock, the clock is supplied as a sine wave, and the output of the superconducting latch circuit is output. Is input to the operation determination circuit, the output can be converted into a rectangular signal having a low output, or a signal whose repetition waveform can be easily observed. Therefore, the upper limit frequency of the operation of the superconducting latch circuit can be obtained. .

According to the present invention, the input of the superconducting latch circuit is made only one clock input and connected so that the output signal is fed back to the data input terminal, so that the timing sequence of the data input and the clock input can be reduced. Since external control is not required, erroneous evaluation due to malfunction of the measurement system at the time of high-speed characteristic evaluation can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of a superconducting element operation test apparatus according to the present invention.

FIG. 2 is a block diagram of an embodiment of a circuit under test in FIG. 1;

FIG. 3 is a circuit diagram of a first example of a circuit under test in FIG. 1;

FIG. 4 is a signal waveform diagram of each unit in FIG. 3;

FIG. 5 is a circuit diagram of a second example of the circuit under test in FIG. 1;

FIG. 6 is a circuit diagram of a third example of the circuit under test in FIG. 1;

FIG. 7 is a signal waveform diagram of each unit in FIG. 6;

8 is a dynamic simulation result of each part of the normal operation determination circuit in FIG.

FIG. 9 is a circuit diagram of a fourth example of the circuit under test in FIG. 1;

FIG. 10 is a block diagram of an example of a conventional superconducting element operation test apparatus.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 Sine wave oscillator 20 Circuit under test 21 Clock signal supply circuit 22 Josephson latch circuit under test 23 Normal operation judgment circuit 30 Oscilloscope 211-214, Jin, J1-J4, Jsq1, Js
q2 Josephson junction 220, 221, 222 Josephson latch circuit 231 Josephson or circuit 232 Josephson and circuit Lin1, Lin2, Lsq, Lcirc Inductance

Claims (6)

(57) [Claims] 1. A clock input terminal of a superconducting latch circuit to be tested having a clock input terminal, a data input terminal, a true output terminal and an auxiliary output terminal, wherein the auxiliary output terminal and the data input terminal are connected. A clock signal input means for inputting a sine wave having a desired frequency or a pulse obtained by shaping the sine wave, and performing a logical operation on both output signals of a true output terminal and an auxiliary output terminal of the superconducting latch circuit. An operation determination circuit that outputs an operation determination signal; and a measurement unit that evaluates and measures whether or not the superconducting latch circuit operation is normal based on a combination of logics of the two operation determination signals from the operation determination circuit. Characteristic operation test equipment for superconducting elements. 2. The apparatus according to claim 1, wherein the clock signal input means directly inputs the sine wave of the desired frequency to the clock input terminal of the superconducting latch circuit to be tested. Conduction element operation test equipment. 3. The clock signal input means includes: a sine wave oscillator that oscillates and outputs a sine wave of the desired frequency; and a sine wave from the sine wave oscillator that converts the sine wave into a pulse to input a clock to the superconducting latch circuit. A clock signal supply circuit for inputting the signal to a terminal, wherein the clock signal supply circuit comprises a series circuit of a plurality of Josephson junctions connected between a clock input terminal of the superconducting latch circuit and ground. The operation test apparatus for a superconducting element according to claim 1. 4. The superconducting circuit according to claim 1, wherein said operation judging circuit comprises a Josephson OR circuit and a Josephson AND circuit provided in parallel, and each outputs said operation judging signal. Device operation test equipment. 5. The method according to claim 1, wherein the operation determination circuit uses a Josephson junction that divides a frequency of a combined signal of the output signals of the true output terminal and the auxiliary output terminal of the superconducting latch circuit and outputs one operation determination signal. The operation test apparatus for a superconducting element according to claim 1, wherein a frequency dividing circuit is used. 6. The superconducting latch circuit to be tested comprises first and second superconducting latch circuits whose clock input terminals are commonly connected to each other, and the auxiliary output terminal of the first superconducting latch circuit is A data input terminal of the second superconducting latch circuit, a true output terminal of the second superconducting latch circuit connected to a data input terminal of the first superconducting latch circuit, A true output terminal of the conduction latch circuit and the second
4. The operation test apparatus for a superconducting element according to claim 1, wherein a signal is output from the auxiliary output terminal of the superconducting latch circuit to the operation judging circuit.