JP2910752B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a semiconductor element on an insulating amorphous material.

[0002]

2. Description of the Related Art Insulating amorphous substrates such as glass and quartz,
Attempts have been made to form a high-performance semiconductor element on an insulating amorphous layer such as SiO ₂ .

In recent years, large and high-resolution liquid crystal display panels, high-speed and high-resolution contact type image sensors,
As the need for C and the like increases, realization of a high-performance semiconductor device on an insulating amorphous material as described above has been desired.

[0004] Taking the case of forming a thin film transistor (TFT) on an insulating amorphous material as an example, (1) a TFT using amorphous silicon as an element material formed by a plasma CVD method or the like; A TFT using a polycrystalline silicon formed by a method or the like as an element material, and (3) a TFT using a single crystal silicon formed by a melt recrystallization method or the like as an element material are being studied.

However, of these TFTs, TFTs using amorphous silicon or polycrystalline silicon as an element material
Is compared with the case where single crystal silicon is used as the element material.
Field effect mobility is significantly lower (amorphous silicon TFT
<Lcm ² / V · sec, polycrystalline silicon TFT-10
cm ² / V · sec), and it was difficult to realize a high-performance TFT.

On the other hand, the melt recrystallization method using a laser beam or the like cannot be said to be a technique that has been sufficiently completed yet, and it is necessary to form an element in a large area such as a liquid crystal display panel. Especially difficult.

[0007]

Therefore, as a simple and practical method for forming a high-performance semiconductor device on an insulating amorphous material, a method of growing polycrystalline silicon having a large grain size in a solid phase has attracted attention. And research is ongoing. (Thin So
lid Films 100 (1983) p.227, JJAP Vol. 25No.2
(1986) p.L121) However, according to the conventional technique, polycrystalline silicon is formed by a CVD method, Si ⁺ is ion-implanted to make the polycrystalline silicon amorphous, and then a heat treatment at about 600 ° C. is performed for 100 hours. I was going for almost an hour. Therefore, an expensive ion implantation apparatus is required, and the heat treatment time is extremely long.

Therefore, the present invention provides a method for forming polycrystalline silicon having a large grain size and a high crystallization rate by a simpler and more practical method.

[0009]

According to the present invention, a silicon layer is formed on a substrate, and the substrate is heated to a predetermined temperature of 550 ° C. to 650 ° C .; The method is characterized in that the substrate is again heated to 550 ° C. to 650 ° C. and the silicon layer is annealed.

[0010]

[0011]

FIG. 1 is an example of a manufacturing process diagram of a semiconductor device according to an embodiment of the present invention. FIG. 1 shows an example in which a thin film transistor (TFT) is formed as a semiconductor element.

In FIG. 1, (a) shows a silicon layer 102 on an insulating amorphous material 101 such as an insulating amorphous substrate such as glass or quartz or an insulating amorphous material layer such as SiO _2. Is a step of forming As an example of film forming conditions, the substrate temperature is kept at about room temperature to about 600 ° C. by a plasma CVD method,
Monosilane or a gas obtained by diluting monosilane with hydrogen, argon, helium, or the like is introduced into the reaction chamber, and high-frequency energy or the like is applied to decompose the gas to form a silicon layer on a desired substrate with a thickness of about 100 angstroms to 2000 angstroms. And so on. However, the film formation method is not limited to this.

FIG. 2B shows a step of forming a polycrystalline silicon layer 103 by crystal growth of the silicon layer 102 by heat treatment or the like. The optimum conditions for the heat treatment differ depending on the method of forming the silicon layer in step (a). For example, there are the following differences depending on the substrate temperature during film formation.

(1) A film formed at a relatively low substrate temperature of room temperature to about 150 ° C. becomes amorphous silicon containing a large amount of hydrogen in the film, but is formed at about 200 to 300 ° C. Hydrogen in the film can be removed by heat treatment at a lower temperature than that of the film. An example of the heat treatment condition is described below. Plasma C
First annealing is performed on the formed amorphous silicon film in the VD reaction chamber. Since an amorphous silicon film having a low film formation temperature is a porous film, if the film is taken out to the atmosphere as it is after film formation, oxygen and the like are easily taken into the film, which causes a deterioration in film quality. When the heat treatment is performed appropriately, the film is densified, and the incorporation of oxygen and the like is prevented. The heat treatment temperature is desirably 300 ° C. or higher, and increasing the temperature to about 400 to 500 ° C. is particularly effective. Even if the heat treatment temperature is lower than 300 ° C., there is an effect of densification of the film by the heat treatment. However, if annealing is performed continuously without breaking vacuum, the first annealing can be omitted.

Subsequently, a second annealing is performed. An amorphous silicon film formed at a low film formation temperature is 550 ° C. to 650 ° C.
When the heat treatment at a relatively low temperature of about ° C. is performed for several hours to about 20 hours, desorption of hydrogen and crystal growth occur, and
Polycrystalline silicon having a large grain size of about 2 μm is formed.
In addition, it is not preferable that both the first annealing and the second annealing rapidly increase the temperature in a short time when the temperature is increased to a predetermined annealing temperature. The reason is that as the temperature is increased (especially when the temperature exceeds 300 ° C.), hydrogen in the film is desorbed, and when the rate of temperature rise is rapid, defects are easily formed in the film. In some cases, pinholes are formed or the film is peeled off. When the temperature is gradually increased at a temperature of at least 300 ° C. at a rate of temperature rise lower than 20 ° C./min (particularly desirable is a rate of temperature rise lower than 5 ° C./min), defects in the film are reduced. The details of the heating method will be described later.

(2) A film formed at a substrate temperature of about 150 ° C. to 300 ° C. has a smaller amount of hydrogen in the film than the above-described amorphous silicon film formed at a low temperature, but desorbs hydrogen. Temperature shifts to higher temperatures. However, since the film after film formation is denser than a film formed at a low temperature, the first annealing described above can be omitted. The second annealing condition is
When heat treatment at about 550 ° C. to 650 ° C. is performed for several hours to about 40 hours, desorption of hydrogen and crystal growth occur, and the crystal grain size l
Polycrystalline silicon having a large grain size of about 2 μm is formed. still,
The details of the method of raising the temperature from 550 ° C. to 650 ° C. will be described later, but the temperature rise is slower than 20 ° C./min (preferably 5 ° C./min) at a temperature of at least 300 ° C. as in the case of (1). Increasing the temperature gradually at a speed is desirable because defects in the film are reduced.

(3) When the substrate temperature exceeds 300.degree. C., the amount of hydrogen in the film further decreases, but the annealing at about 550.degree. C. to 650.degree. Heat treatment at temperature is important. The method will be described in the description of the step shown in FIG.

Next, conditions for heat treatment, particularly a method for raising the temperature to a predetermined temperature, will be described. FIG. 2 is an example of a schematic diagram of the temperature raising method in the embodiment and the reference example of the present invention. In FIG. 2, FIG. 2 (a) is a reference example, and a predetermined temperature (T
₁ ) Raise the temperature at a predetermined rate to a predetermined temperature ( _Tl )
Shows the case of annealing. The heating rate is 2 as described above.
Slower than 0 ° C./min (preferably 5 ° C./min) is preferable because generation of defects due to desorption of hydrogen is suppressed. It is to be noted that the heating rate does not need to be always constant, and may be changed within the above range. FIG. 2B is also a reference example, in which the temperature is raised at a predetermined temperature rising rate to a predetermined temperature (T ₂ ).
A case is shown in which the temperature is raised to a predetermined temperature (T ₁ ), which is the annealing temperature, by lowering the heating rate. The reason for changing the heating rate before and after T ₂ is that the desorption of hydrogen from the film starts at a temperature higher than about 300 ° C. as described above. After that, increase the heating rate to 20
This is because the generation of defects is suppressed at a rate lower than C / min (preferably 5 C / min). (Temperature rise time is also shortened.) Therefore, T ₂ is desirably set to about 250 ° C. to 400 ° C. As in the case of FIG. 2A, the heating rate does not need to be always constant. Or it may be gradually changed heating rate need not change in the heating rate before and after T ₂ is also a step manner. The temperature at which the heating rate is changed (T ₂ )
May be plural. FIG. 2C is also a reference example, in which the temperature is raised to a predetermined temperature (T ₂ ), then maintained at T ₂ for a predetermined time, and then raised to a predetermined temperature T ₁ which is an annealing temperature. Show. By keeping the temperature lower than the annealing temperature for a predetermined time (for example, about 20 minutes to 2 hours), much of the hydrogen in the film can be removed without generating polycrystalline nuclei.
Accordingly, the hardly occurs generation of defects resulting from removal of hydrogen be faster heating rate is when the temperature is raised to the annealing temperature after a predetermined time perquisite at T _2. T ₂ is desirably about 350 ° C. to 550 ° C. The predetermined temperature (T ₂ ) does not need to be kept constant. For example, the temperature may be raised slowly at a temperature rising rate lower than 5 ° C./min. Further, the temperature (T
₂ ) There may be more than one. For example, there is a method of once holding at about 350 ° C. and then holding again at about 500 ° C., and hydrogen can be more completely removed while suppressing the occurrence of defects in the film. FIG. 2D shows an embodiment of the present invention.
After the temperature is once increased to the annealing temperature (T ₁ ), the temperature is increased to a temperature (T ₃ ) higher than T _{1 in} a short time of about several minutes, and again T _1.
Until it cooled in a short time of about several minutes, shows the case of annealing at T _1. If the hydrogen in the film is annealed at a temperature T ₁ of the order as described above 550 ° C. to 650 ° C. by providing a step of raising the temperature to T ₃ is not sufficiently escape, crystal growth is inhibited, more hydrogen The crystal growth can be completely promoted. T ₃ is desirably about previously described 700 ° C. to 800 ° C.. Further, the time required for heating and cooling needs to be short (preferably within 10 minutes) in order to suppress the generation of polycrystalline nuclei. In addition, it is also possible to suppress generation | occurrence | production of a defect more by combining and using two or more of FIG.2 (a)-(d). FIGS. 2A to 2D are examples of the present embodiment and a reference example, and the present invention is not limited thereto. When raising the temperature to the predetermined annealing temperature,
In order to remove hydrogen in the film without generating defects, the film formation conditions, the heating method, the heating rate, etc. were optimized, and the amorphous film formed by the plasma CVD method, which was conventionally considered difficult, was used. It is important to realize a manufacturing method in which silicon is solid-phase grown on polycrystalline silicon having a large grain size. (Plasma C
The amorphous silicon film formed by the VD method is rich in mass productivity,
Although there is a merit such as easy area enlargement, a large amount of hydrogen is contained in the film, and the hydrogen inhibits solid-phase growth, which is not preferable as a method for forming an amorphous silicon film for solid-phase growth. It was previously thought. ) FIG. 1 (c)
Is a step of oxidizing the polycrystalline silicon layer 103 by a thermal oxidation method to form a gate insulating film 104. The gate oxidation temperature is about 1000 ° C. to 1200 ° C. The polycrystalline silicon layer 103 has been grown by the solid phase growth method in the step (b), but its crystallization ratio is not always high.
In particular, a silicon substrate formed by a plasma CVD method (amorphous silicon or microcrystalline silicon in which a fine crystal region exists in an amorphous phase) is solid-phase grown by heat treatment. The crystallization ratio is as low as about 40% to 65%. Therefore, when the polycrystalline silicon layer is oxidized by the thermal oxidation method, if the temperature is rapidly increased to a high temperature of about 1000 ° C. to 1200 ° C. in a short time, about 60% to 35% of the remaining uncrystallized region Our investigations have shown that the crystallinity is impaired. Although a clear causal relationship is not clear at present, when the temperature rises rapidly, (1) many crystal nuclei are generated in the uncrystallized region, and many fine crystal grains grow.

(2) The crystallization of the non-crystalline region, which proceeds during the temperature raising to thermal oxidation process, does not progress very much.

(3) During the temperature rise, the hydrogen remaining in the film is rapidly desorbed, causing defects.

The causes can be considered. So, we
As a means for solving such a problem, 1000 ° C. to 12 ° C.
By controlling the heating rate and the heating method when the temperature is raised to a thermal oxidation temperature of about 00 ° C., a method for greatly improving the crystallinity of the polycrystalline silicon layer has been found.

Furthermore, it has been found that there is also an important correlation between the substrate temperature of the film formed by the plasma CVD method and the method of increasing the temperature during gate oxidation. That is, (1) As the substrate temperature becomes higher, the amount of hydrogen in the film becomes smaller, and the substrate temperature becomes 350 ° C.
When the temperature is set to 400 ° C. or higher, the amount of hydrogen in the film is drastically reduced. Therefore, generation of defects due to desorption of hydrogen generated when the temperature is raised to a solid phase growth temperature of about 550 ° C. to 650 ° C. is reduced. However, since the temperature at which hydrogen in the film is almost completely desorbed shifts to a higher temperature side as compared with a film formed at a low temperature, when the temperature is increased to a gate oxidation temperature of about 1000 ° C. to 1200 ° C., it will be described later. Therefore, it is important to optimize the heating rate and the heating method. When a film formed at a substrate temperature of about 500 ° C. or higher is subjected to solid phase growth, polycrystalline silicon oriented in <110> can be obtained, so that the interface state density of the TFT can be reduced and the field effect mobility can be improved. And so on. (2) A film formed at a substrate temperature of about 350 ° C. or less contains a large amount of hydrogen. Therefore, as described above, it is important to remove hydrogen from the film so as not to generate many defects in the film before performing the solid phase growth at about 550 ° C. to 650 ° C. When desorption of hydrogen is performed under favorable conditions, the crystal grain size of polycrystalline silicon tends to increase as the film formation temperature decreases. However, the lower the temperature,
Since the crystallization rate after solid-phase growth tends to be low, it is important to optimize the rate of temperature rise and the method of temperature rise after solid-phase growth, as described later.

The present invention is not limited to a film formed by a plasma CVD method, but also includes a method in which amorphous silicon or microcrystalline silicon is formed by an evaporation method, a CVD method, an EB evaporation method, an MBE method, a sputtering method, or the like. After forming crystalline silicon or polycrystalline silicon by a plasma CVD method, a CVD method, an evaporation method, an EB evaporation method, an MBE method, a sputtering method, or the like, Si, Ar,
It is also effective when the element such as B, P, He, Ne, Kr, or H is ion-implanted to form the microcrystalline silicon or the polycrystalline silicon by completely or partially amorphizing. It is. In particular, a film in which the proportion of the amorphous phase in the as-depo film is high and the density of polycrystalline nuclei generated is low (that is, a polycrystalline silicon having a large grain size is easily formed by the solid phase growth method) is the present invention. Has a great effect.

Next, a description will be given of a heat treatment condition in the present invention, in particular, a method of raising the temperature to a predetermined temperature (for example, a gate oxidation temperature). FIG. 3 is an example of a schematic view of a temperature raising method according to the embodiment of the present invention. In FIG. 3, FIG.
As shown in (b), annealing is performed at a predetermined temperature (T ₁ ) in an atmosphere of an inert gas such as argon, nitrogen, or the like, so that the silicon layer 102 is solid-phase grown to form a polycrystalline silicon layer 103. The case where the gate oxidation is performed by increasing the temperature to a predetermined gate oxidation temperature (T ₂ ) at a predetermined temperature rising rate will be described. T ₁
The rate of temperature rise from T ₂ to T ₂ is preferably lower than about 20 ° C./min (preferably 5 ° C./min) because the crystallization rate after gate oxidation is high. Further, there is a method in which the temperature is increased while switching the atmosphere from an inert gas atmosphere such as argon or nitrogen to an atmosphere containing at least one of oxygen, water vapor, hydrogen chloride, etc. during the oxidation, while the oxidation proceeds. (This method can also be applied to the heating method described below.) The heating rate does not need to be constant at all times, and may vary within the above-described range. Further, after heat treatment at a temperature T _1, there once the sample is removed, a method of raising the temperature to T ₂ again at a predetermined heating rate. (However, continuous heat treatment is advantageous in terms of time and crystallinity.) FIG. 3B shows a predetermined temperature (T) as shown in FIG. 1B.
Annealing in ₁ ) to form the polycrystalline silicon layer 103 by solid-phase growth of the silicon layer 102, and then increasing the temperature at a lower rate as the temperature increases to a predetermined gate oxidation temperature (T ₂ ). And the case of performing gate oxidation. Especially when the temperature is 8
In the region exceeding about 00 ° C. to 1000 ° C., the heating rate is 5
It is desirable that the temperature be lower than ° C / min. On the other hand, 700
At about ° C or lower, the temperature raising rate may be higher than 10 ° C / min.

FIG. 3 (c) shows a polycrystalline silicon layer 103 by annealing at a predetermined temperature (T ₁ ) to solid-phase-grow the silicon layer 102 as shown in FIG. 1 (b). A case is shown in which the temperature is raised to a predetermined temperature (T ₂ ) at a predetermined heating rate, held for a predetermined time, and then raised to a predetermined gate oxidation temperature (T ₃ ) at a predetermined heating rate. By maintaining the temperature (T ₂ ) lower than the gate oxidation temperature (T ₃ ) for a predetermined time (for example, about 10 minutes to 1 hour), the crystallinity is not impaired.
The crystallization rate can be increased. Therefore, hardly occur generation of defects by faster heating rate is when the temperature is raised to the gate oxidation temperature after a predetermined time held at T _2. T ₂ is 700
C. to about 900.degree. C. is desirable. In addition, a predetermined temperature (T ₂ )
Need not be kept constant. For example, the temperature may be raised slowly at a temperature rising rate lower than 5 ° C./min. Further, there may be a plurality of temperatures (T ₂ ) maintained at the predetermined temperature. For example, 70
There is also a method of once holding at about 0 ° C. and then holding again at about 800 ° C., which has the effect of further reducing defects in the film.

FIG. 3D shows a predetermined gate oxidation temperature (T
₁ ) The case where the gate oxidation is performed by increasing the temperature at a predetermined temperature raising rate until the solid temperature growth is performed, and the solid phase growth is performed while increasing the temperature without particularly providing a step of performing the solid phase growth while maintaining the predetermined temperature. And the processing time can be reduced. The rate of temperature rise to T ₁ is preferably lower than 5 to 10 ° C./min (preferably 2 ° C./min) to increase the crystallization rate in order to promote solid phase growth while increasing the temperature. It is to be noted that the heating rate does not need to be always constant, and may be changed within the above range.

FIG. 3E shows a predetermined gate oxidation temperature (T
Until ₁ ), the case where the temperature is increased at a lower temperature as the temperature becomes higher and the temperature is increased to perform gate oxidation is shown. In particular, when the temperature is 700
In the region exceeding about 1000 ° C. to 1000 ° C., the heating rate is set to 5 ° C. /
It is desirable to set the time to be smaller than the minute (preferably 2 ° C./min) because the crystallinity of the polycrystalline silicon is improved. On the other hand, in the region where the temperature is 250 ° C. or less, even if the rate of temperature rise is higher than 40 ° C./min, there is almost no effect on the crystallinity of polycrystalline silicon, which leads to a reduction in the time required for temperature rise. In the region of about 300 ° C. to 500 ° C., the desorption of hydrogen in the film proceeds.
It is desirable that the rate of temperature rise be lower than 10 ° C./min (preferably 2 to 4 ° C./min). Since solid phase growth proceeds in the region of 500 ° C. to 700 ° C., 5 ° C./min (preferably 2 ° C./min.
It is desirable that the heating rate be lower than that of (minute).

It should be noted that the use of a plurality of the combinations shown in FIGS. 3A to 3E can further suppress the occurrence of defects and improve the crystallinity and the crystallization ratio. Also,
FIGS. 3A to 3E are examples of the present embodiment, and the present invention is not limited thereto.

FIG. 1D shows a step of forming a semiconductor element. In FIG. 1D, a TFT is used as a semiconductor element.
Is formed as an example. In the figure, 104 indicates a gate insulating film, 105 indicates a gate electrode, 106 indicates a source / drain region, 107 indicates an interlayer insulating film, 108 indicates a contact hole, and 109 indicates a wiring. As an example of a TFT forming method, after forming a gate electrode, a source / drain region is formed by an ion implantation method, a thermal diffusion method, a plasma doping method, etc.
It is formed by a VD method, a sputtering method, a plasma CVD method, or the like.
Further, a TFT is formed by forming a contact hole in the interlayer insulating film and forming a wiring.

In this embodiment, the case where gate oxidation is performed as the high-temperature heat treatment is described as an example, but the present invention is not limited to this. For example, a predetermined temperature (for example, 70
After the temperature is raised at a predetermined temperature rising rate to about 0 ° C. to 1200 ° C.), the heat treatment may be simply performed at the predetermined temperature.
However, in the case of forming an insulated gate type semiconductor element, it is effective to use the above-described heat treatment in the gate oxidation step, because the step can be shortened.

The field-effect mobility of a polycrystalline silicon TFT (N-channel) manufactured by the method of manufacturing a semiconductor device according to the present invention is 150 to 200 cm 2 / V · sec. It can be formed by a process.

Further, a step of exposing the semiconductor element to a plasma atmosphere of a gas containing at least hydrogen gas or ammonia gas is provided in the TFT manufacturing step,
Is hydrogenated, the density of defects existing in the crystal grain boundaries is reduced, and the field-effect mobility is further improved.

A means for doping an impurity in the channel region to control Vth (threshold voltage) is also very effective. Polycrystalline silicon T formed by solid phase growth method
In FT, the Nth transistor tends to shift Vth in the depletion direction, and the P channel transistor tends to shift in the enhancement direction. When the TFT is hydrogenated, the tendency becomes more remarkable. Therefore, 10 ¹⁵ to 10 ¹⁹ / cm ^{3 is set in} the channel region.
By doping a certain amount of impurities, the shift of Vth can be suppressed. For example, in FIG. 1, there is a method of implanting an impurity such as B (boron) with a dose of about 10 ¹¹ to 10 ¹³ / cm ² by ion implantation or the like before forming the gate electrode. In particular, when the dose is about the above-described value, Vth can be controlled so that the off-state current of both the P-channel transistor and the N-channel transistor is minimized. Therefore, even when a CMOS type TFT element is formed, the entire surface can be channel-doped in the same step without selectively channel-doping Pch and Nch.

It should be noted that the present invention relates to the TF shown in the embodiment of FIG.
In addition to T, it can be applied to insulated gate semiconductor devices in general, and semiconductor devices such as bipolar transistors, static induction transistors, photoelectric conversion devices such as solar cells and optical sensors are formed using polycrystalline semiconductors as device materials. This is an extremely effective manufacturing method.

[0035]

As described above, according to the present invention, the following effects can be obtained. (A) According to the present invention, a large grain polycrystalline silicon film can be formed by a simple manufacturing process. (B) At a temperature of about 550 ° C. to 650 ° C., hydrogen in the silicon film is not sufficiently removed, and crystal growth is hindered.
By setting the temperature to 0 ° C. or higher, hydrogen can be sufficiently removed. 550 ° C.-65
Annealing the silicon film at 0 ° C. can promote crystal growth.

The present invention is also applicable to the T shown in FIG.
In addition to FT, it can be applied to insulated gate semiconductor devices in general, and semiconductor devices such as bipolar transistors, electrostatic induction transistors, photoelectric conversion devices such as solar cells and optical sensors, etc. are formed using polycrystalline semiconductors as device materials. This is an extremely effective manufacturing method.

[Brief description of the drawings]

1 (a) to 1 (d) are manufacturing process diagrams of a semiconductor device according to an embodiment of the present invention.

FIGS. 2A to 2D are schematic diagrams of a temperature raising method in Examples and Reference Examples of the present invention.

FIGS. 3A to 3E are schematic diagrams of a temperature raising method according to an embodiment of the present invention.

[Explanation of symbols]

 101 Insulating amorphous material 102 Silicon layer 103 Polycrystalline silicon layer 104 Gate insulating film 105 Gate electrode 106 Source / drain region 107 Interlayer insulating film 108 Contact hole 109 Wiring

Claims (1)

(57) [Claims] 1. A silicon layer is formed on a substrate, the substrate is heated to a predetermined temperature of 550 ° C. to 650 ° C., and the substrate is heated to 700 ° C. or higher.
A method for manufacturing a semiconductor device, wherein the silicon layer is annealed at a temperature of about 650 ° C.