JP2906470B2 - Active matrix substrate - Google Patents
Active matrix substrateInfo
- Publication number
- JP2906470B2 JP2906470B2 JP21648189A JP21648189A JP2906470B2 JP 2906470 B2 JP2906470 B2 JP 2906470B2 JP 21648189 A JP21648189 A JP 21648189A JP 21648189 A JP21648189 A JP 21648189A JP 2906470 B2 JP2906470 B2 JP 2906470B2
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- line
- electrode
- film
- constant voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000758 substrate Substances 0.000 title claims description 23
- 239000011159 matrix material Substances 0.000 title claims description 11
- 239000010408 film Substances 0.000 claims description 52
- 239000010409 thin film Substances 0.000 claims description 41
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 239000004973 liquid crystal related substance Substances 0.000 description 11
- 239000004065 semiconductor Substances 0.000 description 7
- 230000007547 defect Effects 0.000 description 6
- 239000011229 interlayer Substances 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 125000004437 phosphorous atom Chemical group 0.000 description 2
- 239000000565 sealant Substances 0.000 description 2
- 238000002834 transmittance Methods 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000012780 transparent material Substances 0.000 description 1
Landscapes
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Description
【発明の詳細な説明】 ［産業上の利用分野］ 本発明は、液晶パネルといったフラットパネルディス
プレイに用いるアクティブマトリックス基板の構造に関
する。The present invention relates to a structure of an active matrix substrate used for a flat panel display such as a liquid crystal panel.
［従来の技術］ 絶縁性基板上にアモルファスシリコン，多結晶シリコ
ン薄膜等を能動領域として用いた薄膜トランジスターを
マトリックス状に配置し、もう一枚の透明絶縁基板とで
液晶を封じ込めた液晶パネルは、小型液晶テレビ，壁掛
けテレビ，投影型液晶ディスプレイ等応用が広い。[Prior art] A liquid crystal panel in which thin film transistors using amorphous silicon, polycrystalline silicon thin film and the like as an active area are arranged in a matrix on an insulating substrate, and the liquid crystal is sealed with another transparent insulating substrate, Widely applicable for small LCD TVs, wall mounted TVs, projection type LCD displays, etc.
第３図は、前記液晶パネルのアクティブマトリックス
基板の等価回路である。１はｎ本のデータ線群（S1……
…Sn）,2はｍ本の走査線群（G1………Gm）,3はｍ×ｎ個
の薄膜トランジスター、５は液晶容量、４は付加容量で
ある。○印は、対向基板の電極端子であり共通に短絡さ
れている、第４図は、液晶パネルの概略断面図である。FIG. 3 is an equivalent circuit of the active matrix substrate of the liquid crystal panel. 1 is a group of n data lines (S 1 ...)
... Sn), 2 are m scanning line groups (G 1 ... Gm), 3 is m × n thin film transistors, 5 is a liquid crystal capacitor, and 4 is an additional capacitor. The circles indicate the electrode terminals of the counter substrate and are commonly short-circuited. FIG. 4 is a schematic sectional view of the liquid crystal panel.
６は、絶縁性基板からなるアクティブマトリックス基
板、７は透明画素電極、８は絶縁性対向基板、９は透明
対向電極、10は、薄膜トランジスターの光リーク電流及
び、画素電極間のもれ光を遮断する遮光膜、11は、液
晶、12はシール剤、13は下偏光板、14は上偏光板であ
る。6 is an active matrix substrate made of an insulating substrate, 7 is a transparent pixel electrode, 8 is an insulating counter substrate, 9 is a transparent counter electrode, and 10 is a light leak current of a thin film transistor and light leaking between pixel electrodes. A light shielding film for blocking, 11 is a liquid crystal, 12 is a sealant, 13 is a lower polarizing plate, and 14 is an upper polarizing plate.
第５図（ａ）は、第３図の等価回路の中の一画素の構
造を示す平面図、（ｂ）は、（ａ）内のａ−ａ′断面図
である。FIG. 5 (a) is a plan view showing the structure of one pixel in the equivalent circuit of FIG. 3, and FIG. 5 (b) is a sectional view taken along the line aa 'in FIG.
透明絶縁性基板６上に、アモルファスシリコン，多結
晶シリコン薄膜15を堆積し、パターニングして能動領域
とする。次にゲート絶縁膜16をCVD法で堆積するか、シ
リコン薄膜を酸化して形成したあと、ゲート電極，ゲー
ト配線（走査線）17となる多結晶シリコン薄膜や、金属
薄膜を堆積し、パターニングする。次に、別の導電薄膜
を堆積しパターニングして、定電圧共通線18とする。定
電圧共通線18は、ゲート線17と同一材料とすることもで
きるが、画素中央を横切ることが多く、画素電極の開口
率を低下させる原因となるため、透明導電膜とする場合
が多い。An amorphous silicon and polycrystalline silicon thin film 15 is deposited on the transparent insulating substrate 6 and patterned to form an active area. Next, a gate insulating film 16 is deposited by a CVD method or a silicon thin film is formed by oxidation, and then a polycrystalline silicon thin film or a metal thin film serving as a gate electrode and a gate wiring (scanning line) 17 is deposited and patterned. . Next, another conductive thin film is deposited and patterned to form a constant voltage common line 18. The constant voltage common line 18 can be made of the same material as that of the gate line 17, but is often made of a transparent conductive film because it often crosses the center of the pixel and causes a reduction in the aperture ratio of the pixel electrode.
次に、ゲート電極17をマスクにして、Ｎ型薄膜トラン
ジスターをつくるならリン原子,p型薄膜トランジスター
をつくるならボロン原子をイオン打込みして、ソース・
ドレイン領域を形成する。適度なアニールの後、層間絶
縁膜19を堆積し、ソース・ドレイン領域上にコンタクト
ホールを開口した後、透明導電膜を堆積しパターニング
して、透明画素電極20を形成する。次に、金属材料を堆
積しパターニングして、ソース線（データ線）21とす
る。第３図中の付加容量４は、透明画素電極20と、定電
圧共通線18の間の層間絶縁膜19によりつくりこまれてい
る。Next, using the gate electrode 17 as a mask, a phosphorus atom is implanted for forming an N-type thin film transistor, and a boron atom is implanted for forming a p-type thin film transistor.
Forming a drain region; After an appropriate annealing, an interlayer insulating film 19 is deposited, a contact hole is opened on the source / drain region, and a transparent conductive film is deposited and patterned to form a transparent pixel electrode 20. Next, a metal material is deposited and patterned to form a source line (data line) 21. The additional capacitance 4 in FIG. 3 is formed by an interlayer insulating film 19 between the transparent pixel electrode 20 and the constant voltage common line 18.
破線22に囲まれている部分が、対向基板上の開口部で
あり、ソース線21,ゲート線17上の領域は遮光膜10とな
る。A portion surrounded by a broken line 22 is an opening on the counter substrate, and a region on the source line 21 and the gate line 17 becomes the light shielding film 10.
［発明が解決しようとする課題］ 前述したように、定電圧共通線18は、開口率を高める
上で、透明な方が望ましく、透明導電膜は低融点材料が
多いことから層間絶縁膜19としては低温形成できる材
料、すなわち、CVD膜や、スパッタ膜の必要がある。通
常、この種の膜はゴミ，フレークが発生しやすいため、
ピンホールによって画素電極20と定電圧共通線が短絡す
ることが多く不良点欠陥が多発する。付加容量は大きい
方が好ましく、この場合、層間絶縁膜の膜厚を減少する
ことは困難なため、電極面積を増大するさせるわけであ
るが、点欠陥の発生率は、さらに増加する。[Problems to be Solved by the Invention] As described above, the constant voltage common line 18 is preferably transparent in order to increase the aperture ratio, and the transparent conductive film has a low melting point material. Requires a material that can be formed at a low temperature, that is, a CVD film or a sputtered film. Usually, this type of film is liable to generate dust and flakes.
The pixel electrode 20 and the constant voltage common line are often short-circuited due to the pinhole, and the defective point defect frequently occurs. It is preferable that the additional capacitance is large. In this case, since it is difficult to reduce the thickness of the interlayer insulating film, the electrode area is increased, but the incidence of point defects further increases.
この点欠陥の発生をおさえるには、容量をつくる絶縁
膜をピンホールの少ない熱酸化膜にする方法がある。第
６図は付加容量を熱酸化ゲート絶縁膜によってつくる方
法を示したもので、（ａ）は平面図、（ｂ）は（ａ）内
のａ−ａ′断面図である。具体的には、付加容量は、定
電圧共通線18と、薄膜トランジスターのドレイン電極の
延長電極との間のゲート絶縁膜容量と画素電極20と定電
圧共通線18との間の層間絶縁容量とで構成されるが、絶
縁膜厚の関係から、前者の容量が大部分を占める。した
がって、第５図に比べ、付加容量を同程度つくる場合、
電極面積を１桁近く小さくできるため、面積，膜質から
ピンホールによる点欠陥は、著しく減少する。In order to suppress the occurrence of this point defect, there is a method in which a thermal oxide film having few pinholes is used as an insulating film for forming a capacitor. FIGS. 6A and 6B show a method of forming an additional capacitance by a thermal oxidation gate insulating film, wherein FIG. 6A is a plan view and FIG. 6B is a sectional view taken along line aa 'in FIG. Specifically, the additional capacitance is a constant voltage common line 18, a gate insulating film capacitance between the extension electrode of the drain electrode of the thin film transistor, and an interlayer insulating capacitance between the pixel electrode 20 and the constant voltage common line 18. However, due to the thickness of the insulating film, the former capacity occupies the majority. Therefore, compared to FIG. 5, when the additional capacity is made approximately the same,
Since the electrode area can be reduced by almost one digit, point defects due to pinholes are remarkably reduced from the area and film quality.
しかし、定電圧共通線18の材料を透明材料としても、
ドレイン領域が半透明な半導体薄膜なので透過率が低下
し、開口率の低下の原因となる。However, even if the material of the constant voltage common line 18 is a transparent material,
Since the drain region is a semi-transparent semiconductor thin film, the transmittance is reduced, which causes the aperture ratio to be reduced.
定電圧共通線18をゲート線17に近接させれば、開口率
は向上できるが、２つの配線間距離Ｗは、長い平行配線
では、短絡する可能性が強いため、限界があり、画素中
央部を通ることな避けづらい。If the constant voltage common line 18 is brought close to the gate line 17, the aperture ratio can be improved, but the distance W between the two wirings is limited due to the strong possibility of short-circuiting in a long parallel wiring. It is hard to avoid passing through.
特に、高密度の画素ピッチになると、開口率にしめ
る、定電圧共通線の面積の比率が高くなり、開口率の低
下は著しい。具体的に、画素ピッチが縦50μm,横50μｍ
ぐらいの高密度パネルでは、開口率は十分な付加容量
（液晶容量の３〜５倍程度）をつくる場合、20％程度に
なり、パネル全体は遮光領域が大半をしめるため暗っぽ
い表示になる。In particular, when the pixel pitch is high, the ratio of the area of the constant voltage common line that increases the aperture ratio increases, and the aperture ratio decreases significantly. Specifically, the pixel pitch is 50 μm vertically and 50 μm horizontally
For a high-density panel of about the same size, the aperture ratio becomes about 20% when a sufficient additional capacity (about 3 to 5 times the liquid crystal capacity) is created, and the entire panel becomes dark because the light-shielding area is mostly covered. .
本発明の目的は、高密度パネルにおいても、十分な付
加容量をつくり、かつ開口率の高いパネルが実現できる
アクティブマトリックス基板を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide an active matrix substrate capable of producing a sufficient additional capacitance and realizing a panel having a high aperture ratio even in a high-density panel.
［課題を解決するための手段］ 本発明は、基板にソース線と、ゲート線と、前記ソー
ス線及びゲート線に接続された薄膜トランジスターと、
前記薄膜トランジスターに接続された画素電極と、前記
薄膜トランジスターのソース・ドレイン領域となるシリ
コン薄膜に連結された第１電極と、誘電体膜を隔てて前
記第１電極に対向配置された共通線とを有するアクティ
ブマトリックス基板であって、 前記共通線と前記第１電極とは絶縁膜を介して前記ソ
ース線に重なっていることを特徴とする。[Means for Solving the Problems] The present invention provides a source line, a gate line, a thin film transistor connected to the source line and the gate line on a substrate,
A pixel electrode connected to the thin film transistor, a first electrode connected to a silicon thin film that is to be a source / drain region of the thin film transistor, and a common line opposed to the first electrode with a dielectric film interposed therebetween. Wherein the common line and the first electrode overlap the source line via an insulating film.
［作用］ 本発明は、開口率を上げるために、定電圧共通線を、
ソース線やゲート線や薄膜トランジスターを遮光する遮
光領域に配置した。そのために、ソース線や、ゲート線
と短絡しないように多層配線とした。具体的には、定電
圧共通線上には、第１の絶縁膜、薄膜トランジスターの
半導体膜、第２の絶縁膜が形成され、その上に、ゲート
線あるいは、ソース線が配線されている。[Operation] In the present invention, a constant voltage common line is used to increase the aperture ratio.
The source line, the gate line, and the thin film transistor were arranged in a light shielding region for shielding light. For this reason, a multilayer wiring is used so as not to short-circuit with a source line or a gate line. Specifically, a first insulating film, a semiconductor film of a thin film transistor, and a second insulating film are formed on the constant voltage common line, and a gate line or a source line is provided thereon.
第１の絶縁膜、第２の絶縁膜は、それぞれ、定電圧共
通線、半導体薄膜の熱酸化膜とすれば、ピンホールの少
ない絶縁膜となり、点欠陥の少ない高密度パネルが実現
できる。If the first insulating film and the second insulating film are a constant voltage common line and a thermal oxide film of a semiconductor thin film, respectively, the insulating film has few pinholes, and a high-density panel with few point defects can be realized.
［実施例］ 第１図は、本発明の第１の実施例を示すもので定電圧
共通線を、ソース線と近接あるいは、重畳させた構造の
場合である。（ａ）は、構造の平面図であり、（ｂ），
（ｃ）は、（ａ）内のａ−ａ′,b−ｂ′断面図である。[Embodiment] FIG. 1 shows a first embodiment of the present invention, in which a constant voltage common line is adjacent to or overlapped with a source line. (A) is a plan view of the structure, (b),
(C) is a sectional view taken along aa 'and bb' in (a).
工程順に説明すれば、絶縁性基板６上に、導電膜を堆
積し、パターニングして定電圧共通線18とする。導電膜
は、金属でもよいし、高濃度不純物が添加された多結晶
シリコン薄膜でもよい。次に絶縁膜23を堆積する。誘電
体膜である絶縁膜は、CVD法、スパッタ法等によるSiO2
膜か、熱酸化法による定電圧共通線の酸化膜でもよい。
次に多結晶シリコン薄膜，アモルファスシリコン薄膜等
の半導体薄膜15を堆積しパターニングして、能動領域を
形成する。In the order of steps, a conductive film is deposited on the insulating substrate 6 and patterned to form the constant voltage common line 18. The conductive film may be a metal or a polycrystalline silicon thin film to which a high concentration impurity is added. Next, an insulating film 23 is deposited. The insulating film, which is a dielectric film, is made of SiO 2 by a CVD method, a sputtering method, or the like.
It may be a film or an oxide film of a constant voltage common line by a thermal oxidation method.
Next, a semiconductor thin film 15 such as a polycrystalline silicon thin film or an amorphous silicon thin film is deposited and patterned to form an active region.
付加容量は、絶縁膜23の膜厚、膜質、容量を構成する
半導体薄膜15と定電圧共通線18の電極面積に依存する。
熱酸化法によって構成された絶縁膜は、ピンホールも少
なく、均一なため、膜厚もうすくでき、電極面積も小さ
くできる長所をもつ。The additional capacitance depends on the thickness of the insulating film 23, the film quality, and the electrode area of the semiconductor thin film 15 and the constant voltage common line 18 which constitute the capacitance.
The insulating film formed by the thermal oxidation method has advantages in that pinholes are small and uniform, so that the thickness can be reduced and the electrode area can be reduced.
次に、半導体薄膜15を熱酸化するか、同様なCVD法に
よりゲート絶縁膜16を形成し、つづいて、高ドーピング
多結晶シリコン薄膜あるいは金属薄膜を堆積し、パター
ニングして、ゲート電極、ゲート線17を形成する。次
に、前記ゲート電極をマスクにして、Ｎ型薄膜トランジ
スターであれば、リン原子,P型薄膜トランジスターであ
れば、ボロン原子をイオン打込みした後、アニールし
て、ソースドレイン領域24,25を形成する。Next, the semiconductor thin film 15 is thermally oxidized or a gate insulating film 16 is formed by a similar CVD method, and then a highly doped polycrystalline silicon thin film or a metal thin film is deposited and patterned to form a gate electrode and a gate line. Form 17. Next, using the gate electrode as a mask, an N-type thin film transistor is ion-implanted with phosphorus atoms, and a P-type thin film transistor is ion-implanted with boron atoms, followed by annealing to form source / drain regions 24 and 25. I do.
次に、CVD法により層間絶縁膜19を堆積し、コンタク
トホールを開口する。透明導電膜を堆積しパターニング
して透明画素電極20,金属薄膜を堆積して、パターニン
グによりソース線21を形成する。このような工程によ
り、薄膜トランジスターはソース線21にソース領域、ゲ
ート線にゲート電極、透明画素電極20にドレイン領域が
連結され、ドレイン領域と連結する電極と誘電体膜であ
る絶縁膜23を隔てて定電圧共通線18が対向配置されるこ
とになる。Next, an interlayer insulating film 19 is deposited by a CVD method, and a contact hole is opened. A transparent conductive film is deposited and patterned to deposit a transparent pixel electrode 20, a metal thin film, and a source line 21 is formed by patterning. Through such a process, the thin film transistor has a source region connected to the source line 21, a gate electrode connected to the gate line, a drain region connected to the transparent pixel electrode 20, and an electrode connected to the drain region and an insulating film 23 serving as a dielectric film. As a result, the constant voltage common lines 18 are arranged to face each other.
定電圧共通線は、共通線上に、チャンネルシリコン薄
膜が形成されているときはチャンネル反転がおこらない
ように、接地電位にしておくのが好ましい。また、定電
圧共通線上からチャンネル領域をずらしておけば、定電
圧のレベルは自由に変えることができる。定電圧共通線
は、ソース線から少々ずれてもかまわないがずれ量によ
り、遮光領域が増加し、破線22が画素電極の内側にくる
ため開口率は、少々低下する。The constant voltage common line is preferably set to the ground potential so that channel inversion does not occur when a channel silicon thin film is formed on the common line. If the channel region is shifted from the constant voltage common line, the level of the constant voltage can be freely changed. The constant voltage common line may be slightly deviated from the source line, but the amount of deviation increases the light-shielding region and the broken line 22 comes inside the pixel electrode, so that the aperture ratio slightly decreases.
第２図は、本発明の第２の実施例を示すもので定電圧
共通線を、ゲート線と近接あるいは、重畳させた構造の
場合である。（ａ）は、構造の平面図であり、（ｂ），
（ｃ）は、ａ−ａ′,b−ｂ′断面図である。FIG. 2 shows a second embodiment of the present invention, in which a constant voltage common line is in the vicinity of or overlapped with a gate line. (A) is a plan view of the structure, (b),
(C) is a sectional view taken along aa 'and bb'.
プロセスは、第１図のものと同じなので省略する。第
６図と比較すると、定電圧共通線と、ゲート線が多層配
置になっているため、定電圧共通線とゲート線の間隔を
なくすことが可能である。The process is the same as that of FIG. Compared to FIG. 6, since the constant voltage common line and the gate line are arranged in a multilayer structure, it is possible to eliminate the interval between the constant voltage common line and the gate line.
したがって、第６図に比べれば、透過率と開口率を向
上できる。Therefore, as compared with FIG. 6, the transmittance and the aperture ratio can be improved.
［発明の効果］ 本発明によれば、共通線とソース線とは絶縁膜を介し
て重なる構造となるため、画素の開口率を向上させるこ
とができる。[Effect of the Invention] According to the present invention, the common line and the source line have a structure in which the common line and the source line overlap with the insulating film interposed therebetween, so that the aperture ratio of the pixel can be improved.
これは、高密度画素をもつパネル（例えば、ビデオプ
ロジェクターのライトバルブ）のような場合には一層効
果がある。This is more effective in the case of a panel having high-density pixels (for example, a light valve of a video projector).
また、付加容量の絶縁膜を熱酸化膜にした場合ピンホ
ールが少なく、点欠陥の少ないパネルが実現でき歩留り
が向上、コストダウンにつながる。Further, when the insulating film of the additional capacitance is a thermal oxide film, a panel having few pinholes and few point defects can be realized, leading to an improvement in yield and a reduction in cost.
第１図，第２図は、本発明の実施例を示す、アクティブ
マトリックス基板の平面図と断面図である。 第３図は、アクティブマトリックス基板の基本回路図で
ある。 第４図は、アクティブマトリックス基板を用いた液晶パ
ネルの構造断面図である。 第５図，第６図は、従来のアクティブマトリックス基板
の平面図と断面図である。 １……ソース線（データ線） ２……ゲート線（走査線） ３……薄膜トランジスター ４……付加容量 ５……液晶容量 ６……絶縁性基板 ７……画素電極 ８……対向基板 ９……対向電極 10……遮光層 11……液晶 12……シール剤 13……下偏光板 14……上偏光板 15……半導体薄膜 16……ゲート絶縁膜 17……ゲート線（ゲート電極） 18……定電圧共通線 19……層間絶縁膜 20……画素電極 21……ソース線 22……対向基板の開口領域と遮光領域の境界 23……付加容量絶縁膜 24……ソース領域 25……ドレイン領域1 and 2 are a plan view and a sectional view of an active matrix substrate showing an embodiment of the present invention. FIG. 3 is a basic circuit diagram of the active matrix substrate. FIG. 4 is a structural sectional view of a liquid crystal panel using an active matrix substrate. 5 and 6 are a plan view and a sectional view of a conventional active matrix substrate. DESCRIPTION OF SYMBOLS 1 ... Source line (data line) 2 ... Gate line (scanning line) 3 ... Thin film transistor 4 ... Additional capacitance 5 ... Liquid crystal capacitance 6 ... Insulating substrate 7 ... Pixel electrode 8 ... Counter substrate 9 ...... Counter electrode 10 ...... Light shielding layer 11 ...... Liquid crystal 12 ...... Sealant 13 ...... Lower polarizing plate 14 ...... Upper polarizing plate 15 ...... Semiconductor thin film 16 ...... Gate insulating film 17 ...... Gate line (gate electrode) 18: constant voltage common line 19: interlayer insulating film 20: pixel electrode 21: source line 22: boundary between the opening region of the opposing substrate and the light shielding region 23: additional capacitance insulating film 24: source region 25 ... ... Drain region
Claims (2)
ス線及びゲート線に接続された薄膜トランジスターと、
前記薄膜トランジスターに接続された画素電極と、前記
薄膜トランジスターのソース・ドレイン領域となるシリ
コン薄膜に連結された第１電極と、誘電体膜を隔てて前
記第１電極に対向配置された共通線とを有するアクティ
ブマトリックス基板であって、 前記共通線と前記第１電極とは絶縁膜を介して前記ソー
ス線に重なっていることを特徴とするアクティブマトリ
ックス基板。A source line, a gate line, and a thin film transistor connected to the source line and the gate line on a substrate;
A pixel electrode connected to the thin film transistor, a first electrode connected to a silicon thin film that is to be a source / drain region of the thin film transistor, and a common line opposed to the first electrode with a dielectric film interposed therebetween. Wherein the common line and the first electrode overlap the source line via an insulating film.
記絶縁膜は前記第１電極のシリコン薄膜の熱酸化膜から
なることを特徴とする請求項１に記載のアクティブマト
リックス基板。2. The active matrix substrate according to claim 1, wherein said first electrode comprises a silicon thin film, and said insulating film comprises a thermal oxide film of said first electrode silicon thin film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21648189A JP2906470B2 (en) | 1989-08-23 | 1989-08-23 | Active matrix substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21648189A JP2906470B2 (en) | 1989-08-23 | 1989-08-23 | Active matrix substrate |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP33103398A Division JP3011210B2 (en) | 1998-11-20 | 1998-11-20 | Active matrix substrate manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0380225A JPH0380225A (en) | 1991-04-05 |
| JP2906470B2 true JP2906470B2 (en) | 1999-06-21 |
Family
ID=16689109
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21648189A Expired - Lifetime JP2906470B2 (en) | 1989-08-23 | 1989-08-23 | Active matrix substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2906470B2 (en) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100268007B1 (en) * | 1992-12-22 | 2000-10-16 | 구본준 | Fabrication method of lcd |
| JP3567183B2 (en) * | 1996-08-19 | 2004-09-22 | 大林精工株式会社 | Liquid crystal display |
| KR100324914B1 (en) | 1998-09-25 | 2002-02-28 | 니시무로 타이죠 | Test method of substrate |
| GB9827901D0 (en) * | 1998-12-19 | 1999-02-10 | Secr Defence | Active semiconductor |
| JP3463007B2 (en) * | 1999-08-26 | 2003-11-05 | シャープ株式会社 | Liquid crystal display |
| TW478014B (en) | 1999-08-31 | 2002-03-01 | Semiconductor Energy Lab | Semiconductor device and method of manufacturing thereof |
| JP4700156B2 (en) | 1999-09-27 | 2011-06-15 | 株式会社半導体エネルギー研究所 | Semiconductor device |
| US6624856B2 (en) * | 2000-07-07 | 2003-09-23 | Casio Computer Co., Ltd. | Liquid crystal display device having thin film transistors for reducing leak current |
| JP4798907B2 (en) | 2001-09-26 | 2011-10-19 | 株式会社半導体エネルギー研究所 | Semiconductor device |
| CN101807583B (en) | 2009-02-18 | 2011-07-27 | 北京京东方光电科技有限公司 | TFT-LCD (Thin Film Transistor Liquid Crystal Display) array substrate and manufacture method thereof |
-
1989
- 1989-08-23 JP JP21648189A patent/JP2906470B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0380225A (en) | 1991-04-05 |
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