JP2904997B2 - Semiconductor memory device and method of manufacturing and controlling the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method for manufacturing and controlling the same. More specifically, the present invention relates to a storage device integrally provided with a nonvolatile semiconductor storage device (MROM) and a dynamic semiconductor storage device (DRAM) on the same chip.

[0002]

2. Description of the Related Art Conventionally, as a read-only nonvolatile semiconductor memory device in which storage contents are programmed in advance at the time of manufacturing,
A contact hole program type mask ROM is known. This is to store information depending on whether or not the drain of the transistor T constituting each storage element is connected to the bit lines Yn and Yn + 1 as shown in FIG. The data is written depending on whether or not a contact hole for connecting the drain is provided.

[0003]

On the other hand, a dynamic semiconductor memory device (DRAM) programmable by a user has a memory element (memory element) formed of a transistor and a capacitor as is well known, There is a problem that it is difficult to manufacture on the same chip by the same process because the structure of the storage element itself is different from that of the semiconductor memory device (DRAM).
The present invention has been made in view of such circumstances,
An object of the present invention is to provide a semiconductor device in which the storage elements of an MROM and a DRAM are made similar in structure so that both can be formed on the same chip in the same step.

[0004]

According to the present invention, a substrate and first and second regions provided on a first region and a second region, respectively, on the substrate are provided.
A semiconductor memory device includes a semiconductor memory device and a second semiconductor memory device. The first and second semiconductor memory devices each include a plurality of word lines and bit lines, and a memory element provided at each address positioned by the word lines and the bit lines. Wherein each of the memory elements has a capacitance element, a switching element, and a word line, a bit line, and a word line such that the switching element charges and discharges the capacitance element in response to a voltage applied from the word line and the bit line. The second semiconductor memory device includes a conductive portion that electrically connects the switching element and the capacitor. In the second semiconductor memory device, a part of the conductive portion of the memory element at a predetermined address is removed so that the switching element and the capacitor are electrically connected. Not connected to
A semiconductor memory device is provided.

It is preferable that a part of the conductive portion to be removed is a connection between the switching element and the capacitor.

[0006] The invention further provides the above method for producing a semiconductor memory device, forming a step of forming a switching device on a substrate, forming a word line, an insulating film on the upper surface of the switching element and the word line Forming a contact hole in the insulating film corresponding to each address; forming a capacitor on the insulating film and connecting one electrode of the capacitor to the switching element via the contact hole; Forming a bit line, wherein in the step of forming a contact hole, a contact hole corresponding to all addresses is opened in the first region, and a contact hole having only a predetermined address is opened in the second region. And a method for manufacturing a semiconductor memory device.

Further, according to the present invention, with respect to the first semiconductor memory device, a write / read process and a refresh process are performed on each memory element so that the first semiconductor memory device functions as a write / read memory device. In the case of, driving is performed by performing a writing process of a signal “1” to all memory elements as an initial process, then continuing a refresh operation, and performing a reading process similar to that of the first semiconductor device when reading information. A control method is provided wherein a signal "1" is read from a memory element and a signal "0" is read from a non-driveable memory element, thereby causing the second semiconductor memory device to function as a read-only memory device. Is what you do.

[0008]

The first semiconductor memory device formed in the first region is:
By performing write / read processing and refresh processing on each memory element, it operates as a write / read storage device. Further, the second semiconductor memory device formed in the second region performs the writing process of the signal “1” to all the memory elements as an initial process, and then continues the refresh operation. By performing a similar read process, the signal “1” is read from the drivable memory element and the signal “0” is read from the non-drivable memory element, so that the second semiconductor storage device is a read-only storage device. Operate.

Therefore, each of the memory elements of the first and second semiconductor devices has a switching element and a capacitive element, and only the difference between the two elements is electrically connected to the two and not connected. Therefore, the first and second semiconductor memory devices can be formed on the same substrate (same chip) in the same process. The electrical connection between the switching element and the capacitor can be easily determined in the manufacturing process, for example, by making a contact hole in an insulating film interposed between the switching element and the capacitor. That is, the MROM area and the DRAM area on the memory map can be arbitrarily set by the ROM mask and the fuse.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the embodiments shown in the drawings. This does not limit the present invention. FIG. 1 is a circuit diagram of a semiconductor memory device showing an embodiment of the present invention, and FIG. 2 is an enlarged circuit diagram of a main part of FIG.

In these figures, 1 is a first semiconductor memory device, and 2 is a second semiconductor memory device. x ₀ , x ₁ ... x
_n, x _{n + 1} word lines provided in the first semiconductor memory device 1, the _{y 0, y 1, y 2} ...... y n-1, y n, y n + 1 is the first semiconductor memory device 1 Provided are bit lines, and each address located by these is provided with a memory element consisting of a capacitance C and a transistor T.

In the first semiconductor memory device 1, in all the memory elements, the drain of the transistor T is connected to the bit line, the gate of the transistor T is connected to the word line, and the source of the transistor T is connected to one electrode of the capacitor C. It is connected. That is, the first semiconductor device 1 has the same configuration as a known DRAM, and has a structure as a writable and readable storage device.

The second semiconductor memory device 2 includes word lines X ₀ , X ₁ ... X _n , X _{n + 1} and bit lines Y ₀ , Y ₁ , Y.
₂ ... Y _n−1 , Y _n , and Y _{n + 1,} and each address positioned by these is provided with a memory element including a capacitor C and a transistor T similarly to the first semiconductor device 1.

The first semiconductor device 1 and the second semiconductor device 2 are formed on the same chip. Each memory element of the first semiconductor device 1 has a word line and a bit so that the transistor T charges and discharges the capacitor C in response to the voltage applied from the word line and the bit line, as shown as an element Ma in FIG. It has a complete conductive circuit that electrically connects the lines, switching elements and capacitors.

On the other hand, the second semiconductor memory device includes not only the element Ma but also an element Mb (FIG. 2) in which the charge / discharge operation of the capacitor C is not possible due to the lack of a part P of the conductive circuit. .

That is, in the memory element Ma, the drain D, the gate G and the source S of the transistor T are respectively connected to the bit line, the word line and one electrode of the capacitor C, and the other electrode of the capacitor C is connected to the ground line. However, in the memory element Mb, the connection P between the source S of the transistor T and one electrode of the capacitor C is electrically insulated.

When the storage device shown in FIG. 1 is incorporated in a known memory control device, the first semiconductor storage device 1 can arbitrarily perform information writing and reading operations while continuing a refresh operation, similarly to a conventional DRAM. Can do it.

Regarding the second semiconductor device 2, as a process after power-on, a "1" level data write process is performed on all the memory elements by the same operation as that of the DRAM, and thereafter the refresh operation similar to that of the DRAM is continued. . At the time of reading information, data “1” is output from the address having the element Ma, and data “0” is output from the address having the element Mb by outputting the data in the same manner as in the DRAM.
Is read every time. That is, the second semiconductor storage device functions as a read-only storage device.

The element Mb, together with the element Ma, is manufactured in the same process at the time of manufacture so as to correspond to read-only storage contents (program). Further, the circuit of the element Mb is not limited to the connection part P in FIG. 2 and any part may be omitted.

Next, a method for manufacturing a semiconductor memory device having elements Ma and Mb will be described with reference to the cross-sectional view of the main part of the semiconductor memory device of the embodiment shown in FIG. In FIG. 3, the Si substrate 1
Then, a thermal oxide film 2 of SiO ₂ having a thickness of about 0.4 μm is formed to separate the elements. Further, a gate oxide film 3 having a thickness of about 100 ° is formed, and then a gate oxide film 3 having a thickness
A word line 4 is provided with a polycrystalline Si film of about 0 °.

Then, SiO ₂ spacers 5 and sidewalls 6 formed by anisotropic etching of RIE are provided on the upper and side surfaces of the word lines 4 after SiO ₂ is deposited by the CVD method.

Then, while providing diffusion regions K and R,
An SiO ₂ film 7 and a resist layer (not shown) are sequentially laminated on the entire surface as an insulating layer, a resist film having a predetermined pattern is formed, and RIE is performed using the resist film as a mask.
Of the diffusion region R corresponding to the element Ma
Only the upper SiO ₂ film 7 is removed until the surface of the diffusion region R is at least partially exposed to form a contact hole.

At this time, the SiO ₂ film 7 on the diffusion region R corresponding to the element Mb is not removed, so that no contact hole is formed. Subsequently, the resist film is removed, a polycrystalline Si layer and a resist layer (not shown) are sequentially laminated thereon, a resist film having a predetermined pattern is formed, and the polycrystalline Si layer is formed using the resist film as a mask. The lower electrode 8 of the capacitor C is formed by etching.

The lower electrode 8 of the capacitor C has a thickness of about 500.degree. And is formed by depositing a polycrystalline Si film doped with P at a high concentration by a CVD method, and patterning the film by projection exposure and anisotropic etching of RIE. It is formed by doing.

The upper electrode 10 of the capacitor C has a thickness of 80
After depositing a polycrystalline Si film which is disposed on the lower electrode 8 via a capacitor insulating film 9 of about Å SiN film and is highly doped with P with a thickness of about 1500 、, a difference between projection exposure and RIE is obtained. It is formed by isotropic etching.

Next, Si for planarization is formed on the entire surface of the substrate 1.
The O ₂ film 11 is laminated, and S 2 on the diffusion layer K of the elements Ma and Mb is formed.
A connection hole (bit connection hole) is formed by removing the iO ₂ films 7 and 11, and a bit line 12 having a predetermined pattern is formed on the entire surface of the SiO ₂ film 11 including the connection hole. Note that a known DRAM manufacturing process can be used for each of the above steps.

As described above, in the element Ma, the lower electrode 8 of the capacitor C is electrically connected to the diffusion layer R via the contact hole opened in the SiO ₂ film 7, and in the element Mb, the SiO ₂ film 7 Has no contact hole, the lower electrode 8 of the capacitor C and the diffusion layer R are electrically insulated.

The presence or absence of the contact hole is determined according to the read-only storage contents (program) as described above. In the above manufacturing process, the lower electrode 8 and the diffusion layer R are insulated from each other in the element Mb.
The bit line 12 of b may be insulated from the diffusion layer R.
Thus, the first and second semiconductor memory devices 1 and 2 shown in FIG. 1 are formed on the same substrate (chip) in the same step.

[0029]

According to the present invention, a read-only memory (MRO) programmed in the manufacturing process on the same chip
M) and a dynamic memory (DRAM) that can be written and read on the user side, and data can be read from these two memories using a common peripheral circuit. it can. That is, the MROM area and the DRAM area on the memory map are
It can be set arbitrarily by a ROM mask and a fuse.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

FIG. 2 is an enlarged view of a main part of FIG.

FIG. 3 is a cross-sectional view of a main part of the semiconductor memory device according to the embodiment;

FIG. 4 is a circuit diagram showing a conventional read-only storage device.

[Explanation of symbols]

1 the first semiconductor memory device 2 second semiconductor memory device _{X 0, X 1, ...... X} n, X n + 1 ...... word line _{Y 0, Y 1, ...... Y} n, Y n + 1 ...... bitline _{x 0, x 1, ...... x} n, x n + 1 ...... word line _{y 0, y 1, ...... y} n, y n + 1 ...... bit line Ma, Mb ...... elements C ...... capacitor T ... ... transistors

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-56-27958 (JP, A) JP-A-1-244661 (JP, A) JP-A-62-248249 (JP, A) JP-A-4- 177875 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H01L 27/108 H01L 21/8242 H01L 21/8246 H01L 27/112

Claims (4)

(57) [Claims] 1. A semiconductor device comprising: a substrate; a first semiconductor memory device and a second semiconductor memory device provided in a first region and a second region, respectively, on the substrate. A memory element provided at each address positioned by the word line and the bit line, and the word line and the bit line, wherein each of the memory elements includes a capacitive element, a switching element, and the switching element is connected to the word line and the bit line. A conductive portion that electrically connects the word line, the bit line, the switching element, and the capacitive element so as to charge and discharge the capacitive element in accordance with the applied voltage; In the memory element of the address, the part of the conductive part is removed and the switching element and the capacitor are removed.
A semiconductor memory device in which an element is not electrically connected . 2. The semiconductor memory device according to claim 1, wherein a part of the conductive portion to be removed is a connection between the switching element and the capacitor. 3. The method of manufacturing a semiconductor memory device according to claim 1, wherein: a step of forming a switching element on the substrate; a step of forming a word line to connect to the switching element; Forming a contact hole in the insulating film corresponding to each address, forming a capacitive element on the insulating film, and connecting one electrode of the capacitive element through the contact hole. A step of forming a bit line and connecting to the switching element; and forming a contact hole. In the step of forming a contact hole, a contact hole corresponding to all addresses is opened in the first region; In the semiconductor memory, a contact hole corresponding to a predetermined address is opened in the region. Storage device manufacturing method. 4. The semiconductor memory device according to claim 1, wherein the first semiconductor memory device functions as a write / read memory device by performing a write / read process and a refresh process on each memory element. As for the second semiconductor memory device, the writing process of the signal “1” is performed on all the memory elements as the initial process, and then the refresh operation is continued. At the time of reading information, the same reading process as that of the first semiconductor device is performed. By doing so, the signal "1" is read from the drivable memory element, and the signal "0" is read from the non-drivable memory element, thereby causing the second semiconductor memory device to function as a read-only memory device. Characteristic control method.