JP2904270B2 - Crosstalk error suppression method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CAD (Comp
LSI (Large Scale Integrated) in the field of Uter Aided Design
on (Integrated circuit)) or P
The present invention relates to a layout method for designing a layout of a logic circuit (or a logical connection relationship between logic circuits) such as WB (Printed Wiring Board), and more particularly to a layout design for suppressing (preferably "removing") a crosstalk error. The present invention relates to a crosstalk error suppression system.

[0002]

2. Description of the Related Art In the layout design of a logic circuit such as an LSI or a PWB, when the wiring pitch is large, it is not necessary to consider the influence of crosstalk due to adjacent wiring.
However, as the wiring pitch becomes smaller with the miniaturization of wiring patterns such as LSIs and PWBs, the influence of crosstalk cannot be ignored, and it has become necessary to consider crosstalk errors in this type of layout design.

Conventional crosstalk error suppression systems include the following.

After completion of the placement and routing, crosstalk analysis (calculation of the amount of crosstalk by adjacent wiring, etc.) is performed based on the placement and routing results, and wiring of a net causing a crosstalk error or a net causing crosstalk is performed. Modify the pattern manually.

In order to avoid the generation of a long net that is likely to cause a crosstalk error, the placement and wiring design is manually devised in advance.

In order to prevent generation of a long net likely to cause a crosstalk error, an excessively large relay buffer is inserted at the time of logic design.

In the wiring design, the occurrence of a crosstalk error is suppressed by using an automatic wiring unit that performs line length control so that the wiring route of each net is not linearly wired beyond a certain line length.

[0008]

The above-described conventional crosstalk error suppression system has the following problems.

The first problem is that after the crosstalk error is detected, the wiring result of the net (the net causing the crosstalk error) or the adjacent net (the net causing the crosstalk) is manually corrected. Therefore, the number of man-hours required for wiring correction is large, and because the wiring length of the net to be corrected is long, depending on the degree of wiring congestion, it may not be possible to completely eliminate or suppress crosstalk errors by wiring correction alone. It is.

The second problem is that it is necessary to devise a layout and wiring design manually in advance so as not to cause a crosstalk error. It is necessary to be conscious of the layout (floor plan), which is a constraint on the design, increasing the difficulty of the design, and thereby increasing the required man-hours.

The third problem is that since it is necessary to insert an excessive number of relay buffers at the time of logic design, it takes a lot of man-hours to correct the logic, and the excessive number of relay buffers deteriorates the layout accommodability or reduces power consumption. Or increase it.

The fourth problem is that it is necessary to use automatic wiring means for controlling the wire length so that the wiring route of each net is not linearly routed beyond a certain line length in the wiring design. By itself becoming longer,
Depending on the degree of wiring congestion, there is a case where the crosstalk error cannot be completely removed and suppressed only by limiting the wiring length, which means that the wiring is bent or detoured more than necessary, thereby deteriorating the layout accommodation.

In view of the above, an object of the present invention is to automatically insert a relay buffer or a relay inverter for suppressing a crosstalk error, thereby reducing the man-hour for manually correcting the crosstalk error. Another object of the present invention is to reduce and improve productivity in layout design of a logic circuit.

Even if an attempt is made to improve the crosstalk error only by correcting the wiring route of the net, if the wiring length of the net to be corrected is long, the removal and suppression of the crosstalk error may not be sufficient depending on the degree of wiring congestion. There is. On the other hand, dividing the net itself by the relay buffer or the relay inverter as in the present invention expands the possibility of suppressing the crosstalk error.

Another object of the present invention is to prevent deterioration of layout accommodation capacity and increase in power consumption due to excessive insertion of a relay buffer at the time of logic design, and to improve the characteristics of the layout target LSI and PWB. It is to achieve improvement (high integration and high speed).

In the present invention, there is a problem in the case of using an automatic wiring means for performing line length control such that a wiring route of a net is not linearly routed beyond a certain line length. Consideration is also given to "overcoming the limitations of removal and suppression" and "suppression of deterioration in layout accommodation due to unnecessary bending or detouring of wiring".

[0017]

According to the present invention, there is provided a crosstalk error suppressing system according to the first aspect of the present invention.
Logic / library input means for inputting library information for crosstalk analysis and layout / wiring result information indicating a layout / wiring result of the logic circuit laid out without considering a crosstalk error; A crosstalk amount limit value input unit for inputting crosstalk amount limit value information indicating a talk amount limit value; and a crosstalk analysis unit for a net indicated by the placement and routing result information input by the logic / library input unit. A crosstalk amount is calculated using the library information, and a cross for detecting a net having a crosstalk error is detected based on the calculation result and the crosstalk amount limit value information input by the crosstalk amount limit value input means. Talk analysis means and the crosstalk analysis means Relay buffer insertion means for selecting the type and number of relay buffers suitable for suppressing the crosstalk error for the detected `` net having a crosstalk error '', and inserting the relay buffer into the net; The relay buffer inserted into the net by the relay buffer inserting means is arranged at a position on the route of the initial wiring result of the net and at a position where the crosstalk error of the net can be suppressed, and at the target arrangement position, the arrangement error Occurs, a relay buffer arranging means for performing the arranging at a position that can be arranged near the position on the route of the initial wiring result, wiring of the net divided by the arrangement of the relay buffer by the relay buffer arranging means, and Reroute for other nets affected by the insertion and placement of relay buffers Incremental wiring means for performing, and updating the layout and wiring result information inputted by the logic / library input means by reflecting the layout and wiring result by the relay buffer inserting means, the relay buffer arranging means and the incremental wiring means, A layout / wiring result output means for outputting wiring result information to the outside, the logic / library input means, the crosstalk amount limit value input means, the crosstalk analysis means, the relay buffer insertion means, the relay buffer placement means, It has an incremental wiring means and a control means for performing overall control of the arrangement and wiring result output means.

Further, the crosstalk error suppressing system of the present invention (the invention according to claim 2) uses a logical connection information, a physical information, a library information for crosstalk analysis, and a crosstalk error with respect to a logic circuit to be laid out. Logic / library input means for inputting placement and routing result information indicating placement and routing results of the logic circuit laid out without consideration, and crosstalk limit value information indicating a crosstalk limit value of each net of the logic circuit Calculating a crosstalk amount using the crosstalk analysis library information for a net indicated by the placement and routing result information input by the logic / library input means; The calculation result and the crosstalk input by the crosstalk amount limit value input means are input. A crosstalk analyzing means for detecting a net having a crosstalk error based on the quantity limit value information, and a "net having a crosstalk error" detected by an analysis result by the crosstalk analyzing means. A type and number of relay buffers suitable for suppressing the crosstalk error are selected, a relay buffer inserting unit for inserting the relay buffer into the net, and a relay buffer inserted into the net by the relay buffer inserting unit, It is placed at a position on the route of the initial routing result and at a position where the crosstalk error of the net can be suppressed, and when another block exists at the target placement position and a placement error occurs, the placement error is allowed. Relay buffer arranging means for performing the arrangement at the target arrangement position in an overlapping manner; When the relay buffer placed by the relay placement means has a placement error, the placement error removal means for shifting the placement of the blocks so as to remove the overlap related to the placement error, and the relay buffer placement means by the relay buffer placement means. An incremental wiring means for rewiring the wiring of the net divided by the placement and the placement shift by the placement error removing means and the wiring of other nets affected by the insertion and placement of the relay buffer; The placement and routing result information input by the logic / library input unit is updated by reflecting the placement and routing result by the relay buffer placement unit, the placement error removing unit, and the incremental routing unit, and the placement and routing result information is externally stored. Output placement and routing results Input means, the logic / library input means, the crosstalk amount limit value input means, the crosstalk analysis means, the relay buffer insertion means, the relay buffer placement means, the placement error removal means, the incremental wiring means, and And control means for performing overall control of the placement and routing result output means.

[0019]

Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a first embodiment (an embodiment corresponding to the first aspect of the present invention) of a crosstalk error suppressing system according to the present invention.

The crosstalk error suppression system of the present embodiment includes a control unit 101 and a logic / library input unit 10
2, crosstalk amount limit value input means 103, crosstalk analysis means 104, and relay buffer insertion means 105
, A relay buffer arranging unit 106, an incremental wiring unit 107, and an arrangement and wiring result output unit 108.
10, crosstalk analysis library information 111, crosstalk amount limit value information 112, and placement and routing result information 113 are handled.

FIGS. 2 to 8 are diagrams for explaining the specific operation of the crosstalk error suppression system according to the present embodiment.

FIG. 9 is a flowchart showing the processing of the crosstalk error suppression system of this embodiment. This processing includes a logical connection information input step 901, a crosstalk amount limit value information input step 902, a crosstalk error net detection step 903, a relay buffer selection / insertion step 904, a relay buffer arrangement step 905, It comprises a wiring state net rewiring step 906 and a placement and routing result information update / output step 907.

Next, the operation of the thus configured crosstalk error suppression system of this embodiment will be described.

Here, as shown in FIG.
A description will be given by taking as an example the suppression of a crosstalk error relating to a part of a logical connection relationship composed of blocks 1 and gates 202 and nets 203 to 205 connected to those blocks. Although this example shows a part of the logical connection relationship, it is assumed that the actual placement and routing process is performed on the entire logical connection relationship.

A part of the logical connection relationship shown in FIG.
It is assumed that, as a result of performing the placement and routing processing regarding the steps 202 and 202, a placement and routing result as shown in FIG. Here, in the conventional layout method, the presence or absence of a crosstalk error (judgment based on a crosstalk amount limit value described later) is not considered.

In general, the crosstalk amount (VN) of a certain net (N) is determined by the wiring segment (j.j may exist in plurals) adjacent to the net and the net as shown in the following equation (1). Monotone increasing function (f) with the sum (ΣCj) of j of the inter-wire capacitance (Cj) between
(The sum symbol Σ indicates the sum for all j here).

VN = f (ΣCj) (1)

Here, the capacitance between wirings between a certain net (N) and a certain wiring segment (j) is expressed by an adjacent section (Lj) between the net and the wiring segment as shown in the following equation (2). ), The function (g) monotonically increases with respect to the adjacent distance (Wj) between the net and the wiring segment (“adjacent section” and “adjacent distance”).
Is shown in FIG. 4).

Cj = g (Lj, Wj) (2)

Therefore, in order to reduce the amount of crosstalk of a certain net, the number of adjacent wiring segments must be reduced, the length of the adjacent section between adjacent wiring segments must be reduced, and the distance between adjacent wiring segments must be reduced. It is necessary to make it longer.

Here, in order to simplify the description, the functions f and g of the equations (1) and (2) are approximated by the following simple equations (β and γ are positive coefficients. is there).

F (ΣCj) = β · ΣCj g (Lj, Wj) = γ · Lj / Wj

That is, VN is directly proportional to ΔCj, and Cj is directly proportional to Lj and inversely proportional to Wj. By approximation in this way, V indicating the crosstalk amount
N is represented by the following equation (3) (α is a positive coefficient having a relationship of α = β · γ).

VN = β · ΣCj = β · Σ (γ · Lj / Wj) = α · Σ (Lj / Wj) (3)

In the example of FIG. 3, the unit length (length 1) is set to the size shown in FIG. 3 in the vertical direction and the horizontal direction, and the net to be tested (layout) is arranged between the wiring segments whose adjacent distance is within 3 or less. Assume that it is necessary to determine the inter-wiring capacitance of the target net).

Then, the crosstalk amount (V204) of the net 204 is equal to that of the adjacent wiring segments 303 and 30.
By substituting the sum of the capacitances between the wirings between 4, 305, 307, 308, and 310 into equation (3), it can be obtained as follows.

V204 = α · (L303 / W303 + L304 / W304 + L305 / W305 + L307 / W307 + L308 / W308 + L310 / W310) = α · (3/1 + 16/2 + 11/1 + 3/3 + 14/1 + 11/1) = 48α

If the crosstalk amount limit value of the net 204 is, for example, 40α, the net 204 has a crosstalk error.

In the crosstalk error suppression system of this embodiment, the control means 101
(Logic / Library input means 102, Crosstalk amount limit value input means 10)
3. Crosstalk analyzing means 104, relay buffer inserting means 105, relay buffer arranging means 106, incremental wiring means 107, and layout and wiring result outputting means 10
8) (see FIG. 9).

First, the logic / library input means 102
Is logical connection information 10 indicating a logical connection relationship between blocks.
9. Physical information 110 indicating the arrangement result of the blocks and the wiring result of the connection between the blocks, library information 111 for calculating the amount of crosstalk necessary for crosstalk analysis, and arrangement and wiring indicating the arrangement and wiring results laid out by the conventional method The result information 113 (for example, information including the placement and routing results shown in FIG. 3) is input (step 901).

Each information input in this way is shown in FIG.
Referenced / updated by each means in FIG.

Further, a crosstalk amount limit value input means 1
03 inputs crosstalk amount limit value information 112 indicating the crosstalk amount limit value of each net (step 90).
2). Here, for example, as described above, the net 20
It is assumed that 40α is input as the crosstalk amount limit value of No. 4.

Next, the crosstalk analysis means 104 performs a crosstalk analysis on all nets using the library information 111 for calculating the amount of crosstalk, and finds a net having a crosstalk error (crosstalk amount limit value information. A net exceeding the crosstalk amount limit value indicated by 112 is detected (step 903).

In the example of FIG. 3, as described above, the net 204 is detected as a net having a crosstalk error. That is, as described above, the net 204 having the crosstalk amount of 48α (> 40α: the crosstalk amount limit value) is detected as a net having a crosstalk error.

Next, the relay buffer inserting means 105 responds to the "net having a crosstalk error" detected by the crosstalk analyzing means 104 by using the wiring length of the net, the buffer insertion position, and the buffer insertion position. Considering the crosstalk error suppression effect by
From among the prepared buffer gate types (the buffer gate type indicates the function name of the buffer), select the buffer of the optimal buffer gate type, and insert that buffer into the logical connection as a relay buffer. The logical connection information 109 and the placement and routing result information 113 are updated to reflect the insertion (step 904).

Here, the type of the relay buffer to be inserted (the type of the buffer gate) and the number of insertions can be determined in various ways. For example, it is possible to adopt the following evaluation criteria or combinations thereof. It is possible.

The type and number of relay buffers to be inserted,
The expected insertion position and the degree of suppression of the crosstalk error are calculated by a calculation formula.

The type and number of relay buffers to be inserted,
And the scheduled insertion positions are made into rules according to the crosstalk amount of the processing target net.

The type and number of relay buffers to be inserted,
And the expected insertion position are made into rules according to the wiring length of the processing target net.

The type and number of relay buffers are determined so as to minimize the number or buffer size of relay buffers to be inserted.

The type and number of the relay buffers are determined so that the delay time error is not deteriorated by the insertion of the relay buffers.

In the example shown in FIG. 3, the relay buffer inserting means 105 adds the relay buffer of the type selected based on the above-described evaluation criterion to the net 204 which is a net having a crosstalk error as shown in FIG. Gate 50 shown inside
Insert 1. Then, the logical connection information 109 is updated to indicate this. At the same time, the placement and routing result information 113 is updated so as to delete the routing result of the net 204 divided into the net 502 and the net 503 (see FIG. 6). However, at this time, the wiring result 301 in FIG.
The (initial wiring result) itself is deleted, but information indicating the route is stored in the placement and wiring result information 113.

Next, the relay buffer arranging means 106 can arrange the relay buffer inserted by the relay buffer inserting means 105 at a position on the route of the initial wiring result stored in the arrangement and wiring result information 113 or in the vicinity thereof. At a proper position and at a position where the crosstalk error of the processing target net can be suppressed, the placement result after the insertion of the relay buffer is obtained (step 905). If an arrangement error occurs at a position on the route of the initial wiring result, the arrangement is performed at a position that can be arranged near the position on the route of the initial wiring result.

For example, the relay buffer arranging means 106
Based on the insertion result of the relay buffer shown in FIG. 5, the arrangement result of the relay buffer 501 as shown in FIG. 7 is obtained.

Here, in the example of FIG. 7, the crosstalk amount between the net 502 and the net 503 formed by dividing the net 204 becomes substantially the same (that is, the net 20 is divided into two).
The relay buffer 501 is arranged at such a position that the crosstalk amount in the wiring result 301 of No. 4 becomes approximately half). In the example of FIG.
No wiring of another net exists at the arrangement position of 1. However, if it exists, the wiring that causes a wiring short circuit or a wiring prohibition violation is deleted at the same time.

After that, the incremental wiring means 107
Is for re-routing unwired nets (nets divided by the placement of relay buffers and other nets affected by the insertion and placement of the relay buffers) to reduce crosstalk errors Is obtained (step 906).

As described above, the incremental wiring means 1
In step 07, incremental wiring processing is performed on the initial layout result (layout result by the conventional method) (the relay buffer is arranged and the associated net is wired based on the actual arrangement and wiring result).

In the example of FIG. 7, the nets 502 and 503
Are performed, and the intended wiring results 801 and 802 in which the crosstalk error is suppressed as shown in FIG. 8 are obtained.

In the example of FIG. 8, the relay buffer is arranged at a position expected by the relay buffer arranging means 106 without detouring the wiring, and the wiring results 801 and 802 are generated.

Using the wiring results 801 and 802 of FIG. 8, the crosstalk amount V502 of the nets 502 and 503 is calculated.
And V503 are obtained as follows.

V502 = α · (L303 / W303 + L304 / W304 + L307 / W307 + L308 / W308) = α · (3/1 + 14/2 + 3/3 + 11/1) = 22α

V503 = α · (L305 / W305 + L308 / W308 + L310 / W310) = α · (11/1 + 1/1 + 11/1) = 23α

Thus, it can be seen that the crosstalk amounts V502 and V503 of both nets 502 and 503 are less than the crosstalk amount limit value 40α, and that the crosstalk error is suppressed.

Finally, the placement and routing result output means 108
Relay buffer inserting means 105, relay buffer arranging means 1
06, and the result of the placement and routing by the incremental wiring means 107 is reflected (so as to have such a placement and routing result), the placement and routing result information 113 is updated, and the placement and routing result information 113 is output to the outside (step 9
07).

FIG. 10 is a block diagram showing the configuration of a second embodiment (an embodiment corresponding to the second aspect of the present invention) of the crosstalk error suppression system of the present invention.

The crosstalk error suppression system of this embodiment is different from the first embodiment shown in FIG. 1 in that an arrangement error removing means 121 is added.

In the first embodiment, as described above,
When the relay buffer arranging unit 106 arranges the relay buffer, if the relay buffer cannot be arranged at a position on the route of the initial wiring result (another block exists at the target arrangement position (arrangement candidate position) and an arrangement error occurs. If it occurs)
Another arrangement candidate position is searched from the arrangement possible area in the vicinity.

On the other hand, the present embodiment (second embodiment)
Then, the following processes are performed.

The relay buffer allocating means 106 allocates the relay buffer at a position on the route (initial arrangement candidate position) of the initial wiring result while allowing an arrangement error.

After that, the arrangement error removing unit 121
Shifts the placement of a block (gate) in which a placement error has occurred with priority to the placement position of the relay buffer until the placement error disappears, and causes a wiring short-circuit or a placement shortage due to a routing result of a net connected to the shifted gate or a placement shift. Delete the routing result of the net that causes the placement prohibition violation.

Then, the incremental wiring means 1
07 performs rewiring of the deleted net.

FIG. 11 is a block diagram showing the configuration of a third embodiment (an embodiment corresponding to the third embodiment based on the first embodiment) of the crosstalk error suppression system according to the present invention. It is.

The crosstalk error suppression system of this embodiment is different from the first embodiment shown in FIG. 1 in that the relay buffer insertion means 105 is replaced by the relay inverter insertion means 131 (replacement of the relay buffer by two stages of relay inverters). The means for performing the same processing as the buffer inserting means 105. The same applies to the fourth embodiment. The relay buffer arranging means 106 is replaced by the relay inverter arranging means 132 (replacement of the relay buffer by two stages of relay inverters (A means for performing the same processing as the arranging means 106. The same applies to the fourth embodiment.)

In the crosstalk error suppression system of the present embodiment, what is selected for suppression of the crosstalk error and inserted into the net is not a relay buffer but an even number of relay inverters (two units of relay inverters are regarded as one unit). (Two stages of relay inverters are used instead of the relay buffer in all processes).

FIG. 12 is a block diagram showing the configuration of a fourth embodiment (an embodiment corresponding to the third embodiment based on the second embodiment) of the crosstalk error suppression system according to the present invention. It is.

The crosstalk error suppressing system of this embodiment is different from the second embodiment shown in FIG. 10 in that the relay buffer inserting means 105 is replaced by a relay inverter inserting means 131, and the relay buffer arranging means 106 is The difference is that the relay inverter arranging means 132 is used.

In the crosstalk error suppression system of the present embodiment, what is selected for suppression of the crosstalk error and inserted into the net is not a relay buffer but an even number of relay inverters (two units of relay inverters are regarded as one unit). (Two stages of relay inverters are used instead of the relay buffer in all processes).

[0079]

As described above, according to the present invention, the following effects are produced.

A first effect is that a placement and routing result in which a crosstalk error is suppressed (preferably "removed") can be obtained automatically (without requiring any manpower).

The reason why such an effect occurs is that the crosstalk analyzing means detects a net in which a crosstalk error has occurred, and the relay buffer inserting means (or the relay inverter inserting means) is suitable for suppressing the crosstalk error. A suitable relay buffer (or relay inverter) is selected and inserted (logic change), and the relay buffer (or relay inverter) into which the relay buffer arranging means (or relay inverter arranging means) is inserted is arranged on or near the actual wiring route. It is arranged at a position where the crosstalk error can be suppressed and the incremental wiring means inserts the relay buffer (or the relay inverter) and inserts the wiring of the divided net and the insertion of the relay buffer (or the relay inverter). And placement affected (wiring short Cause design rule error) because rewiring of other nets.

The second effect is to suppress as much as possible the deterioration of the wiring capacity and the increase in power consumption due to the addition of a relay buffer (or a relay inverter) inserted to suppress the crosstalk error. It is possible.

The reason why such an effect occurs is that the relay buffer inserting means and the relay buffer arranging means (or the relay inverter inserting means and the relay inverter arranging means) process only as many relay buffers as necessary to suppress the crosstalk error. (Or a relay inverter) only.

The third effect is that the time required for suppressing the crosstalk error is reduced, and there is no possibility that a new crosstalk error will occur.

The reason for this effect is that incremental placement and routing processing is performed on the initial layout result (layout result by the conventional method) (based on the actual placement and routing result, the placement of the relay buffer and the wiring of the accompanying nets). This is because the increase in processing time is small, and highly accurate suppression of crosstalk error can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of a crosstalk error suppression system according to the present invention.

FIG. 2 is a diagram for explaining a specific operation of the crosstalk error suppression system shown in FIG.

FIG. 3 is a diagram for explaining a specific operation of the crosstalk error suppression system shown in FIG.

FIG. 4 is a diagram for explaining a specific operation of the crosstalk error suppression system shown in FIG.

FIG. 5 is a diagram for explaining a specific operation of the crosstalk error suppression system shown in FIG. 1;

FIG. 6 is a diagram for explaining a specific operation of the crosstalk error suppression system shown in FIG.

FIG. 7 is a diagram for explaining a specific operation of the crosstalk error suppression system shown in FIG.

FIG. 8 is a diagram for explaining a specific operation of the crosstalk error suppression system shown in FIG. 1;

FIG. 9 is a flowchart showing processing of the crosstalk error suppression method shown in FIG. 1;

FIG. 10 shows a second example of the crosstalk error suppression system of the present invention.
FIG. 3 is a block diagram showing a configuration of the example.

FIG. 11 shows a third example of the crosstalk error suppression system of the present invention.
FIG. 3 is a block diagram showing a configuration of the example.

FIG. 12 shows a fourth example of the crosstalk error suppression method according to the present invention.
FIG. 3 is a block diagram showing a configuration of the example.

[Explanation of symbols]

 Reference Signs List 101 control means 102 logic / library input means 103 crosstalk amount limit value input means 104 crosstalk analysis means 105 relay buffer insertion means 106 relay buffer placement means 107 incremental wiring means 108 placement / wiring result output means 109 logical connection information 110 physical information 111 Crosstalk analysis library information 112 Crosstalk amount limit value information 113 Placement and wiring result information 121 Placement error removing means 131 Relay inverter insertion means 132 Relay inverter placement means

Claims (3)

(57) [Claims] 1. A layout and wiring result showing a layout and wiring result of a logic circuit laid out without considering a crosstalk error and logical connection information, physical information, and crosstalk analysis library information on a logic circuit to be layout-designed. Logic / library input means for inputting information, crosstalk amount limit value input means for inputting crosstalk amount limit value information indicating the crosstalk amount limit value of each net of the logic circuit, and the logic / library input means A crosstalk amount is calculated for the net indicated by the placement and routing result information input by using the crosstalk analysis library information, and the calculation result and the crosstalk input by the crosstalk amount limit value input means are calculated. Net causing crosstalk error based on the amount limit information A crosstalk analyzing means to be detected, and a type and number of relay buffers suitable for suppressing the crosstalk error are selected with respect to the "net having a crosstalk error" detected by the analysis result by the crosstalk analyzing means. A relay buffer inserting means for inserting the relay buffer into the net; and a relay buffer inserted into the net by the relay buffer inserting means at a position on the route of an initial wiring result of the net and a crosstalk error of the net. A relay buffer arranging means for arranging the relay buffer at a position where suppression is possible, and when the placement error occurs at the target arrangement position, performing the arrangement at a position that can be arranged near a position on the route of the initial wiring result; The wiring of the net divided by the placement of the relay buffer by the placement means and the An incremental wiring means for rewiring the wiring of other nets affected by the insertion and placement of the relay buffer; and an interconnect wiring means reflecting the arrangement and wiring results of the relay buffer inserting means, the relay buffer arranging means and the incremental wiring means. A placement and routing result output means for updating the placement and routing result information input by the logic / library input means and outputting the placement and routing result information to the outside; the logic / library input means, the crosstalk amount limit value input means, A crosstalk error, comprising: a crosstalk analyzing unit, a relay buffer inserting unit, a relay buffer arranging unit, the incremental wiring unit, and a control unit that performs comprehensive control of the arrangement and wiring result output unit. Suppression method. 2. A layout / wiring result showing a layout / wiring result of a logic circuit laid out without considering a crosstalk error and logical connection information, physical information, and crosstalk analysis library information on a logic circuit to be layout-designed. Logic / library input means for inputting information, crosstalk amount limit value input means for inputting crosstalk amount limit value information indicating the crosstalk amount limit value of each net of the logic circuit, and the logic / library input means A crosstalk amount is calculated for the net indicated by the placement and routing result information input by using the crosstalk analysis library information, and the calculation result and the crosstalk input by the crosstalk amount limit value input means are calculated. Net causing crosstalk error based on the amount limit information A crosstalk analyzing means to be detected, and a type and number of relay buffers suitable for suppressing the crosstalk error are selected with respect to the "net having a crosstalk error" detected by the analysis result by the crosstalk analyzing means. A relay buffer inserting means for inserting the relay buffer into the net; and a relay buffer inserted into the net by the relay buffer inserting means at a position on the route of an initial wiring result of the net and a crosstalk error of the net. Relay buffer arranging means for arranging at a position where suppression is possible, and allowing the arrangement error when another block is present at the target arrangement position and causing an arrangement error to overlap and perform the arrangement at the target arrangement position; The relay buffer arranged by the relay buffer arrangement means causes an arrangement error. A placement error removing unit that shifts the block placement so as to remove the overlap related to the placement error; and a net divided by the placement of the relay buffer by the relay buffer placement unit and the placement shift by the placement error removal unit. Incremental wiring means for rewiring the wiring of the second buffer and the wiring of other nets affected by the insertion and placement of the relay buffer; the relay buffer insertion means, the relay buffer placement means, the placement error removing means, and the incremental wiring means. A placement and routing result output means for updating the placement and routing result information input by the logic / library input means by reflecting the placement and routing result by the wiring means, and outputting the placement and routing result information to the outside; Means, said crosstalk quantity system Control means for comprehensively controlling the limit value input means, the crosstalk analysis means, the relay buffer insertion means, the relay buffer placement means, the placement error removal means, the incremental wiring means, and the placement / wiring result output means And a crosstalk error suppressing system. 3. The relay buffer inserting means and the relay buffer locating means which perform the same processing as the relay buffer inserting means and the relay buffer locating means by replacing the relay buffer with two relay inverters. 3. The crosstalk error suppression system according to claim 1, wherein the relay buffer is provided in place of the relay buffer in all processes.