JP2899237B2 - CPU monitoring device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a CPU monitoring device for monitoring runaway such as CPU stoppage or abnormal operation.

[0002]

2. Description of the Related Art When a CPU suddenly stops or abnormally operates, there is a possibility that a device controlled by the CPU is destroyed or data being processed is destroyed.
Therefore, a CPU monitoring device that constantly monitors the operation state of the CPU has been developed. FIG. 3 is a diagram for explaining a conventional CPU monitoring device. In the figure, 1 is a CPU, 4 is a flip-flop, 5 is a monostable multivibrator,
0 indicates the time constant circuit.

Next, the operation of the conventional apparatus will be described with reference to FIG. When the CPU 1 is operating normally, a CPU operation pulse 15 is periodically output by a built-in program, and this pulse is input to the monostable multivibrator 5. The monostable multivibrator 5 is provided with a time constant circuit 50 composed of a resistor R and a capacitor C, and is determined by the resistor R and the capacitor C with a rising edge of the CPU operation pulse 15 as a trigger. During the time constant α (the period of the CPU operation pulse <α), the output signal is maintained at logic L.

Accordingly, when the CPU operation pulse 15 is output periodically, the CP is not activated before the time constant α elapses in a normal state.
Since the U operation pulse 15 is input, the output from the monostable multivibrator 5 maintains the logic L state, and the alarm signal 16 is not output from the flip-flop 4. Here, when some abnormality occurs in the CPU 1 and the CPU operation pulse 15 is not output, when the time constant α elapses, the output of the monostable multivibrator 5 becomes logic H, and this becomes the output trigger of the flip-flop 4. As a result, an alarm signal 16 of +5 V is output from the flip-flop 4, and an alarm (not shown) warns of an abnormality of the CPU 1 based on this signal. FIG. 4 shows the mutual operation timings of the CPU operation pulse 15, the output of the monostable multivibrator 5, and the alarm signal 16 output from the flip-flop 4, as described above.

[0005]

SUMMARY OF THE INVENTION As described above, the conventional C
The PU monitoring circuit is configured as described above. The time constant of the monostable multivibrator uses a time constant circuit composed of a resistor and a capacitor. And the capacitors need to be changed. Further, in order to obtain a long time constant, it is necessary to use an electrolytic capacitor. However, when using an electrolytic capacitor, it is necessary to design in consideration of a capacity loss due to a change with time. Further, there is a problem that it is necessary to incorporate fluctuations in charge and discharge of the capacitor as a margin in advance.

The present invention has been made to solve such a problem, and an object of the present invention is to provide a CPU monitoring apparatus which can easily change a monitoring cycle and can also downsize and simplify its circuit. .

[0007]

According to the present invention, there is provided a CPU monitoring apparatus, comprising: a CPU for counting a clock output from a hardware timer and a counter incorporated in the CPU while the CPU is operating normally; A built-in program that performs an operation that constantly resets this count value when the value reaches a set value and that outputs a signal when the count value exceeds the set value and reaches a timeout reference value It is characterized by.

[0008] Further, there is provided a means for changing the setting of the set value and / or the timeout reference value by changing a program.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. In FIG.
A timer and a counter built in 1 are flip-flops. The CPU 1 has a built-in timer and counter 2 composed of hardware. Since the timer and the counter 2 can be controlled by a program, a program for determining whether the CPU 1 is operating normally based on the count value is provided. Is set in the CPU 1. That is, while the CPU is operating normally, an operation of resetting the counter when the count value reaches a set value,
When the count value exceeds the set value and reaches the timeout reference value, a program for outputting a signal of logic H is set. Needless to say, this program can be easily realized by slightly modifying the conventional program for generating the CPU operation pulse 15.

FIG. 2 is a diagram showing the operation timing of this embodiment. The counter value which is periodically reset exceeds the timeout reference value (this becomes the monitoring period 11) because the reset is delayed or not performed. Timeout 10 is output. The timeout 10 is input as an output trigger of the flip-flop 4, and the flip-flop 4 outputs a + 5v alarm signal 16,
With this signal, an alarm (not shown) alerts the CPU 1 of an abnormality.

Note that a one-chip CPU used for an embedded application generally has a built-in hardware timer and counter having a time-out output function, and the time-out reference value can be controlled by a program. In addition, when the CPU is operating normally under program control, a device that can easily change the monitoring cycle 11 can be configured by adding a means for periodically resetting the counter with a set value (set value <time-out reference value). . Further, the flip-flop 4 can be omitted.

[0012]

As described above, the CPU monitoring device of the present invention is configured by using the hardware timer built in the CPU capable of controlling the program, so that the monitoring cycle can be easily changed by changing the program. The device can be configured. In addition, since a monostable multivibrator using a CR time constant setting circuit is not used unlike the conventional device, no margin is required for the loss of the capacitance of the capacitor or the fluctuation of the time constant, and the circuit configuration is downsized. There are effects such as simplification.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing operation timing of the embodiment.

FIG. 3 is a block diagram showing a configuration example of a conventional apparatus.

FIG. 4 is a diagram showing operation timing of a conventional device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 CPU 2 Hardware timer and counter built in CPU1 4 Flip-flop 10 Timeout output 16 Alarm signal

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G06F 11/30 310

Claims (2)

(57) [Claims] 1. A CPU monitoring device for monitoring a runaway such as a stop or an abnormal operation of a CPU, wherein the CPU is provided with a CPU while the CPU is operating normally.
When the count value output from the hardware timer and counter incorporated in the CPU reaches a set value, the count value is constantly reset, and the count value exceeds the set value and reaches a timeout reference value. And a program for performing a signal output operation. 2. The apparatus according to claim 1, further comprising means for changing the setting value and / or the setting of the timeout reference value by changing the program.
PU monitoring device.