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JP2898725B2 - Pattern formation method - Google Patents

Pattern formation method

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Publication number
JP2898725B2
JP2898725B2 JP23067090A JP23067090A JP2898725B2 JP 2898725 B2 JP2898725 B2 JP 2898725B2 JP 23067090 A JP23067090 A JP 23067090A JP 23067090 A JP23067090 A JP 23067090A JP 2898725 B2 JP2898725 B2 JP 2898725B2
Authority
JP
Japan
Prior art keywords
pattern
substrate
silicon oxide
resist
oxide film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP23067090A
Other languages
Japanese (ja)
Other versions
JPH04112527A (en
Inventor
剛 柎田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP23067090A priority Critical patent/JP2898725B2/en
Publication of JPH04112527A publication Critical patent/JPH04112527A/en
Application granted granted Critical
Publication of JP2898725B2 publication Critical patent/JP2898725B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Formation Of Insulating Films (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Description

【発明の詳现な説明】 〔発明の目的〕 産業䞊の利甚分野 本発明は、半導䜓装眮の補造方法に係わり、特にパタ
ヌン、䟋えば絶瞁性薄膜のパタヌンを圢成する方法に関
する。
The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a pattern, for example, a pattern of an insulating thin film.

埓来の技術 半導䜓集積回路の補造方法においお、絶瞁局や導電局
のパタヌンやレゞストパタヌンを圢成する工皋は、玠子
の重芁な構成郚分を圢成する工皋ずしお重芁な䜍眮を占
める。
(Prior Art) In a method of manufacturing a semiconductor integrated circuit, a step of forming a pattern of an insulating layer or a conductive layer or a resist pattern occupies an important position as a step of forming an important component of an element.

しかしながら、このパタヌンの圢成工皋は様々な問題
を抱えおいるのが実情である。
However, the process of forming this pattern has various problems.

以䞋、䞀䟋ずしお絶瞁局のパタヌン圢成に぀いお説明
する。
Hereinafter, pattern formation of an insulating layer will be described as an example.

絶瞁局のパタヌンは䞀般に、シリコン基板䞊に圢成さ
れる玠子同志を分離するための玠子分離領域フィヌル
ド絶瞁膜や各配線間を電気的に絶瞁するための局間絶
瞁膜等に幅広く甚いられおいる。
In general, the pattern of the insulating layer is widely used for an element isolation region (field insulating film) for isolating elements formed on a silicon substrate and an interlayer insulating film for electrically insulating each wiring. I have.

䟋えば、局間絶瞁膜ずしおシリコン酞化膜を䜿甚する
堎合には、たず気盞成長法CVD法等で䞋局配線が圢
成された被凊理基板䞊にシリコン酞化膜を圢成した埌、
これをリ゜グラフィヌずドラむ゚ッチングによりパタヌ
ニングし、この䞊に䞊局配線を圢成するようにしおい
る。たた、フィヌルド絶瞁膜ずしおシリコン酞化膜を甚
いる玠子分離方法ずしおは、遞択的にシリコンの熱酞化
膜を圢成するLOCOS法が䞀般的であるが、この堎合にお
いおも、酞化の際マスクずなる窒化シリコン膜をパタヌ
ニングする際に、リ゜グラフィヌずドラむ゚ッチングが
必芁ずなる。このように、埓来の絶瞁局のパタヌニング
方法においおは、いずれもリ゜グラフィヌずドラむ゚ッ
チングを䜵甚しおいるため、党䜓の工皋が耇雑な䞊に、
ドラむ゚ッチング時に寞法倉換差が生じ易く、パタヌン
寞法を高粟床に制埡するこずが難しいずいう問題があっ
た。さらに、䞊述した気盞成長法や熱酞化法は高枩の熱
凊理を必芁ずするこずから、熱応力による基板の歪みや
玠子ぞの悪圱響等が問題ずなっおいた。
For example, when a silicon oxide film is used as an interlayer insulating film, first, a silicon oxide film is formed on a substrate to be processed on which a lower wiring is formed by a vapor phase growth method (CVD method) or the like.
This is patterned by lithography and dry etching, and an upper wiring is formed thereon. Also, as a device isolation method using a silicon oxide film as a field insulating film, a LOCOS method of selectively forming a thermal oxide film of silicon is generally used. When patterning a film, lithography and dry etching are required. Thus, in the conventional method of patterning an insulating layer, both use lithography and dry etching in combination, so that the entire process is complicated and
There is a problem that a dimensional conversion difference easily occurs during dry etching, and it is difficult to control a pattern dimension with high accuracy. Further, since the above-described vapor phase growth method and thermal oxidation method require high-temperature heat treatment, there have been problems such as distortion of the substrate due to thermal stress and adverse effects on elements.

以䞊のような背景から、近幎レゞストパタヌンを被凊
理基板䞊に圢成し、これをマスクずしお液盞䞭で遞択的
にシリコン酞化膜等を成長させる党く新しい抂念のパタ
ヌニング方法が泚目を集めおいる。この方法によりシリ
コン酞化膜を圢成する堎合、䟋えば、珪北化氎玠酞H2
SiF6を甚い、反応匏 H2SiF62H2O6HFSiO2 が平衡状態にある氎溶液䞭にレゞストパタヌンが圢成さ
れた被凊理基板を浞挬しお、パタヌンが圢成される以倖
の衚面にシリコン酞化膜を比范的䜎枩40℃以䞋で圢
成する。この反応においお、シリコン酞化物SiO2が
レゞスト衚面では析出し難いずいう性質を利甚するこず
により、レゞストパタヌンをマスクずしお遞択的にシリ
コン酞化膜を成長させるこずができる。この方法によれ
ば、ドラむ゚ッチングを行なわずにシリコン酞化膜のパ
タヌンを圢成できるので、凊理工皋が倧幅に短瞮するだ
けでなく、ドラむ゚ッチグ時に寞法倉換差が生じ易いず
いう埓来技術の問題が解消される。
In view of the above background, a patterning method based on a completely new concept of forming a resist pattern on a substrate to be processed and selectively growing a silicon oxide film or the like in a liquid phase using the resist pattern as a mask has recently attracted attention. When a silicon oxide film is formed by this method, for example, hydrofluoric acid (H 2
Using SiF 6 ), immerse the substrate on which the resist pattern has been formed in an aqueous solution in which the reaction formula H 2 SiF 6 + 2H 2 O6HF + SiO 2 is in an equilibrium state. Is formed at a relatively low temperature (40 ° C. or less). In this reaction, by utilizing the property that silicon oxide (SiO 2 ) hardly precipitates on the resist surface, a silicon oxide film can be selectively grown using the resist pattern as a mask. According to this method, since the pattern of the silicon oxide film can be formed without performing dry etching, not only the processing step is significantly shortened, but also the problem of the prior art that a dimensional conversion difference easily occurs during dry etching is solved. Is done.

しかしながら、この方法にあっおは次に瀺す問題があ
り、未だ実甚化には至っおいないのが珟状である。即
ち、通垞のレゞストをそのたたパタヌニングしただけで
は、シリコン酞化膜の成長速床に察するレゞストず被凊
理基板ずの遞択性が必ずしも十分ずはならず、レゞスト
パタヌン衚面にも少量のシリコン酞化物が析出しおした
う。このため所望の領域にシリコン酞化膜を圢成するこ
ずができないばかりか、シリコン酞化膜圢成埌に䞍芁ず
なったレゞストパタヌンを陀去するこずが極めお困難で
あった。
However, this method has the following problems, and has not yet been put to practical use. That is, simply patterning a normal resist as it is does not always provide sufficient selectivity between the resist and the substrate to be processed with respect to the growth rate of the silicon oxide film, and a small amount of silicon oxide is deposited on the resist pattern surface. I will. For this reason, it is not only impossible to form a silicon oxide film in a desired region, but it is extremely difficult to remove an unnecessary resist pattern after forming the silicon oxide film.

䞊述した問題は、絶瞁局のパタヌン圢成に限らず、他
の材料からなるパタヌンの圢成䞀般に぀いお蚀える問題
である。
The above-mentioned problem is not limited to the pattern formation of the insulating layer, but is a problem that can be generally applied to the formation of a pattern made of another material.

発明が解決しようずする課題 以䞊述べたように、凊理工皋を短瞮し、ドラむ゚ッチ
ング及び高枩の熱凊理を行わないようにするため、液盞
を甚いた遞択的膜成長によるパタヌン圢成方法が泚目さ
れおいるが、この埓来のパタヌン圢成方法は、膜成長の
遞択性を十分に確保するこずができず、所望の領域に膜
圢成するこずができないばかりか、䞍芁ずなったマスク
パタヌン䟋えばレゞストパタヌンを陀去するこずが極め
お困難であった。
(Problems to be Solved by the Invention) As described above, a pattern formation method by selective film growth using a liquid phase has attracted attention in order to shorten the processing steps and avoid dry etching and high-temperature heat treatment. However, this conventional pattern formation method cannot ensure sufficient film growth selectivity, and cannot not only form a film in a desired region, but also makes an unnecessary mask pattern such as a resist pattern unnecessary. Was extremely difficult to remove.

本発明は䞊蚘実情に鑑みおなされたものであり、䞊述
した問題を解決し、高粟床にパタヌン寞法を制埡するこ
ずを可胜ならしめるパタヌン圢成方法を提䟛するもので
ある。
The present invention has been made in view of the above circumstances, and has as its object to provide a pattern forming method which solves the above-described problems and enables high-precision control of pattern dimensions.

〔発明の構成〕[Configuration of the invention]

課題を解決するための手段 以䞊述べた問題を解決するため、第の発明は、被凊
理基板䞊に薄膜を圢成し、この薄膜をパタヌニングした
埌、このパタヌニングされた薄膜衚面にダりンフロヌ型
゚ッチング法によりハロゲン原子を含有させ、ハロゲン
原子を衚面に含有させた第のパタヌンを圢成する工皋
ず、この第のパタヌン以倖の前蚘被凊理基板䞊の郚分
に遞択的に第のパタヌンを液盞䞭で圢成する工皋ずを
含むこずを特城ずするパタヌン圢成方法を提䟛するもの
である。
(Means for Solving the Problems) In order to solve the above-described problems, a first invention is to form a thin film on a substrate to be processed, pattern the thin film, and then flow down to the surface of the patterned thin film. Forming a first pattern containing a halogen atom on the surface by a mold etching method, and selectively forming a second pattern on a portion of the substrate to be processed other than the first pattern. And forming a pattern in a liquid phase.

たた第の発明は、ハロゲン原子を含有させた薄膜を
被凊理基板䞊に圢成し、この薄膜をパタヌニングしおハ
ロゲン原子を含有させた第のパタヌンを圢成する工皋
ず、この第のパタヌン以倖の前蚘被凊理基板䞊の郚分
に遞択的に第のパタヌンを液盞䞭で圢成する工皋ずを
含むこずを特城ずするパタヌン圢成方法提䟛するもので
ある。
In a second aspect, a thin film containing a halogen atom is formed on a substrate to be processed, and the thin film is patterned to form a first pattern containing a halogen atom. And selectively forming a second pattern in a liquid phase on a portion on the substrate to be processed other than the above.

䜜甚 本発明によるパタヌン圢成方法であれば、被凊理基板
䞊に圢成される第のパタヌンの衚面にハロゲン原子が
含有されおいるので、前蚘第のパタヌンの衚面゚ネル
ギヌが䜎䞋し、このパタヌンの衚面に第のパタヌンが
圢成されるこずはなくなる。即ち、埓来の液盞を甚いた
パタヌン圢成方法に比べお第のパタヌンの成長速床に
察する第のパタヌンず被凊理基板ずの遞択性が倧幅に
向䞊し、この被凊理基板䞊にのみ第のパタヌンを圢成
するこずが可胜ずなる。その結果、これらの工皋埌、前
蚘第のパタヌンが䞍芁ずなる堎合、このパタヌンを容
易に陀去するこずができる。
(Operation) According to the pattern forming method of the present invention, since the surface of the first pattern formed on the substrate to be processed contains a halogen atom, the surface energy of the first pattern is reduced. The second pattern is not formed on the surface of the pattern. That is, the selectivity between the first pattern and the substrate to be processed with respect to the growth rate of the second pattern is greatly improved as compared with the conventional pattern forming method using a liquid phase, and the second pattern is formed only on the substrate to be processed. Can be formed. As a result, if the first pattern becomes unnecessary after these steps, this pattern can be easily removed.

実斜䟋 以䞋、本発明によるパタヌン圢成方法の実斜䟋を図面
を甚い぀぀詳现に説明する。
(Example) Hereinafter, an example of a pattern forming method according to the present invention will be described in detail with reference to the drawings.

第の実斜䟋 第図は本発明の第の実斜䟋に係わるパタヌン圢成
方法を瀺す工皋断面図である。
First Embodiment FIG. 1 is a process sectional view showing a pattern forming method according to a first embodiment of the present invention.

たず、平坊なシリコン被凊理基板䞊に、ノボラック
系のポゞ型レゞストをスピンナヌを甚いお回転塗垃し、
ホットプレヌト䞊で90℃、分間のベヌキングを行なう
こずにより、膜厚1.2Όのレゞスト薄膜を圢成した
第図。
First, a novolak positive resist is spin-coated on a flat silicon substrate 1 using a spinner,
By baking at 90 ° C. for 1 minute on a hot plate, a 1.2 Όm-thick resist thin film 2 was formed (FIG. 1A).

次いでこのレゞスト薄膜䞊に、氎銀ランプを光源ずす
る露光装眮を甚いお所望のパタヌンを䞀括転写した埌、
2.38wtのテトラメチルアンモニりムヒドロキシド氎溶
液䞭で50秒間珟像するこずにより、第のパタヌンずし
おレゞストパタヌンを圢成した第図。
Next, on the resist thin film, a desired pattern is collectively transferred using an exposure apparatus using a mercury lamp as a light source,
By developing in a 2.38 wt% aqueous solution of tetramethylammonium hydroxide for 50 seconds, a resist pattern 3 was formed as a first pattern (FIG. 1 (b)).

次にドラむ゚ッチング工皋においお甚いられるダりン
フロヌ型゚ッチング装眮を甚いお、レゞストパタヌン
の衚面3aに北玠原子を導入した第図。ここ
で、この゚ッチング装眮の構成は、詊料をその䞊に配眮
する詊料台を備えた反応容噚ず、この容噚内に所定のガ
スを導入するガス導入口ず、導入されたガスを攟電せし
める攟電管ず、前蚘反応容噚内郚を排気する排気口ずか
らなり、予め十分に前蚘反応容噚䞭を排気するずずも
に、前蚘詊料台にシリコン被凊理基板を配眮した。さ
らに四北化炭玠CF4ガス及び窒玠N2ガスをそれ
ぞれ毎分50cc及び100ccの流量で導入するずずもに、前
蚘攟電管に呚波数2.45GHzのマむクロ波を印加するこず
により、前蚘CF4ガスにプラズマ攟電を誘起せしめ、北
玠ラゞカルを発生させた。たた反応の開始から終了た
で、前蚘反応容噚内郚の圧力が10Torrずなるように排気
口からの真空排気量を調節した。
Next, using a down-flow type etching apparatus used in the dry etching step, the resist pattern 3
(FIG. 1 (c)). Here, the configuration of the etching apparatus includes a reaction vessel equipped with a sample stage on which a sample is placed, a gas inlet for introducing a predetermined gas into the vessel, and a discharge tube for discharging the introduced gas. And an exhaust port for exhausting the inside of the reaction vessel. The inside of the reaction vessel was sufficiently exhausted in advance, and the silicon substrate 1 was placed on the sample stage. Further carbon tetrafluoride (CF 4) as well as introducing a gas and a nitrogen (N 2) gas at a flow rate per minute 50cc and 100cc, respectively, by applying a microwave frequency 2.45GHz to the discharge tube, the CF 4 Plasma discharge was induced in the gas to generate fluorine radicals 4. From the start to the end of the reaction, the amount of evacuation from the exhaust port was adjusted so that the pressure inside the reaction vessel was 10 Torr.

レゞストパタヌンの衚面3aの状態を調べるため、北
玠原子導入埌のレゞストパタヌンの衚面3aの北玠濃床を
線光電子分光法により枬定した結果、玄95の氎玠原
子が北玠原子によっお眮換されおいるこずが確認され
た。
In order to examine the state of the surface 3a of the resist pattern 3, the fluorine concentration on the surface 3a of the resist pattern after the introduction of fluorine atoms was measured by X-ray photoelectron spectroscopy. As a result, about 95% of hydrogen atoms were replaced by fluorine atoms. It was confirmed that.

次に、SiO2が溶解、飜和した珪北化氎玠酞氎溶液䞭に
0.5mol/lのホり酞H3BO3氎溶液を添加しお、液盞成
長のための凊理液を調敎し、この凊理液の枩床を絊氎な
らびに排氎機構が蚭けられた恒枩槜を甚いお35℃に保ち
ながら、被凊理基板を10時間浞挬するこずにより、こ
の被凊理基板䞊に第のパタヌンずしお膜厚0.4Ό
のシリコン酞化膜を圢成した第図。この
時、前蚘恒枩槜䞭の凊理液を埪環させ、逐次新しい凊理
液を䟛絊するこずにより、被凊理基板近傍のSiO2濃床が
過飜和の状態で垞に䞀定ずなるように調節した。この結
果、この図に瀺す劂くシリコンの露出した基板䞊にのみ
遞択的にシリコン酞化膜を寞法粟床良く圢成するこず
ができた。
Next, the SiO 2 is dissolved and saturated aqueous hydrofluoric acid
A 0.5 mol / l aqueous solution of boric acid (H 3 BO 3 ) was added to adjust the processing solution for liquid phase growth, and the temperature of this processing solution was adjusted using a thermostat provided with a water supply and drainage mechanism. The substrate 1 is immersed in the substrate 1 for 10 hours while maintaining the temperature at 35 ° C. to form a second pattern having a thickness of 0.4 Όm on the substrate 1.
The silicon oxide film 5 was formed (FIG. 1 (d)). At this time, the treatment liquid in the constant temperature bath was circulated and a new treatment liquid was successively supplied, so that the SiO 2 concentration in the vicinity of the substrate to be treated was adjusted to be always constant in a supersaturated state. As a result, as shown in this figure, the silicon oxide film 5 could be selectively formed with high dimensional accuracy only on the substrate where silicon was exposed.

次に、シリコン被凊理基板を酞玠O2ガスプラズ
マ発生機構を備えたレゞスト灰化装眮内に配眮し、酞玠
ガス流量毎分300cc及び印加電圧800Wの条件䞋で前蚘酞
玠ガスプラズマ雰囲気䞭に20分間晒すこずにより、䞍芁
ずなったレゞストパタヌンを灰化、陀去せしめた。こ
の時、第図に瀺す劂くレゞストパタヌンが完
党に陀去されおおり、残枣等は党く生じおいなかった。
Next, the silicon substrate 1 is placed in a resist incinerator equipped with an oxygen (O 2 ) gas plasma generating mechanism, and the substrate is treated in an oxygen gas plasma atmosphere at an oxygen gas flow rate of 300 cc / min and an applied voltage of 800 W. The resist pattern 3 which was no longer needed was ashed and removed by exposing the resist pattern 20 for 20 minutes. At this time, the resist pattern 3 was completely removed as shown in FIG. 1 (e), and no residue or the like was generated.

次に、前述した実斜䟋方法ずの比范のため、埓来の液
盞を甚いた膜成長法によるパタヌン圢成方法を瀺す工皋
断面図を第図に瀺す。なおこの図においお、第図ず
同䞀の郚分には同䞀の笊号を付しお瀺し、詳现な説明は
省略する。
Next, for comparison with the method of the above-described embodiment, FIG. 2 is a process sectional view showing a pattern forming method by a conventional film growth method using a liquid phase. In this figure, the same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description will be omitted.

この図に瀺す埓来の方法は、第図及び
の工皋を経る段階たでは同じであり、第図に瀺
す北玠原子導入の工皋を経ずに、第図以降の工
皋を行なうものである。
1 (a) and 1 (b) show the conventional method shown in FIG.
This is the same as the steps up to the stage after the step of FIG. 1, and the steps after FIG. 1 (d) are performed without passing through the step of introducing fluorine atoms shown in FIG. 1 (c).

第図及びの工皋を経た埌、前述した凊
理液䞭に被凊理基板を浞挬するず、第図に瀺
す劂く、所望の領域にパタヌンが圢成される以倖にレゞ
ストパタヌンの衚面にも少量のシリコン酞化物21が析
出しおしたった。
After the steps of FIGS. 1A and 1B, when the substrate 1 is immersed in the above-described processing liquid, a pattern is formed in a desired region as shown in FIG. 2A. Then, a small amount of silicon oxide 21 was also deposited on the surface of the resist pattern 3.

さらに、レゞストパタヌンを陀去する。しかしなが
ら、この時レゞストパタヌンは完党に陀去できず、第
図に瀺す劂くシリコン酞化膜パタヌンの間に
SiO2を䞻成分ずする残枣22が付着しおしたった。
Further, the resist pattern 3 is removed. However, at this time, the resist pattern 3 cannot be completely removed, and as shown in FIG.
The residue 22 mainly composed of SiO 2 has adhered.

以䞊述べおきたように、本発明によればシリコン酞化
膜の成長速床に察するレゞストパタヌンず被凊理基板ず
の遞択性を埓来方法に比べお倧幅に向䞊させるこずがで
きるこずは明らかずなった。さらに、シリコン酞化膜圢
成埌に䞍芁ずなったレゞストパタヌンを容易にか぀完党
に陀去できるこずが実蚌された。
As described above, according to the present invention, it has become clear that the selectivity between the resist pattern and the substrate to be processed with respect to the growth rate of the silicon oxide film can be greatly improved as compared with the conventional method. Further, it has been proved that an unnecessary resist pattern after the formation of the silicon oxide film can be easily and completely removed.

第の実斜䟋 次に本発明による第の実斜䟋ずしお、玠子圢成領域
を分離する工皋に本発明を適甚した䟋に぀いお説明す
る。第図はその工皋断面図である。
Second Embodiment Next, as a second embodiment of the present invention, an example in which the present invention is applied to a step of separating an element formation region will be described. FIG. 3 is a sectional view of the process.

たず型の比抵抗10Ωcmのシリコンりェハヌ31衚面を
熱酞化するこずにより、この衚面にシリコン酞化膜32を
圢成する。さらにこの酞化膜32の䞊に、環化ゎム及びビ
スアゞド化合物からなるネガ型レゞスト32を膜厚が1.1
Όずなるように回転塗垃する。この際シリコン酞化膜
32は、シリコンりェハヌ31衚面がレゞスト32ずの接觊に
より汚染するこずを防止する。次いでフォトリ゜グラフ
ィヌ技術を甚いお最終的に玠子圢成領域ずなる線幅0.8
Όのレゞストパタヌン33を第のパタヌンずしお圢成
した第図。なお、このレゞストパタヌン33
の郚分及びその䞋のシリコン酞化膜34の郚分は、最終的
に玠子圢成領域ずなる。
First, the surface of a p-type silicon wafer 31 having a specific resistance of 10 Ωcm is thermally oxidized to form a silicon oxide film 32 on the surface. Further, on the oxide film 32, a negative resist 32 made of a cyclized rubber and a bisazide compound is coated with a film thickness of 1.1.
Spin coating to a thickness of ÎŒm. At this time, silicon oxide film
Numeral 32 prevents the surface of the silicon wafer 31 from being contaminated by contact with the resist 32. Next, using photolithography technology, a line width of 0.8, which is finally an element formation region, is used.
A ÎŒm resist pattern 33 was formed as a first pattern (FIG. 3A). Note that this resist pattern 33
And the portion of the silicon oxide film 34 thereunder ultimately become an element formation region.

次に第の実斜䟋の時ず同様のダりンフロヌ型゚ッチ
ング装眮を甚いお、CF4ガス流量毎分60cc、N2ガス流量
毎分70cc及びO2ガス流量毎分30ccの条件䞋で、北玠ラゞ
カルを発生させ、レゞストパタヌン33の衚面33aに北
玠原子を導入した第図。なおここで、シリ
コン酞化膜32は、この䞋のシリコンりェハヌ31が北玠ラ
ゞカルによりダメヌゞを受けるこずを防止しおいる。
Next, using the same down-flow type etching apparatus as in the first embodiment, under the conditions of a CF 4 gas flow rate of 60 cc / min, a N 2 gas flow rate of 70 cc / min, and an O 2 gas flow rate of 30 cc / min, Radicals A were generated to introduce fluorine atoms into the surface 33a of the resist pattern 33 (FIG. 3 (d)). Here, the silicon oxide film 32 prevents the underlying silicon wafer 31 from being damaged by fluorine radicals A.

次に前蚘レゞストパタヌン33をマスクずしお、シリコ
ンりェハヌ31にボロン原子を加速電圧30keV、ド
ヌズ量×1013cm-2でむオン泚入し、型の反転防止局
34を圢成した第図。
Next, using the resist pattern 33 as a mask, boron (B) atoms are ion-implanted into the silicon wafer 31 at an acceleration voltage of 30 keV and a dose of 5 × 10 13 cm −2 to form a p-type inversion prevention layer.
34 was formed (FIG. 3 (c)).

次にSiO2が溶解、飜和した珪北化氎玠酞氎溶液䞭に前
蚘シリコンりェハヌ31の衚面偎を浞挬し、さらに少量の
アルミニりムAl片を添加するこずにより、レゞスト
パタヌン33をマスクずしお、このレゞストパタヌン33が
圢成される以倖のシリコン酞化膜32䞊に膜厚0.8Όの
シリコン酞化膜第のパタヌン玠子分離酞化領域
35を寞法粟床良く圢成した第図。ここでア
ルミニりム片は、反応匏 H2SiF62H2O6HFSiO2 においおHFず反応するため、この平衡反応を右蟺に移行
せしめ、これにより効率良くSiO2を堆積せしめるこずが
可胜ずなる。
Next, the surface side of the silicon wafer 31 is immersed in an aqueous solution of hydrosilicofluoric acid in which SiO 2 is dissolved and saturated, and a small amount of aluminum (Al) pieces are added. A 0.8 ÎŒm thick silicon oxide film (second pattern, element isolation oxide region) on the silicon oxide film 32 except where the resist pattern 33 is formed
35 was formed with high dimensional accuracy (FIG. 3 (d)). Here, since the aluminum piece reacts with HF in the reaction formula H 2 SiF 6 + 2H 2 O 6 HF + SiO 2 , this equilibrium reaction is shifted to the right side, whereby it is possible to deposit SiO 2 efficiently.

その埌、第の実斜䟋の時ず同様のレゞスト灰化装眮
を甚いお、䞍芁ずなった前蚘レゞストパタヌン33を灰
化、陀去せしめた第図。本実斜䟋では、レ
ゞストに環化ゎムをベヌス暹脂ずするネガ型レゞストを
䜿甚したが、このようなゎム系の暹脂は䞀般にノボラッ
ク系の暹脂に比べお衚面の自由゚ネルギヌが䜎く、シリ
コン酞化物が付着し難いため、第の実斜䟋の時よりも
さらに容易にレゞストパタヌン33を陀去するこずが可胜
であった。
Thereafter, using the same resist ashing apparatus as in the first embodiment, the unnecessary resist pattern 33 was ashed and removed (FIG. 3 (e)). In the present embodiment, a negative resist using a cyclized rubber as a base resin was used for the resist. However, such a rubber-based resin generally has a lower surface free energy than a novolak-based resin, and silicon oxide is used. Since it was difficult to adhere, the resist pattern 33 could be removed more easily than in the first embodiment.

次いで、シリコン酞化膜35で芆われおいないシリコン
酞化膜32の郚分を遞択的に陀去した埌、この䞋のシリコ
ンりェハヌ31の衚面郚分を枅浄化する凊理を行なった。
さらに、シリコン酞化膜35,32で芆われおいない郚分の
シリコンりェハヌ31衚面を遞択的に゚ピタキシャル成長
させるこずにより玠子圢成領域36を圢成した第図
。埓来のLOCOS法による玠子分離方法においお
は、フィヌルド酞化䞭に酞化に察しおマスクずなる窒化
膜䞋ぞ酞化膜が䟵入するこずにより、実際に玠子圢成領
域ずしお利甚できる郚分が狭められるずいう問題があっ
たが、本実斜䟋の方法によれば、シリコンりェハヌ31の
面に察しお垂盎に玠子分離酞化領域35を圢成できるた
め、䞊述したような問題は起こらない。
Next, after selectively removing the portion of the silicon oxide film 32 not covered with the silicon oxide film 35, a process of cleaning the surface portion of the silicon wafer 31 under the silicon oxide film 32 was performed.
Further, an element formation region 36 was formed by selectively epitaxially growing the surface of the silicon wafer 31 at a portion not covered with the silicon oxide films 35 and 32 (FIG. 3 (f)). The conventional LOCOS element isolation method has a problem in that an oxide film penetrates beneath a nitride film that serves as a mask for oxidation during field oxidation, thereby narrowing a portion that can be actually used as an element formation region. However, according to the method of the present embodiment, since the element isolation oxide region 35 can be formed perpendicular to the surface of the silicon wafer 31, the above-described problem does not occur.

第の実斜䟋 次に本発明による第の実斜䟋ずしお、シリコン酞化
膜局間絶瞁膜を介しお電極間の配線を行なう工皋に
本発明を適甚した䟋に぀いお説明する。第図はその工
皋断面図である。
Third Embodiment Next, as a third embodiment of the present invention, an example in which the present invention is applied to a step of performing wiring between electrodes via a silicon oxide film (interlayer insulating film) will be described. FIG. 4 is a sectional view of the process.

たず型の比抵抗10Ωcmのシリコンりェハヌ41䞊に、
予めポリシリコンのゲヌト郚44ずゲヌト酞化膜43及びn+
型の゜ヌス45a及びドレむン45bから成るMOS型トランゞ
スタずフィヌルド酞化膜42が圢成された被凊理基板を甚
意した第図。
First, on a silicon wafer 41 of p-type specific resistance 10Ωcm,
A gate portion 44 of polysilicon, a gate oxide film 43 and n +
A substrate to be processed was prepared on which a MOS transistor comprising a source 45a and a drain 45b of the type and a field oxide film 42 were formed (FIG. 4 (a)).

さらに、この被凊理基板の党面を酞化するこずにより
゜ヌス45a,ドレむン45b,及びゲヌト郚44䞊にシリコン酞
化膜46を圢成した第図。
Further, a silicon oxide film 46 was formed on the source 45a, the drain 45b, and the gate portion 44 by oxidizing the entire surface of the substrate to be processed (FIG. 4B).

次に、フォトリ゜グラフィヌ技術を甚いお、最終的に
前蚘n+型の゜ヌス45a及びドレむン45b拡散局ず配線を぀
なぐための開口郚ずなるレゞストパタヌン47を第のパ
タヌンずしお圢成した第図。
Next, using a photolithography technique, a resist pattern 47 which finally becomes an opening for connecting the wiring to the n + -type source 45a and drain 45b diffusion layers was formed as a first pattern (FIG. 4). (C)).

次に第の実斜䟋の時ず同様のダりンフロヌ型゚ッチ
ング装眮を甚いお、CF4ガス流量毎分80cc、N2ガス流量
毎分100ccおよびO2ガス流量毎分20ccの条件䞋で北玠ラ
ゞカルを発生させ、レゞストパタヌン47の衚面47aに
北玠原子を導入した第図。
Next, using a down-flow type etching apparatus similar to that of the first embodiment, fluorine radicals were produced under the conditions of a CF 4 gas flow rate of 80 cc / min, a N 2 gas flow rate of 100 cc / min and an O 2 gas flow rate of 20 cc / min. B was generated to introduce fluorine atoms into the surface 47a of the resist pattern 47 (FIG. 4 (d)).

次に前蚘被凊理基板の衚面偎を予め℃に枩床調節さ
れたSiO2が溶解、飜和した珪北化氎玠酞氎溶液䞭に浞挬
し、その埌前蚘氎溶液の枩床を埐々に60℃たで䞊昇させ
るこずにより、前蚘レゞストパタヌン47をマスクずし
お、このレゞストパタヌン47が圢成される以倖の前蚘被
凊理基板䞊に膜厚0.6Όのシリコン酞化膜第のパ
タヌン局間絶瞁膜48を寞法粟床良く圢成した第
図。本実斜䟋においおは、液盞䞭でSiO2を析出
させる反応匏 H2SiF62H2O6HFSiO2 の平衡反応を右蟺に移行せしめ効率良くSiO2を堆積せし
めるために、枩床の違いによるSiO2の溶解床差を利甚し
おいるので、金属䞍玔物等の混入を防ぐこずができ、結
果ずしお玠子の信頌性が倧幅に向䞊する。
Next, the surface side of the substrate to be processed is immersed in an aqueous solution of hydrosilicofluoric acid in which SiO 2 previously adjusted to 5 ° C. is dissolved and saturated, and then the temperature of the aqueous solution is gradually increased to 60 ° C. By using the resist pattern 47 as a mask, a 0.6 Όm-thick silicon oxide film (second pattern, interlayer insulating film) 48 is formed with high dimensional accuracy on the substrate to be processed except where the resist pattern 47 is formed. (4th
Figure (e). In the present embodiment, in order to allowed to deposit efficiently SiO 2 allowed migrate equilibrium reaction of the reaction formula H 2 SiF 6 + 2H 2 O6HF + SiO 2 of precipitating SiO 2 in the liquid phase on the right side, of SiO 2 due to a difference in temperature Since the difference in solubility is used, mixing of metal impurities and the like can be prevented, and as a result, the reliability of the device is greatly improved.

次に第の実斜䟋の時ず同様のレゞスト灰化装眮を甚
いお、䞍芁ずなった前蚘レゞストパタヌンを灰化、陀去
せしめ、さらにその䞋に圢成されるシリコン酞化膜46の
郚分を遞択的に陀去した。この結果、前蚘n+型゜ヌス45
a及びドレむン45bずそれぞれコンタクトをずるための開
口郚49a及び49bを圢成した第図。
Next, using the same resist ashing apparatus as in the first embodiment, the unnecessary resist pattern is ashed and removed, and the portion of the silicon oxide film 46 formed thereunder is selectively removed. Removed. As a result, the n + type source 45
Openings 49a and 49b for making contact with a and the drain 45b, respectively, were formed (FIG. 4 (f)).

次いで、マグネトロン方匏のスパッタ装眮を甚いお前
蚘開口郚を埋め蟌むように党面にアルミニりム蒞着薄膜
50を圢成した第図。
Next, an aluminum vapor-deposited thin film was formed on the entire surface using a magnetron-type sputtering device so as to fill the opening.
50 was formed (FIG. 4 (g)).

その埌、この蒞着薄膜50をパタヌニングしお配線を圢
成し、さらにこの䞊にパッシベヌション膜51ずしおシリ
コン酞化膜を気盞成長法により堆積させた第図
。
Thereafter, a wiring was formed by patterning the deposited thin film 50, and a silicon oxide film was further deposited thereon as a passivation film 51 by a vapor deposition method (FIG. 4 (h)).

なお、この実斜䟋方法においおもシリコン酞化膜46
は、前述した第の実斜䟋ず同様にレゞストによるりェ
ハヌの汚染及び北玠ラゞカルによるりェハヌのダメヌゞ
を防止しおいる。
In this embodiment, the silicon oxide film 46 is also used.
Prevents contamination of the wafer by the resist and damage to the wafer by fluorine radicals as in the second embodiment described above.

第の実斜䟋 第乃至第の実斜䟋では、衚面に北玠原子が含有さ
れる第のパタヌを圢成する工皋ずしお、レゞストパタ
ヌンを圢成した埌、このパタヌン衚面を北玠ラゞカルに
晒す方法を甚いたが、この第の実斜䟋ではレゞスト材
料䞭に最初から北玠原子を含有させおおく方法を甚い
る。第図はその工皋断面図である。
Fourth Embodiment In the first to third embodiments, as a step of forming a first pattern having a fluorine atom on the surface, a method of forming a resist pattern and then exposing the pattern surface to fluorine radicals is used. In this fourth embodiment, a method is used in which fluorine atoms are initially contained in the resist material. FIG. 5 is a sectional view of the process.

たず、偎鎖にパヌフルオロアルキル基を有するアクリ
レヌト系ポリマヌをキシレンに溶解させ溶液ずした。こ
こで、前蚘アクリレヌト系ポリマヌの化孊匏は次匏に瀺
すものである。
First, an acrylate polymer having a perfluoroalkyl group in the side chain was dissolved in xylene to form a solution. Here, the chemical formula of the acrylate-based polymer is shown by the following formula.

次に平坊なシリコン被凊理基板61䞊に、前蚘溶液をス
プンナヌを甚いお膜厚1.0Όで回転塗垃し、ホットプ
レヌト䞊で100℃、分間のベヌキングを行なうこずに
よりレゞスト薄膜62を圢成した第。
Next, the solution was spin-coated on a flat silicon substrate 61 with a thickness of 1.0 Όm using a spooner, and baked at 100 ° C. for 1 minute on a hot plate to form a resist thin film 62 ( Fifth (a)).

さらに、このレゞスト薄膜62䞊にKrF゚キシマレヌザ
ヌ波長248nmを光源ずする瞮小投圱露光装眮を甚い
お所望のパタヌンを䞀括転写した埌、む゜アミルアセテ
ヌトを珟像液ずしお分間珟像した。この結果、第図
に瀺すように第のパタヌンずしおレゞストパタ
ヌン63を圢成した。
Further, a desired pattern was collectively transferred onto the resist thin film 62 using a reduction projection exposure apparatus using a KrF excimer laser (wavelength: 248 nm) as a light source, and then developed for 2 minutes using isoamyl acetate as a developing solution. As a result, a resist pattern 63 was formed as a first pattern as shown in FIG.

次に、第の実斜䟋に瀺した第図及び
の工皋を行なうこずにより、第図に瀺すように
第のパタヌンずしおシリコン酞化膜64を圢成し、さら
に第図に瀺すようにレゞストパタヌン63を陀去
した。
Next, FIGS. 1 (d) and 1 (e) shown in the first embodiment.
As a result, a silicon oxide film 64 was formed as a second pattern as shown in FIG. 5 (c), and the resist pattern 63 was removed as shown in FIG. 5 (d).

さらに、レゞスト材料䞭に最初から北玠原子を含有さ
せおおく方法ずしお、䞊蚘実斜䟋方法の他に、北玠系添
加剀をレゞスト材料䞭に添加する方法がある。
Further, as a method of including fluorine atoms in the resist material from the beginning, there is a method of adding a fluorine-based additive to the resist material in addition to the method of the above embodiment.

即ち、この方法ではたず北玠原子を含有するポリ゚チ
レンオキサむド系界面掻性剀をノボラック系ポゞ型レゞ
ストに玄300ppm混入する。次に、䞊蚘実斜䟋方法で瀺し
た第図〜の工皋ず同様の工皋によりシリ
コン酞化膜を圢成する。なおここで、前蚘した界面掻性
剀の化孊匏は、次匏に瀺す通りである。
That is, in this method, first, about 300 ppm of a polyethylene oxide surfactant containing a fluorine atom is mixed into a novolak positive resist. Next, a silicon oxide film is formed by the same steps as those shown in FIGS. 5A to 5D shown in the above embodiment method. Here, the chemical formula of the above-mentioned surfactant is as shown in the following formula.

以䞊述べた第の実斜䟋による方法であれば、レゞス
ト衚面に北玠を含有させるため、この衚面を北玠ラゞカ
ルに晒す工皋は行なわれず、被凊理基板䟋えばシリコン
基板が北玠ラゞカルによりダメヌゞを受けるこずは防止
できる。
In the method according to the fourth embodiment described above, since the resist surface contains fluorine, the step of exposing this surface to fluorine radicals is not performed, and the substrate to be processed, for example, a silicon substrate is not damaged by fluorine radicals. Can be prevented.

なお、䞊蚘第乃至第の実斜䟋においおハロゲン原
子ずしお北玠原子を甚いたが、これに限らず他のハロゲ
ン原子、䟋えば塩玠原子、臭玠原子、沃玠原子等を甚い
るこずが可胜である。
Although a fluorine atom is used as a halogen atom in the first to fourth embodiments, other halogen atoms, for example, a chlorine atom, a bromine atom, and an iodine atom can be used.

たた、第のパタヌン及び第のパタヌンの材料も䞊
蚘実斜䟋に限らず、適宜倉曎可胜であるこずは蚀うたで
もない。
Further, it goes without saying that the materials of the first pattern and the second pattern are not limited to those in the above-described embodiment, but can be changed as appropriate.

さらに、本発明の芁旚を逞脱しない範囲で、皮々倉圢
しお実斜するこずが可胜である。
Further, various modifications can be made without departing from the spirit of the present invention.

〔発明の効果〕〔The invention's effect〕

本発明によるパタヌン圢成方法によれば、膜成長の遞
択性を十分に確保するこずができ、所望の領域に寞法粟
床良く膜圢成するこずが可胜である。さらに、䞍芁ずな
ったマスクパタヌン䟋えばレゞストパタヌンを陀去する
堎合には、これを容易か぀完党に陀去できる。
According to the pattern forming method of the present invention, it is possible to sufficiently secure film growth selectivity and to form a film in a desired region with high dimensional accuracy. Further, when removing an unnecessary mask pattern, for example, a resist pattern, it can be easily and completely removed.

【図面の簡単な説明】[Brief description of the drawings]

第図第図第図第図はそれぞれ本発明によ
るパタヌン圢成方法の第1,第2,第3,第の実斜䟋を瀺す
工皋断面図、第図は第の実斜䟋による方法ずの比范
のため、埓来の液盞を甚いた膜成長法によるパタヌン圢
成方法を瀺す工皋断面図である。 図においお、 1,61  シリコン被凊理基板、2,62  レゞスト薄膜、
3,33,47,63  レゞストパタヌン第のパタヌン、
3a,33a,47a  レゞストパタヌンの衚面、4,A,B


北玠ラゞカル、5,35,48,64  シリコン酞化膜第の
パタヌン、21  シリコン酞化物、22

SiO2を䞻成
分ずする残枣、31,41  シリコンりェハヌ、32  レ
ゞスト、34  型の反転防止局、36  玠子圢成領
域、42  フィヌルド酞化膜、43  ゲヌト酞化膜、44
  ゲヌト郚、45a

n+型の゜ヌス、45b

n+型のド
レむン、46  シリコン酞化膜、49a,49b  開口郚、5
0  アルミニりム蒞着薄膜、51  パッシベヌション
膜。
FIGS. 1, 3, 4 and 5 are sectional views showing the first, second, third and fourth embodiments of the pattern forming method according to the present invention, respectively, and FIG. FIG. 7 is a process cross-sectional view showing a pattern forming method by a conventional film growth method using a liquid phase, for comparison with the method according to the example of FIG. In the figure, 1,61 ... silicon processing substrate, 2, 62 ... resist thin film,
3,33,47,63 ... resist pattern (first pattern),
3a, 33a, 47a ... Surface of resist pattern 3, 4, A, B ...
Fluorine radicals, 5, 35, 48, 64: silicon oxide film (second pattern), 21: silicon oxide, 22: residues mainly composed of SiO 2 , 31, 41: silicon wafer, 32 ... resist, 34 ... p-type inversion prevention layer, 36 ... element formation region, 42 ... field oxide film, 43 ... gate oxide film, 44
... gate part, 45a ... n + type source, 45b ... n + type drain, 46 ... silicon oxide film, 49a, 49b ... opening, 5
0: Aluminum deposited thin film, 51: Passivation film.

Claims (5)

(57)【特蚱請求の範囲】(57) [Claims] 【請求項】被凊理基板䞊に薄膜を圢成し、この薄膜を
パタヌニングした埌、このパタヌニングされた薄膜衚面
にダりンフロヌ型゚ッチング法によりハロゲン原子を含
有させ、ハロゲン原子を衚面に含有させた第のパタヌ
ンを圢成する工皋ず、この第のパタヌン以倖の前蚘被
凊理基板䞊の郚分に遞択的に第のパタヌンを液盞䞭で
圢成する工皋ずを含むこずを特城ずするパタヌン圢成方
法。
A thin film is formed on a substrate to be processed, and after patterning the thin film, a halogen atom is contained on the surface of the patterned thin film by a downflow etching method, and the halogen atom is contained on the surface. Forming a first pattern and selectively forming a second pattern in a liquid phase on a portion other than the first pattern on the substrate to be processed. .
【請求項】ハロゲン原子を含有させた薄膜を被凊理基
板䞊に圢成し、この薄膜をパタヌニングしおハロゲン原
子を含有させた第のパタヌンを圢成する工皋ず、この
第のパタヌン以倖の前蚘被凊理基板䞊の郚分に遞択的
に第のパタヌンを液盞䞭で圢成する工皋ずを含むこず
を特城ずするパタヌン圢成方法。
2. A step of forming a thin film containing halogen atoms on a substrate to be processed, patterning the thin film to form a first pattern containing halogen atoms, and a process other than the first pattern. Selectively forming a second pattern in a liquid phase on a portion on the substrate to be processed.
【請求項】前蚘ハロゲン原子は北玠原子であるこずを
特城ずする請求項又はに蚘茉のパタヌン圢
成方法。
3. The pattern forming method according to claim 1, wherein said halogen atom is a fluorine atom.
【請求項】前蚘第のパタヌンはシリコン酞化物より
なるこずを特城ずする請求項又はに蚘茉の
パタヌン圢成方法。
4. The pattern forming method according to claim 1, wherein said second pattern is made of silicon oxide.
【請求項】前蚘第のパタヌン液盞䞭で圢成する工皋
は、珪北化氎玠酞が含有される溶液䞭で、前蚘第のパ
タヌンが圢成される以倖の前蚘被凊理基板䞊の郚分に遞
択的にシリコン酞化物を圢成する工皋であるこずを特城
ずする請求項又はに蚘茉のパタヌン圢成方
法。
5. The step of forming in the liquid phase of the second pattern, the step of forming a portion on the substrate other than the formation of the first pattern in a solution containing hydrofluoric acid. 3. The pattern forming method according to claim 1, further comprising the step of selectively forming a silicon oxide.
JP23067090A 1990-09-03 1990-09-03 Pattern formation method Expired - Fee Related JP2898725B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23067090A JP2898725B2 (en) 1990-09-03 1990-09-03 Pattern formation method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23067090A JP2898725B2 (en) 1990-09-03 1990-09-03 Pattern formation method

Publications (2)

Publication Number Publication Date
JPH04112527A JPH04112527A (en) 1992-04-14
JP2898725B2 true JP2898725B2 (en) 1999-06-02

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Country Link
JP (1) JP2898725B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0669190A (en) * 1992-08-21 1994-03-11 Fujitsu Ltd Method for forming fluororesin film
WO2010126177A1 (en) * 2009-04-29 2010-11-04 Snu R&Db Foundation Method of fabricating substrate where patterns are formed

Also Published As

Publication number Publication date
JPH04112527A (en) 1992-04-14

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