JP2898062B2 - Solid-state imaging device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device capable of performing high-speed scanning of pixels.

[Conventional technology]

3 and 4 are a circuit configuration diagram showing a basic configuration of a conventional MOS type solid-state imaging device and a cross-sectional view showing a cross-sectional structure of a component for one pixel.

In FIG. 3, 41 is a horizontal scanning circuit, 42 is a vertical scanning circuit, 44 is a horizontal switch MOS transistor, 45 is an integration circuit for detecting a read signal, VS is a video signal output line, V _OUT is a video output, and P _OD is Overflow drain terminal, _PG is overflow gate terminal, l1 is overflow gate line, l2
Is an Al horizontal selection line, l3 is an Al vertical signal line, and l4 is an overflow drain line. Reference numeral 46 denotes a component for one pixel, which comprises a photodiode PD and transistors T1 and T2 each having an overflow gate and a MOS transfer gate.

As shown in FIG. 4, each pixel 46 has three N ⁺ diffusion regions 51 to 53 formed in the upper layer of the P-type Si substrate 50. N ⁺ diffusion region
An overflow gate 56 made of polysilicon is formed on a P-type Si substrate 50 between 51 and 52 via an SiO ₂ film 54. In addition, a transfer gate 57 made of polysilicon is formed on the P-type Si substrate 50 between the N ⁺ diffusion regions 52 and 53 via a SiO ₂ film 55. The transistor T1 is connected to the N ⁺ diffusion regions 51, 52 and the overflow gate 56, and the N ⁺ diffusion regions 52, 53
And the transfer gate 57, the transistor T2 is connected to the N ⁺ diffusion region 52.
A photodiode PD is formed by a pn junction between the photodiode PD and the P-type Si substrate 50. Further, the N ⁺ diffusion region 51, the overflow gate 56, the transfer gate 57, and the N ⁺ diffusion region 53 are respectively an overflow drain line l4, an overflow gate line l1,
It is connected to the Al horizontal selection line l2 and the Al vertical signal line l3.

The transistor T2 having the transfer gate 57 functions to prevent the charge photoelectrically converted by the photodiode PD from flowing to the Al vertical signal line l3 when turned off.
Overflow gate 56 of transistor T1, N ⁺ diffusion region 5
1 is connected to an overflow gate terminal P _OG and an overflow drain terminal P _OD , respectively, and performs a preset operation of the photodiode PD as described later.
Further, at the time of imaging, when strong light irradiates the photodiode PD, it also serves as an overflow drain that sweeps out charges overflowing from the photodiode PD and suppresses blooming.

In such a configuration, the overflow gate terminal
P via the overflow gate line l1 from _OG giving a reset pulse to the overflow gate 56 of the transistor T1, the potential of the N ⁺ diffusion region 52 forming the photodiode PD in all pixels 46 is set to a preset potential, the preset state charge Determine the amount.

When light is incident on the photodiode PD during the given integration period Ti in this state, photoexcited optical signal charges are accumulated in the N ⁺ diffusion region 52, the potential of the N ⁺ diffusion region 52 is lowered. This operation is called “IEEE J. Solid-State Circuits, Vol SC-2, n
o.12 p.65-73 Sept 1967, GPWeckler's paper, "Operation of pn junction photodetectors in a
PFI (Photon-Flux Integ) in a normal MOS-type solid-state imaging device disclosed in "photon flux integration mode"
ration) mode.

Thus, each pixel accumulated in the N ⁺ diffusion region 52
The reading of the charge of 46, that is, the imaging, is performed by causing the horizontal scanning circuit 41 and the vertical scanning circuit 42 to output scanning pulses respectively, and
By selecting the vertical signal line l3 and selectively turning on / off the selection transistor T2 of each pixel 46 via the Al horizontal selection line l2, each pixel 46 is scanned, and information is finally _output as a video signal _VOUT. Is performed by reading out.

[Problems to be solved by the invention]

The conventional solid-state imaging device is configured as described above,
Since the selection transistor T2 has a MOSFET structure, there is a problem that short-channel effects such as generation of hot electrons and induction of a bunch-through phenomenon occur when miniaturization is performed.

Further, since the switching operation of the selection transistor T2 is not so fast, the scanning speed of the pixel 46 is limited.
For this reason, there is a problem in that the number of pixels cannot be increased when imaging an object having a high spatial frequency, such as an object moving at a high speed, so that it is not possible to image with a sufficient resolution.

Further, since the photoelectric conversion unit and the scanning circuit are provided in the same layer, there is a problem that the photoelectric conversion efficiency is deteriorated due to the limitation of the aperture ratio.

On the other hand, as an MOSFET with high switching speed and no short channel effect, “IEEE International Erectlo
n Devices Meeting, Digest of Technical Papers, pp402
−405 ”by E. TAKEDA et al.“ A band to band tunneli
ng MOS device "
FET (hereinafter, referred to as. "B ² T-MOSFET") it is.

FIG. 5 is a sectional view of the B ² T-MOSFET. P as shown in FIG. ^- P ⁺ drain region 11 on the substrate 10 surface and the N ⁺ source region 12
Are formed respectively. An oxide film 13 having a thickness of 10 to 15 nm capable of tunneling is formed from the center of the P ⁺ drain region 11 to the end of the N ⁺ source region 12, and a gate electrode 14 is formed on the oxide film 13. Have been. Also,
P ⁺ drain region 11, gate electrode 14 and N ⁺ source region 12 are drain terminal 15, gate terminal 16 and source terminal 1 respectively.
Connected to 7.

In FIG. 5, _LOV is the length of a region where the gate electrode 14 and the P ⁺ drain region 11 overlap (hereinafter referred to as “gate / drain overlap region”) (hereinafter referred to as “gate / drain overlap region”). is that long ".), L _SP
Is the length between the P ⁺ drain region 11 and the N ⁺ source region 12 (hereinafter, referred to as “drain-source length”).

In such a configuration, when a voltage is applied to the drain terminal 15 and the source terminal 17 so that the source side becomes a high voltage, and a positive voltage is applied to the gate electrode 14 via the gate terminal 16, the P ⁺ drain region 11 6, a deep depletion region 10a is formed on the surface of the P ^- substrate 10 between the N ⁺ source region 12 and the surface region 11a of the P ⁺ drain region 11 in the gate / drain overlap region. As shown in the figure, band-to-band tunneling occurs and electrons (elec
tron) and hole pairs are generated in the conduction band and the valence band, respectively. Then, by electron space charge conductivity, it flows into the N ⁺ source region 12 through the depletion region 10a, by the holes flow into the P ⁺ drain region 11, a current I _t in the following equation (1) Flows.

I _t = q · N _t · μ _eff · E (1) In the equation (1), N _t is the number of hole-electron pairs, q
Elementary electric charge, the drain of mu _eff is the depletion region 10a, the effective mobility is determined by the source length L _SP, E is the gate,
This is the electric field intensity applied to the oxide film 13 in the drain overlap region.

As described above, a current flows in the B ² T-MOSFET due to the movement of two carriers, so that a high-speed switching operation can be performed. The drain, has different conductivity type of the source, drain, since the P ⁺ N ⁺ potential barrier is generated between the source, drain, miniaturization and even short channel effect such that the source length L _SP to 0.1μm or less Does not occur. However, the B ² T-MOSFET is never used as a switching transistor of the solid-state imaging device.

There is also a solid-state imaging device in which a photoelectric conversion function is provided in all the uppermost layers, a scanning unit is provided below the uppermost layer, and the aperture ratio is increased to 100% to improve the photoelectric conversion sensitivity. FIG. 7 is a cross-sectional view showing one example. This figure shows a one-pixel solid-state imaging device. This solid-state imaging device is based on the paper of the Institute of Television Engineers of Japan (Vol.5, No.29, ED606, 1981). ".

As shown in FIG. 7, an image sensor section in which an amorphous Si: H film 31 is formed on the entire upper layer section as a photoelectric conversion surface
1a and a scanning circuit section 1b formed thereunder.

In the image sensor section 1a, a glass plate 32, a color filter 33, an adhesive 34, a transparent electrode 35, and an amorphous Si: H film 31 are formed from the uppermost layer. On the other hand, the scanning circuit portion 1b has N ⁺ source / drain diffusion layers 22 and 23 formed on the upper layer of the P layer 21 and a peripheral portion on the P layer 21 between these N ⁺ source / drain diffusion layers 22 and 23. The transistor T3 for the scanning circuit (FIG. 3) is formed by the polysilicon gate 25 formed by being covered with the insulating film 24.
T2). Also, polysilicon gate 25
Also functions as a horizontal signal line (corresponding to l2 in FIG. 3).

The N ⁺ source diffusion layer 22 is electrically connected to an amorphous Si: H film 31 that performs photoelectric conversion via a first Al layer 26 and a second Al layer 27. On the other hand, an Al vertical signal line 28 (corresponding to l3 in FIG. 3) is formed on the N ⁺ drain diffusion layer 23. 29 is an interlayer insulating film, and 30 is an n-type Si substrate.

As described above, there is a solid-state imaging device in which the photoelectric conversion function is provided on the entire upper layer portion to increase the aperture ratio to 100% to improve the photoelectric conversion sensitivity. ² T-MOSFETs have never been used.

The present invention has been made in order to solve the above-mentioned problems, and is constituted by a selection transistor which does not cause a short channel effect even when miniaturized, enables high-speed scanning of pixels, and an aperture ratio required for photoelectric conversion. It is intended to obtain a solid-state imaging device in which is set to 100%.

[Means for solving the problem]

A solid-state imaging device according to the present invention is provided with a first layer having a photoelectric conversion unit, and formed below the first layer, electrically connected to the photoelectric conversion unit, and photoelectrically converted by the photoelectric conversion unit. A second layer having a selection transistor that performs switching of a selected electric signal, wherein the selection transistor includes a semiconductor layer of a first conductivity type formed in the second layer, and a semiconductor layer. A first conductivity type drain region selectively formed on the surface, a second conductivity type source region selectively formed on the semiconductor layer surface, and an end of the source region from above the drain region An insulating film formed on the insulating film and capable of tunneling, a nonvolatile information storage layer formed on the insulating film to store nonvolatile information by trapping carriers, and a nonvolatile information storage layer formed on the nonvolatile information storage layer. Is provided with a gate electrode, a first of the gate electrode overlap with said drain region planarly
The overlapping region is larger than the second overlapping region where the gate electrode planarly overlaps the source region, and when a voltage is applied to the drain region, the source region, and the gate electrode under predetermined conditions, It is large enough to cause inter-band tunneling in the surface area of the rain area in the first overlapping area.

[Action]

In the present invention, the selection transistor formed in the second layer, which performs switching of the electric signal photoelectrically converted by the photoelectric conversion unit formed in the first layer, applies a predetermined scanning pulse to the gate electrode, The on / off operation is performed depending on whether or not inter-band tunneling occurs on the surface of the drain region immediately below the gate.

〔Example〕

FIG. 1 is a sectional view showing a sectional structure of one pixel of a three-dimensional solid-state imaging device according to an embodiment of the present invention. The basic configuration of this solid-state imaging device is substantially the same as the conventional example shown in FIG. However, the photodiode PD is not used as the photoelectric conversion means, but the amorphous Si: H film 31 is used.

As shown in the figure, a scanning circuit section is formed in the lower layer section LD,
In the upper layer LU, a photoelectric conversion section composed of the amorphous Si: H film 31 shown in FIG. 7 is formed.

In the lower layer LD, a P-type formed under the lower layer LD
An N ⁺ diffusion region 2, an N ⁺ source region 3, and a P ⁺ drain region 4 are formed in the upper layer of the Si layer 1, respectively. An overflow gate 5 made of polysilicon is formed on the P-type Si layer 1 between the N ⁺ diffusion region 2 and the N ⁺ source region 3 via an SiO ₂ film 9.

Further, the film thickness capable of tunneling from the center of the P ⁺ drain region 4 to the end of the N ⁺ source region 3 is 10 to 15 μm.
nm of SiO ₂ 6a is formed. Then, a Si ₃ N ₄ film 6b is formed on the SiO ₂ film 6a, and a transfer gate 7 is formed on the Si ₃ N ₄ film 6b.

The transistor T1 shown in FIG. 3 is formed by the N ⁺ diffusion region 2, the N ⁺ source region 3 and the overflow gate 5, and the transistor T1 is formed by the N ⁺ source region 3, the P ⁺ drain region 4 and the transfer gate 7.
The select transistor T2 in the figure is formed. That is, the transistor T2 having the transfer gate 7 becomes a B ² T-MNOSFET, and its operation is to apply a predetermined voltage to the transfer gate 7,
This is performed by causing interband tunneling (hereinafter, this phenomenon is referred to as “horizontal tunneling”) in the surface region 4a of the P ⁺ drain region 4 in the drain / gate overlap region. In addition, as will be described in detail later, the threshold voltage of the select transistor T2 can be changed between V _{th1 and} V _th2 by a write and erase operation. Note that 1A is a deep depletion region. The N ⁺ diffusion region 2 and the P ⁺ drain region 4 correspond to overflow drain lines l4 and Al, respectively.
Connected to vertical signal line l3. The overflow gate 5 and the transfer gate 7 also serve as an overflow gate line l1 and an Al horizontal selection line l2, respectively.

Between the upper layer LU and the lower layer LD, the Al layer 27
Al layer 60 between the N ⁺ source region 3 is formed by penetrating the SiO ₂ film 8, an amorphous Si and: thereby achieving an electrical connection between the H film 31 and the N ⁺ source region 3. Another region between the upper layer LU and the lower layer LD is insulated by an interlayer insulating film 61 made of polyimide or the like. The interlayer insulating film 61 also has a role of flattening the lower layer portion LD.

The selection transistor T2 having the transfer gate 7 is
By being in the off state, the charge photoelectrically converted by the amorphous Si: H film 31, which is the photoelectric conversion unit in the upper layer, is changed to the Al vertical signal line.
Works to prevent spillage to l3. The overflow gate 5 and the N ⁺ diffusion region 2 of the transistor T1 are connected to an overflow gate terminal P _OG and an overflow drain terminal P _OD , respectively, as shown in FIG. : Performs the preset operation of the H film 31. Furthermore, when strong light is applied to the amorphous Si: H film 31 in the upper layer LU during imaging, the charge overflows from the N ⁺ source region 3 and also serves as an overflow drain for suppressing blooming.

An imaging operation of the solid-state imaging device having such a configuration will be described.

First, given a reset pulse via the overflow gate terminal P _OG from the overflow gate line l1 to the overflow gate 5 of the transistor T1, and sets the potential of the N ⁺ source region 3 of all the pixels 46 to a preset potential, the charge amount of the preset state To determine.

In this state (hereinafter referred to as “imaging preparation state”), the light is irradiated with the amorphous Si: H film 31 of the upper layer LU for a certain integration period Ti.
Incident on the N ⁺ source region 3
And the potential of the N ⁺ source region 3 decreases. This operation is equivalent to the PFI mode in a normal MOS type solid-state imaging device as described in the conventional example.

Each pixel thus accumulated in the N ⁺ source region 3
The reading of the charge of 46 is performed by the horizontal scanning circuit 41 and the vertical scanning circuit.
A scanning pulse is output from each of the Al vertical signal lines l3
Of each pixel 46 via the Al horizontal selection line l2.
Is performed by selectively turning on / off the select transistor T2 erased and having the threshold voltage set to V _th2 so that writing does not occur. At this time, the selection transistor T2 is turned on / off by horizontal tunneling.
Since this is performed by moving one carrier, a high-speed switching operation can be performed. Therefore, this select transistor
In the solid-state imaging device according to the present embodiment in which pixels are scanned by turning on / off T2, high-speed scanning of pixels is possible, and an object having a high spatial frequency, such as a fast-moving object, can be imaged with sufficient resolution.

In addition to the above-described imaging operation, writing of the image information of each pixel 46 to the selection transistor T2 is performed as follows.

First, in the imaging preparation state, as in the imaging operation, when light is incident on the amorphous Si: H film 31 for a certain integration period Ti, photo-excited optical signal charges are accumulated in the N ⁺ source region 3 and the N ⁺ source region The potential of 3 drops.

Thereafter, when the drain side of the select transistor T2 is set to a sufficiently lower potential than the source side and a predetermined positive high voltage is applied to the transfer gate 7, the P-type Si layer 1 between the P ⁺ drain region 4 and the N ⁺ source region 3 Deep depletion region 1A is formed on the surface. Then, the surface region 4a of the P ⁺ drain region 4 immediately below the transfer gate 7
, Horizontal tunneling occurs. At this time, the amount of horizontal tunneling also changes according to the potential of the N ⁺ source region 3 that determines the amount of photoelectric conversion. Thereafter, electrons flow into the N ⁺ source region 3 through the depletion region 1a by space charge conduction, and holes flow out toward the P ⁺ drain region 4.

Further, a write voltage is a high voltage, the electric field intensity applied to the SiO ₂ film 23 is high enough, tunneling occurs in the SiO ₂ film 23, a part of electrons generated by the horizontal tunneling Si
Tunneling occurs in the O ₂ film 6a and is trapped in the Si ₃ N ₄ film 6b (hereinafter, this phenomenon is referred to as “vertical tunneling”). The threshold voltage of the selection transistor T2 rises from the erased state _Vth2 due to the trapped charges in the Si ₃ N ₄ film 6b.

The amount of increase in the threshold voltage is proportional to the electric field intensity and the amount of horizontal tunneling generated, and the electric charge intensity increases as the potential of the N ⁺ source region 3 that determines the surface potential of the P-type Si layer 1 decreases. The threshold voltage of the select transistor T2 increases in proportion to the amount of photoelectric conversion in the amorphous Si: H film 31, which is information. Thus, the pixel information of the pixel 46 is written to the selection transistor T2. The highest threshold level of the selection transistor T1 by this writing is V _th1 .

FIG. 2 is a band diagram showing the above-mentioned horizontal tunneling and vertical tunneling. FIG. 7A shows the case where the vertical tunneling is the modified FN tunneling, and FIG. 7B shows the case where the vertical tunneling is the direct tunneling. In FIG. 2, TN1 indicates horizontal tunneling, and TN2 indicates vertical tunneling. Φ ₁₁ and φ ₁₂ are unique values determined by the P ⁺ drain region 4 and the Si ₃ N ₄ film 6b, respectively, and V _OX ′ is a potential applied from the front surface to the back surface of the SiO ₂ film 6a.

Also, phi _B 'is phi _B' is an index defined by _{≡φ 11 -φ 12 -V OX '...} (2).

When the index φ _B ′> 0, as shown in FIG.
Corrected FN tunneling occurs as horizontal tunneling, and if φ ′ _B ≦ 0, direct tunneling occurs as horizontal tunneling.

The image information written in the selection transistor T2 is read out as follows.

First, turn on the transistor T1 by applying a predetermined voltage from the overflow gate P _OG in time corresponding to the blanking period of the horizontal scanning, a predetermined voltage from the overflow drain terminal P _OD, the drain of the transistor T1 N ⁺ Supply to diffusion region 2. Then, the transistor T1
Is supplied to the N ⁺ source region 3 which is also the source of the select transistor T2 and the amount of photoelectric conversion of the amorphous Si: H film 31 is negligible.

Thereafter, a write pulse, that is, a scanning pulse of a voltage level ( _Vth1 or more) that does not cause vertical tunneling is sequentially applied to the transfer gate 7 of the select transistor T2 of each pixel 46 to cause horizontal tunneling, thereby causing the select transistor T2 to generate horizontal tunneling.
By turning on T2, the amount of charge corresponding to the threshold voltage of the selection transistor T2 is transferred to the P ⁺ drain region 4. That is,
When the threshold voltage of the selection transistor T2 is high, the amount of charge transferred to the P ⁺ drain region 4 decreases, and when the threshold voltage of the transistor T2 is low, the amount of charge transferred to the P ⁺ drain region 4 increases. Therefore, the video output V having a negative correlation with the photoelectric conversion amount of the amorphous Si: H film 31 during writing.
_OUT is read via the Al vertical signal line l3. In addition, since the switching of the selection transistor T2 is performed by horizontal tunneling, a high-speed reading operation can be performed as in the case of imaging.

On the other hand, to erase the image information stored in the select transistor T2, a negative high voltage is applied to the transfer gate 7, and the electrons trapped in the Si ₃ N ₄ film 6b are detrapped in the direction of the P-type Si layer 1. This is performed by lowering the threshold voltage to V _th1 . When this erasing operation is performed, the above-described imaging operation can be performed thereafter.

As described above, since the selection transistor T2 is turned on / off by horizontal tunneling at the time of imaging and reading, a high-speed switching operation can be performed.

In addition, since the conductivity type of the drain and source of the selection transistor T2 is different and a P ⁺ N ⁺ potential barrier is generated between the drain and the source, the length between the drain and source of the selection transistor T2 is reduced to 0.1 μm or less. The short channel effect does not occur even if the reduction is performed. Therefore, the number of pixels can be increased by miniaturization.

Further, the amorphous S of the upper layer LU formed on the entire surface
Since optical information is obtained based on the amount of charge photoelectrically converted by the i: H film 31, a solid-state imaging device having an aperture ratio of 100% can be obtained.

In this example, an amorphous Si: H film was shown as the photoelectric conversion means, but a new vicon film (Zn _1-x Cd _X Te)
Other photoelectric conversion films may be used.

In this embodiment, the selection transistor T2 has the MNOS structure in order to have a nonvolatile memory function. However, the present invention is not limited to this. The floating gate type MOSFET structure, MONOS (Metal
An Oxide Nitride Oxide Semiconductor) structure may be used.

〔The invention's effect〕

As described above, according to the present invention, switching of the electric signal photoelectrically converted by the photoelectric conversion unit formed in the upper layer portion, the selection transistor formed in the lower layer portion is configured by B ² T-MNOSFET. Therefore, the select transistor applies a predetermined voltage to its gate electrode, and performs on / off operation depending on whether or not inter-band tunneling occurs on the surface of the drain region immediately below the gate.

Therefore, the switching operation of the selection transistor becomes faster, and the solid-state imaging device having the selection transistor can perform high-speed scanning of pixels. Also, since the conductivity type of the drain region and the source region of the select transistor are different, a short channel effect does not occur in the select transistor due to the PN barrier generated between the two regions, and the number of pixels can be increased by miniaturization. It becomes possible.

Furthermore, since the first layer does not need to have a function other than the photoelectric conversion function, by making the entire surface a photoelectric conversion portion,
The aperture ratio can be made 100%.

Then, a predetermined high voltage is applied to the gate electrode to cause band-to-band tunneling on the surface portion of the drain region immediately below the gate electrode, and furthermore, electrons generated by the band-to-band tunneling are tunneled through the insulating film to form a nonvolatile information storage layer. Since image information can be written by trapping inside, nonvolatile information can be stored.

In addition, reading of non-volatile information is performed by applying a predetermined reading voltage to the gate electrode and causing band-to-band tunneling on the surface of the drain region immediately below the gate electrode, so that the switching operation becomes faster, The read operation of the stored image information can be performed at high speed.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a section of one pixel of a three-dimensional solid-state imaging device according to an embodiment of the present invention, FIG. 2 is a band diagram showing a write operation of a select transistor T2 shown in FIG.
FIG. 4 is a circuit diagram showing a basic configuration of a conventional solid-state imaging device. FIG. 4 is a cross-sectional view showing a cross section of one pixel of the conventional solid-state imaging device. FIG. 5 is a cross-sectional view showing a B ² T-MOSFET. Figure 6 is the fifth
FIG. 7 is a band diagram showing the operation of the B ² T-MOSFET shown in FIG.
The figure is a sectional view showing a section of one pixel of a conventional three-dimensional solid-state imaging device. In the figure, 1 is a P-type Si layer, 3 is an N ⁺ source region, and 4 is a P ⁺
The drain region, 6a is a SiO ₂ film, 6b is a Si ₃ N ₄ film, 7 is a transfer gate, 31 is an amorphous Si: H film, and 27 and 60 are Al layers. In the drawings, the same reference numerals indicate the same or corresponding parts.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 21/8247 H01L 27/14-27/148 H01L 29/762-29/768 H01L 29/788-29 / 792

Claims (1)

(57) [Claims] A first layer having a photoelectric conversion unit; an electric signal formed under the first layer, electrically connected to the photoelectric conversion unit, and photoelectrically converted by the photoelectric conversion unit. A second layer having a selection transistor that performs switching of the above, wherein the selection transistor comprises: a first conductivity type semiconductor layer formed in the second layer; and a surface of the semiconductor layer. A first conductivity type drain region selectively formed on the semiconductor layer, a second conductivity type source region selectively formed on the semiconductor layer surface, and an end of the source region from above the drain region. An insulating film having a thickness capable of tunneling, formed over the insulating film, a nonvolatile information storage layer formed on the insulating film to store nonvolatile information by trapping carriers, and on the nonvolatile information storage layer. A first overlapping region in which the gate electrode planarly overlaps with the drain region is larger than a second overlapping region in which the gate electrode planarly overlaps with the source region; Moreover, when a voltage is applied to the drain region, the source region, and the gate electrode under a predetermined condition, the drain region, the source region, and the gate electrode have a size such that inter-band tunneling occurs in a surface region of the drain region in the first overlap region. A solid-state imaging device.