JP2895634B2 - Method for manufacturing field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a field effect transistor having a recess structure (hereinafter sometimes abbreviated as "FET"), and more particularly to the manufacture of an FET having a two-stage recess. It is about the method.

[0002]

2. Description of the Related Art In a FET having a recess structure, a recess may have a two-stage structure in order to reduce parasitic capacitance and source resistance. As an example of an FET having such a structure, there is, for example, a HEMT disclosed in a document (Proceedings of the 1989 Joint Lecture Meeting of the Japan Society of Applied Physics, p.1066, 28p-2A-11). FIG. 6 is a diagram provided for explanation thereof, and is a cross-sectional view schematically showing this FET.

This FET has a semi-insulating GaAs substrate 11
Non-doped GaAs layer 1 as a two-dimensional electron gas layer 1
3, n-type AlGaAs layer 15a, n-type GaAs layer 15
Active layer 1 composed of b and n-type AlGaAs layer 15c
5 and an n-type GaAs layer 17 as a contact layer. Further, this FET includes ohmic electrodes 19a and 19b on the contact layer 17, a first recess 21 in a predetermined portion of the contact layer 17 between the ohmic electrodes 19a and 19b, and the first layer 21 in the active layer 15. The first recess 21 having a smaller plane area than the recess 21
, And a gate electrode 25 in the second recess 23.

In this FET, the first recess 21 is connected to the second recess 21.
The contact layer 17 and the gate electrode 25 do not come into contact with each other. Therefore,
Parasitic capacitance can be reduced as compared with the case without such a structure. In addition, since the contact layer 17 does not contact the gate electrode 25, there is no need to worry about an increase in parasitic capacitance.
The thickness of the contact layer 17 can be increased. Therefore, the source resistance can be reduced. In addition, the electric breakdown voltage was improved.

[0005] The second recess 23 is formed in the active layer 15.
However, since only the gate electrode forming portion is removed and formed, the surface depletion layer does not reach the carrier supply layer (the layer indicated by 15a in this example) in the first recessed portion beside the gate electrode 25. was gotten.

When the FET shown in FIG. 6 is manufactured, generally, the following method is used. FIGS. 7A and 7B and FIGS. 8A and 8B are process diagrams for explanation thereof. Each is shown by a schematic element sectional view.

First, a two-dimensional electron gas layer 13, an active layer 15, and a contact layer 17 are sequentially formed on a GaAs substrate 11 by a known method, and an ohmic electrode 19a and an ohmic electrode 19a are formed on the contact layer 17. 19b is formed (FIG. 7A).

Next, an etching mask 31 having an opening at a portion corresponding to a region where a first recess is to be formed is formed on the contact layer 17, and a part of the contact layer 17 is removed thereafter. One recess 21 is formed (FIG. 7B).

Next, an etching mask (for example, a resist pattern) 3 having an opening at a portion corresponding to a region where a second recess is to be formed is formed on the sample on which the first recess 21 has been formed.
3 is formed (FIG. 8A), and then a part of the active layer 15 is removed to form a second recess 23 (FIG. 8A).
(B)).

Thereafter, a thin film of a gate electrode forming material is formed on the sample provided with the etching mask (resist pattern) 33 (not shown), and then unnecessary portions of the gate electrode forming material are removed by a lift-off method. As a result, a gate electrode 25 is formed in the second recess 23. Thus, the FET (HEM) shown in FIG.
T) is obtained.

[0011]

However, in the conventional manufacturing method, the dimension L (see FIG. 6; hereinafter, gate length L) of the gate electrode 25 in the channel length direction is equal to the opening of the resist pattern 33 used at the time of lift-off. Width S (FIG. 8)
(B)). In particular, since the resist pattern 33 has an overhanging cross section in order to facilitate lift-off, the gate electrode 25 actually has a trapezoidal shape as shown in FIG. That is, the gate length L cannot be larger than the width of the opening of the resist pattern 33, but rather becomes narrower upward (see FIG. 9).
Therefore, there is a problem in that even if an attempt is made to reduce the gate resistance by increasing the thickness of the gate electrode, the increase in the thickness does not effectively contribute to the reduction of the resistance.

In addition, there is a problem that the number of steps is increased because it is necessary to separately manufacture etching masks for forming the two-stage recess.

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and accordingly, it is an object of the present invention to easily obtain a gate electrode having a shape capable of reducing gate resistance when manufacturing an FET having a two-stage recess. It is an object of the present invention to provide a method that can perform the two-stage recess formation more easily than before.

[0014]

According to the present invention, at least an active layer and a contact layer are formed on a compound semiconductor substrate in this order, and a first recess is formed in the contact layer. Forming, forming a second recess in the active layer having a smaller area than the first recess and connected to the first recess, and forming a gate in the second recess. And a step of forming an electrode, wherein the first and second recesses are formed in steps including the following steps (a) to (d) and then deformed. The gate electrode is formed with the etching mask left.

(A) A step of forming a mask pattern having an opening on the contact layer and made of a material deformable by heat treatment.

(B) a step of forming a first recess in the contact layer by isotropically etching the contact layer using the mask pattern as an etching mask;

(C) a step of heat-treating the above-mentioned mask pattern after the formation of the first recess, and deforming the portion of the above-mentioned mask pattern which hits the first recess to the inside of the first recess.

(D) forming a second recess in the active layer using the deformed mask pattern as a mask;

In practicing the present invention, it is preferable that the above-mentioned mask pattern forming material is a polyimide resin.

Further, it is preferable to use the deformed mask pattern as an interlayer insulating film between the gate electrode and the ohmic electrode.

[0021]

According to the structure of the present invention, first, the contact layer is isotropically etched using the etching mask having the opening as a mask. Because it is isotropic etching,
Since the contact layer is to be side-etched, a first recess having an area larger than the area of the opening is obtained below the etching mask.

After the formation of the first recess, a heat treatment is performed on the above-mentioned mask pattern, and the portion of the mask pattern that hits the first recess is deformed to the inside of the first recess. In this process, the portion of the mask pattern that hits the first recess is deformed so as to hang down to the first recess side, and the opening of the deformed etching mask is shaped to have a larger opening area toward the upper side.

The edge region of the first recess is covered with the deformed etching mask, and the second etching is performed in this state. Therefore, a target second recess having an area smaller than that of the first recess and connected to the first recess is obtained. In addition, since the etching mask for forming the second recess can be easily obtained without performing the photolithography process, the number of steps of the etching mask manufacturing process can be reduced as compared with the related art.

Since the gate electrode is formed with the deformed etching mask remaining, the gate electrode forming material is deposited to conform to the shape of the etching mask. Therefore, a gate electrode having a shape in which the gate length L increases as it goes upward is obtained.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, as an embodiment, a general FET (meaning that it is not HEMT) having an active layer and a contact layer in this order on a semi-insulating GaAs substrate and having a two-stage recess will be described. An example in which the present invention is applied to manufacturing will be described. 2 (A) and (B), FIGS. 3 (A) and (B),
4 (A) and 4 (B), FIG. 5 and FIG. 1 are diagrams for explanation. Here, FIG. 2 to FIG. 5 are process diagrams schematically showing the state of the element in the main process of the embodiment process by a schematic cross-sectional view, and FIG. 1 shows the structure of the FET obtained after the process of the embodiment. FIG. 4 is a schematic cross-sectional view. In FIG. 1, 41
Denotes a semi-insulating GaAs substrate as a compound semiconductor substrate,
3 is an n-type GaAs layer as an active layer, 45 is an n + -type GaAs layer as a contact layer, 47a, 4
7b is an ohmic electrode, 49x is a mask pattern deformed after forming the first recess (deformed mask pattern), 51
Is a first recess, 53 is a second recess, and 59 is a gate electrode.

First, as shown in FIG.
For example, an n-type GaAs layer 43 as an active layer and an n + -type GaAs layer 45 as a contact layer are formed in this order on a As substrate 41 (hereinafter sometimes abbreviated as the substrate 41) by a conventionally known method. Further, ohmic electrodes 47a, 47b are provided on predetermined portions of the contact layer 45.
(Source electrode and drain electrode) are formed by a known method. The active layer 43 and the contact layer 45 are
The substrate 41 may be formed thereon by a crystal growth technique.
May be formed by implanting an n-type impurity into the substrate.

Next, on the contact layer 45 on which the ohmic electrode has been formed, a mask pattern having an opening 49a having substantially the same shape as the plane shape of the second recess to be formed later, which is made of a material which can be deformed by heat treatment. The formed mask pattern 49 is formed (FIG. 2B). In this example,
DuPont photosensitive polyimide resin (PI-2703)
A mask pattern 49 is formed using D). Specifically, the PI is formed on the contact layer 45 on which the ohmic electrode has been formed.
-2703D is applied to form a film, and then the film is selectively exposed to obtain a mask pattern 49. Here, the shape substantially the same as the planar shape of the second recess means that the shape of the opening 49a is the same as the shape of the second recess even after the mask pattern 49 is deformed by receiving heat. It refers to the shape within the approximate range. The photosensitive polyimide resin (PI-2703D) used in this example is characterized in that when heat-treated after patterning, the pattern is deformed (heat-treatment conditions will be described later), but the width of the opening hardly changes before and after the heat-treatment. Mask pattern 4
9 as a forming material.

Next, using the mask pattern 49 as an etching mask, the contact layer 45 is etched by means capable of isotropically etching, for example, known wet etching. In this etching, the mask pattern 49 is used.
Since the lower contact layer is side-etched,
A desired first recess 51 having a larger area than opening 49a is formed in contact layer 45 (FIG. 3A).

Next, in the case of this embodiment, the mask pattern 49 is heated in air at a temperature of 120 ° C. for 30 minutes, at a temperature of 300 ° C. for 30 minutes, and further in a nitrogen atmosphere for 400 minutes.
Heat treatment is sequentially performed at a temperature of 60 ° C. for 60 minutes. Due to this heat treatment, the portion of the mask pattern 49 that contacts the first recess 51 hangs down and deforms toward the first recess 51 (FIG. 3B). The deformed mask pattern 49x has a shape in which the width of the opening increases as it goes upward. However, the width y at the portion where the opening of the deformed mask pattern 49x is in contact with the active layer 43 (see FIG. 2 (D))
Was almost the same as the width of the opening before the heat treatment.

Next, using the deformed mask pattern 49x as an etching mask, the active layer 43 is etched by anisotropic etching means in which etching selectively proceeds in the thickness direction. As a result, the desired second
Is formed (FIG. 4A).

Next, a gate electrode is formed as follows while leaving the deformed mask pattern 49x.

First, on the transformed mask pattern 49x,
A resist pattern 55 in which a portion facing the second recess 53 has an opening 55a is formed by a known method (FIG. 4B).

Next, a thin film 57 of a gate electrode forming material is formed on the sample by a known method (FIG. 5). afterwards,
By removing the resist pattern 55 with a suitable solvent, a portion of the gate electrode forming material on the resist pattern 55 is removed (lift-off). As a result, the gate electrode 59 is formed in the second recess 53, and the FET shown in FIG. 1 is obtained.

The gate electrode 59 thus formed
Has a mushroom-like shape, for example, a shape whose width increases upward. For this reason, when the thickness of the thin film of the gate electrode forming material is increased, the gate resistance reduction ratio becomes larger than that of the conventional gate electrode.

It should be noted that the deformed mask pattern 49x is
In this case, since it is made of a polyimide resin having excellent heat resistance, in this embodiment, it is used as it is as an interlayer insulating film between the gate electrode 59 and the ohmic electrodes 47a and 47b. This has the advantage that the step of forming an interlayer insulating film can be omitted.

Although the embodiment of the present invention has been described above, the present invention is not limited to the above-described embodiment, and the following modifications can be made.

For example, in the above-described embodiment, the photosensitive polyimide resin is used as the mask pattern forming material. However, the mask pattern forming material is not limited to this, and any other material may be used as long as the same effect can be obtained. For example, photoresist can be expected as a mask pattern forming material. When the mask pattern is made of a material having poor heat resistance, it is not preferable to use the mask pattern as it is as the interlayer insulating film. Therefore, after forming the gate electrode, the mask pattern is removed and a new interlayer insulating film or passivation film is formed. Is preferred.

The above-described embodiment is an example in which the manufacturing method according to the present invention is applied to a conventional FET having a two-stage recess but other structures. However, it is clear that the method of the present invention can be applied to the formation of various FETs having a two-stage recess, such as the HEMT shown in FIG. 6 having a two-stage recess.

[0039]

As is apparent from the above description, according to the method for manufacturing a field effect transistor of the present invention, a photolithography step for forming a mask pattern requires one step.
It only needs times. Therefore, the manufacturing process can be simplified. This mask pattern can also be used as a two-step recess forming mask and a gate electrode forming mask, although there is a step of deforming the mask pattern. Therefore, there is an advantage that alignment between each recess forming mask and each gate electrode forming mask becomes unnecessary. Further, when this mask pattern is made of a polyimide resin or the like, there is an advantage that the mask pattern can be used as an interlayer insulating film.

Since the gate electrode is formed while the deformed etching mask is left, the gate electrode forming material is deposited to conform to the shape of the etching mask. For this reason, a gate electrode is obtained in which the width of the cross section cut along the gate length direction increases as it goes upward.
Therefore, the gate resistance is efficiently reduced by increasing the thickness of the thin film of the gate electrode forming material.

[Brief description of the drawings]

FIG. 1 is a sectional view schematically showing an FET obtained by a manufacturing method of the present invention.

FIGS. 2A and 2B are process diagrams for explaining an example.

FIGS. 3 (A) and 3 (B) are process diagrams following FIG. 2 for describing an example.

FIGS. 4 (A) and (B) are process drawings following FIG. 3 for describing an example.

FIG. 5 is a process drawing following FIG. 4 for describing an example.

FIG. 6 is a diagram provided for explanation of a conventional technique.

7 (A) and 7 (B) are process diagrams for explaining a conventional technique.

FIGS. 8 (A) and (B) are process diagrams following FIG. 7 for explanation of a conventional technique.

FIG. 9 is a diagram provided for explaining a problem of the related art.

[Explanation of symbols]

41: Compound semiconductor (for example, semi-insulating GaAs substrate) 43: Active layer (for example, n-type GaAs layer) 45: Contact layer (for example, n + GaAs layer) 47a, 47b: Ohmic electrode 49: Mask pattern 49a: Second recess 51: first recess 49x: deformed mask pattern 53: second recess 55: resist pattern 55a: opening of resist pattern 57: thin film 59 of gate electrode forming material ： Gate electrode

──────────────────────────────────────────────────続 き Continued on the front page (58) Investigated field (Int.Cl. ⁶ , DB name) H01L 21/337-21/338 H01L 27/095-27/098 H01L 29/775-29/778 H01L 29 / 80-29/812

Claims (3)

(57) [Claims] An active layer is formed on a compound semiconductor substrate.
Forming a contact layer in this order, forming a first recess in the contact layer, and forming a first recess in the active layer having a smaller planar area than the first recess and connected to the first recess. In a method of manufacturing a field effect transistor including a step of forming a second recess and a step of forming a gate electrode in the second recess, the first and second recesses are formed by the following (a) to (d): A method for manufacturing a field-effect transistor, comprising: forming a gate electrode in a step including a step, and thereafter forming a gate electrode with the deformed etching mask remaining. (A) A step of forming a mask pattern having an opening on the contact layer and made of a material deformable by heat treatment. (B) forming a first recess in the contact layer by isotropically etching the contact layer using the mask pattern as an etching mask; (C) a step of subjecting the mask pattern to a heat treatment after the formation of the first recess, and deforming a portion of the mask pattern corresponding to the formed first recess to the inside of the formed first recess. (D) forming a second recess in the active layer using the deformed mask pattern as a mask. 2. The method for manufacturing a field-effect transistor according to claim 1, wherein said mask pattern forming material is a polyimide resin. 3. The method for manufacturing a field-effect transistor according to claim 1, wherein the deformed mask pattern is used as an interlayer insulating film between a gate electrode and an ohmic electrode. Method.