JP2895292B2 - Semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device such as a semiconductor memory device such as an SRAM (Static Random Access Memory) having a memory cell of a flip-flop structure.

[0002]

2. Description of the Related Art Conventionally, in this type of semiconductor memory device, memory cells are arranged in a matrix, and a memory cell is selected by selecting one word line and a pair of bit lines determined by an address input. Data is read from or written to the memory cell. FIG. 2 shows an example of the configuration. FIG. 2 is a partial circuit diagram of a conventional semiconductor memory device.

This semiconductor memory device is an SRAM having a plurality of word lines WL and a plurality of pairs of bit lines BLa and BLb selected by an address, and a memory cell 10 at each intersection thereof. They are connected and arranged in a matrix. Each memory cell 10 has a flip-flop structure in which two N-channel MOS transistors (hereinafter, referred to as NMOS) 11 and 12 are cross-connected.
Connected to the power supply potential VCC via the terminals 3 and 14;
It is connected to the ground potential VSS. Also, NMOS1
1 and 12 are connected to complementary pairs of bit lines BLa and BLb via NMOSs 15 and 16 as switching means, respectively.

One end of a pair of bit lines BLa and BLb is connected to power supply potential VCC via NMOSs 21a and 21b for load resistance, and the other end is connected to NM for a transfer gate.
Complementary data lines DLa, DLa, via OSs 22a, 22b
Connected to DLb pair. NMOS 22a, 22b
Is turned on by the column line CL selected by the address,
Controlled off.

[0005] The non-inverting input terminal 31a and the inverting input terminal 31b of the sense amplifier 30 for detecting and amplifying the potential difference on the bit line pair are connected to the pair of data lines DLa and DLb. The sense amplifier 30 has differential amplifying NMOSs 32 and 33 whose gates are controlled by a non-inverting input terminal 31a and an inverting input terminal 31b, and one of their sources and drains is a load P-channel MOS transistor (hereinafter referred to as a load). , PMOS) 34 and 35, respectively, and the other is connected to the ground potential VSS via the constant current source 36. NMOS 32,3
The drain-side output terminals 38a and 38b of 3 are connected to the source and drain of a resetting NMOS 37 whose gate is controlled by an address transition detection pulse φa. In the sense amplifier 30, the NMOS 37 is turned on once at the time of the address transition by the address transition detection pulse φa, and the output terminals 38a and 38b are short-circuited and reset.

The output terminal 38b of the sense amplifier 30 has
The input terminal 41 of the output transfer gate 40 is connected, and the output terminal 45 is connected to the output latch circuit 50 and the output circuit. Output transfer gate 40
Is a circuit controlled by complementary address transition detection pulses φa and φb to transfer the output of the sense amplifier to the output circuit side, and a PMOS 42 inverting the potential of the input terminal 41
CMOS inverter 42 comprising a and NMOS 42b
And the inverter 42 outputs the address transition detection pulse φa,
PMOS 43 and NM controlled on / off by φb
OS44.

The output terminal 4 of the output transfer gate 40
The output latch circuit 50 connected to 5 is a circuit that latches output data under the control of the address transition detection pulses φa and φb, and includes a flip-flop (hereinafter referred to as FF) 51 connected to the output terminal 45 and an address. PMOS gate controlled by transition detection pulses φa, φb
52 and an NMOS 53. FF51
Are PMOS 51a, 51b and NMOS 51c, 51
d is cross-connected.

Output terminal 4 of output transfer gate 40
5 includes inverters 61 and 62 for inverting the potential of the output terminal 45 and inverters 61 and 6
And an output buffer 63 driven by the output buffer 2. The output buffer 63 includes a PMOS 63 a and an N connected in series between the power supply potential VCC and the ground potential VSS.
MOS 63b, the connection point of which is an output terminal 64
Is connected.

FIG. 3 is an operation waveform diagram of FIG. 2, and the read operation in the semiconductor memory device of FIG. 2 will be described with reference to FIG. In the read cycle, the address ADD
, And complementary address transition detection pulses φa and φb are generated by an address transition detection circuit (not shown).
At this time, the address transition detection pulse φa is once set to “H”.
Level, φb becomes “L” level. Therefore, the NMOS 37 in the sense amplifier 30 is turned on, and the output terminal 38
a and 38b are short-circuited, and both output potentials approach the operating point of the sense amplifier 30. Further, since the PMOS 43 and the NMOS 44 in the output transfer gate 40 are turned off, the output terminal 4 of the output transfer gate 40 is turned off.
5 is in a floating state. At this time, since the PMOS 52 and the NMOS 53 in the output latch circuit 50 are turned on and the NMOS 53 is turned on, the output data of the previous read cycle is held while the FF 51 operates and the address transition detection pulse φa is generated. Thus, the output data of the previous read cycle is continuously output to the output terminal 64 of the output buffer 63.

At the same time, a transition of the address ADD causes the word line WL to go high and the column line C to go high.
L goes to the “H” level, and the memory cell 10 is selected. Therefore, the NMOSs 15 and 16 in the memory cell 10
Is turned on, and the stored data is output to the pair of bit lines BLa and BLb. At this time, since the NMOSs 22a and 22b are on, the storage data read from the memory cell 10 is transferred to the pair of data lines DLa and DLb and sent to the sense amplifier 30.

In the sense amplifier 30, when the address transition detection pulse φa transitions from “H” level to “L” level, the reset NMOS 37 is turned off, and the amplification operation is started. Address transition detection pulse φa
Becomes “H” level and φb becomes “L” level, the PMOS 43 and NMOS 4 in the output transfer gate 40 become
4 is turned on, and the output of the sense amplifier 30 is sent to the inverters 61 and 62 via the CMOS inverter 42. Inverters 61 and 62 invert the output of output transfer gate 40 to operate output buffer 63. As a result, output data is output from the output terminal 64 of the output buffer 63, and the read operation ends. At this time, in the output latch circuit 50, since both the PMOS 52 and the NMOS 53 are off, the FF 51 is turned off and has no effect on the output data.

[0012]

However, in the device having the above structure, the reading speed is increased and the sense amplifier 30 is used.
However, there is a strong demand for simplification of the reset timing design, but the demand could not be sufficiently satisfied technically for the following reasons.

That is, in the device shown in FIG. 2, the output terminal 64 changes only after the output of the address transition detection pulse φa is completed, so that it is disadvantageous in terms of speed depending on the timing of the address transition detection pulse φa. In addition, since the sense amplifier 30 always approaches the operating point of the sense amplifier 30 at the time of reset, there is a possibility that an erroneous output may occur depending on the output of the previous cycle.

The present invention solves the problems of the prior art, such as the necessity of performing complicated output control timing at the time of high-speed read operation and the possibility of erroneous output. Such a semiconductor integrated circuit device is provided.

[0015]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a plurality of memory cells connected to respective intersections of a plurality of word lines and a plurality of bit lines selected by an address. , a sense amplifier for detecting and amplifying a potential difference of the bit pair after being reset by the address transition detection pulse upon transition of the address in the read cycle of the memory data of the memory cell, a predetermined
And an output circuit for outputting output data based on the output of the sense amplifier, a semiconductor integrated circuit device such as a semiconductor memory device,
It has the following circuit .

That is, in the present invention, the connection to the sense amplifier is made.
And resetting the sense amplifier in the first state.
Potential to a first potential higher than the threshold potential.
The reset voltage of the sense amplifier in the second state.
Set to a second potential lower than the threshold potential
Setting circuit, and the sense amplifier and the setting circuit.
Connected, the output of the sense amplifier and the address transition
The setting circuit is brought into the first state or
And a control circuit for setting the second state.

[0017]

According to the present invention, since the semiconductor integrated circuit device is configured as described above, when the sense amplifier is reset in a read cycle , the output of the sense amplifier and
Set by the control circuit in response to the address transition detection pulse.
The constant circuit enters the first state or the second state. Setting circuit
Is in the first state or the second state, the sense amplifier
Reset potential is set to the first potential or the second potential.
It is. The address transition detection pulse causes the sense amplifier to
After being reset, when reading from memory cells
The potential difference between the pair of bit lines is detected by the sense amplifier.
It is amplified and output data is output from the output circuit.

[0018]

FIG. 1 is a partial circuit diagram of a semiconductor memory device showing an embodiment of the present invention. Elements common to those in FIG. 2 are denoted by the same reference numerals. This semiconductor memory device shows an SRAM as in the prior art. A plurality of bit line pairs B respectively connected to the memory cell 10 of FIG.
L1a / BL1b, BL2a / BL2b,... Are transfer gate NMOS pairs 22a-1 and 22b-, which are on / off controlled by column lines CL1, CL2,.
Are connected to complementary pairs of data lines DLa and DLb via 1, 22, 22b-2,. Data line D
Instead of the conventional sense amplifier 30, a sense amplifier 30A having a different configuration is connected to the La and DLb pairs. The sense amplifier 30A includes an NMOS 32 whose gate is controlled by the data line DLa and an NMOS 33 whose gate is controlled by the data line DLb.
32 is connected to the load PMO
It is connected to the power supply potential VCC via S34. The drain-side output terminal 38b of the NMOS 33 is connected to the power supply potential VCC via the load PMOS 35. Between the output terminals 38a and 38b, the source and the drain of the resetting NMOS 37 whose gate is controlled by the address transition detection pulse φa are respectively connected.

Of the NMOSs 32 and 33 for performing differential amplification,
The source side of the NMOS 32 is provided with a constant current source 36 for obtaining a first operating point (reset potential) VR1 in the first state.
To the ground potential VSS. Furthermore, N
The source side of the MOS 33 is connected to the input side of the constant current source 36 and to the setting circuit 100 for obtaining a second operating point (reset potential) VR2 in the second state . The setting circuit 100 is a circuit that is turned on and off by the NOR logic of the signal of the output terminal 38b and the address transition detection pulse φa, and the NMOS 10 connected in series between the source side of the NMOS 33 and the ground potential VSS.
1, 102. The drain and gate of the NMOS 102 are connected to each other.

The output terminal 38b of the sense amplifier 30A is connected to an output circuit 60 similar to that shown in FIG. 2 and a newly provided control circuit 110. The output circuit 60 includes inverters 61 and 62 for inverting a signal on the output terminal 38b of the sense amplifier 30A, and an output buffer 63 driven by the inverters 61 and 62.
It is configured. The output buffer 63 includes the inverter 6
PM gated by outputs of 1, 62
It has an OS 63a and an NMOS 63b, which are connected in series between a power supply potential VCC and a ground potential VSS, and an output terminal 64 is connected to the connection point.

The control circuit 110 generates an address transition detection pulse φa output from an address transition detection circuit (not shown).
And the signal from the output terminal 38b of the sense amplifier 30A, the "H" level or the "L" level of the output data in the previous read cycle is detected, and the NMOS 101 in the setting circuit 100 is turned on according to the detection result. , And a circuit for outputting a control signal φu for off control.

FIG. 4 is a circuit diagram showing a configuration example of FIG. In FIG. 4, the control circuit 110 includes a PMOS 11
1,112 and NMOS 113,114,
OSs 111 and 112 are connected in series to the power supply potential VCC,
Further, the source of the PMOS 112 is connected to the ground potential VSS via NMOSs 113 and 114 connected in parallel. PMOS 112 and NMOS 113, 114
Is connected to the gate of the NMOS 101 in the setting circuit 110. PMOS 112 and NMOS 1
14 are connected to the output terminal 38 of the sense amplifier 30A.
b, and a PMOS 111 and an NMOS
Each of the gates 113 is connected to the output side of the inverter 121 that inverts the address transition detection pulse φa.

On the output side of the inverter 121, two inverters 122 and 123 are cascaded, and the inverter 123 outputs an inverted address transition detection pulse φb. FIG. 5 is an operation waveform diagram of FIGS. 1 and 4, and the read operation of the semiconductor memory device shown in FIGS. 1 and 4 will be described with reference to FIG.

First, the reset state of the sense amplifier 30A will be described. When the output control signal φu of the control circuit 110 is at "L" level, the NMOS 10 in the setting circuit 100
1 is turned off, and the sense amplifier 30A at this time is turned off.
Is referred to as a first operating point VR1. When the output control signal φu of the control circuit 110 is at “H” level, the NMOS 101 in the setting circuit 100 is turned on, and the operating point of the sense amplifier 30A at this time is set to the second operation VR.
Let it be 2. Then, there is a relationship of VCC>VR1>VR2> VSS. Furthermore, the threshold potential VTH of the buffer driving inverters 61 and 62 in the output circuit 60 is
Is a potential satisfying VR1>VTH> VR2.

For example, in a read cycle, the word line WL of FIG. 2 rises to read data stored in memory cell 10, and the data is stored in bit line pair BL1a.BL1.
, BL2a, BL2b,... and column lines CL1, C
NMOS pair 22a-1 turned on by L2,.
-Via 22b-1, 22a-2, 22b-2, ...
The data is transferred to the pair of data lines DLa and DLb. In a read state in which one of the complementary data lines DLa and DLb is at the "H" level and the other data line DLb is at the "L" level, the NMO in the sense amplifier 30A is in a read state.
S33 is turned on, and NMOS 32 is turned off. Therefore, the output terminal 38b becomes "L" level. At this time, since the address ADD has not changed, the address transition detection pulse φa is at the “L” level, which is inverted by the inverter 121 to the “H” level, and the control circuit 1
The NMOS 113 in 10 is turned on, and the control signal φu output from the control circuit 110 goes to “L” level. When the control signal φu goes to “L” level, the NMOS 101 in the setting circuit 100 is turned off.

From this state, the address ADD transits,
Consider a state in which the data line DLa has transitioned to the “L” level and the data line DLb has transitioned to the “H” level. Address ADD
Makes a transition, the address transition detection pulse φa temporarily goes to the “H” level, which is inverted by the inverter 121 to the “L” level, and the “L” level turns on the PMOS 111 in the control circuit 110 to temporarily turn on the control signal. φu becomes “H” level. When the control signal φu goes to “H” level, the NMOS 101 in the setting circuit 100 turns on, and the reset potential of the sense amplifier 30A is set to the second operating point VR2. Since the threshold potential VTH of the inverters 61 and 62 is VHT> VR2, the inverters 61 and 62 do not perform the inverting operation by the output signal of the output terminal 38b of the sense amplifier 30A, and the output buffer 63 outputs the output data of the previous read cycle. Continue to output.

When the reset is completed by turning off the NMOS 37 in the sense amplifier 30A, as soon as the reset is completed, the sense amplifier 30A detects and amplifies the read data on the pair of data lines DLa and DLb in the read cycle. , And output from the output terminal 38b. This output causes the inverters 61 and 62 to perform an inversion operation, and output data is output from the output terminal 64 of the output buffer 63.
Thus, as soon as the reset is completed, the sense amplifier 30
A is the data line DLa, DL in the read cycle.
Since the data on the pair b is amplified, there is no possibility of erroneous output.

The same applies to the state of the transition opposite to the data. In this case, the output control signal φu
Becomes "L" level and the setting circuit 100 does not operate.
Therefore, the reset potential of the sense amplifier 30A is set to the first operating point VR1. This first operating point VR1
Since VR1> VHT, the inverters 61 and 62 do not perform the inverting operation, and the output buffer 63 holds the output data of the previous read cycle until the output data of the read cycle is output.

As described above, in the present embodiment, the output latch circuit 5 which operates during reset of the sense amplifier as in the prior art is
0 is omitted, and since the sense amplifier 30A and the output circuit 60 are not separated by the output transfer gate 40 as in the related art during reset of the sense amplifier, erroneous output of output data can be accurately prevented. In addition, since erroneous output can be prevented, the reading speed can be increased. Further, since the conventional output transfer gate 40 and output latch circuit 50 can be omitted, the circuit configuration can be simplified.

The present invention is not limited to the above embodiment,
Various modifications are possible. For example, the memory cell 1 of FIG.
0 may have another circuit configuration, or the sense amplifier 30A of FIG. 4 may be configured with another transistor. Further, the setting circuit 100, the output circuit 60, and the control circuit 110 in the sense amplifier 30A may have another transistor configuration. In the above embodiment, the SRAM has been described. However, the above embodiment can be applied to other semiconductor memory devices and the like.

[0031]

As described above in detail, according to the present invention, in the read operation of the memory cell using the address transition detection pulse, the setting circuit is controlled by the control circuit to the first circuit.
State or the second state, and reset the sense amplifier.
Since the potential is set to the first potential or the second potential, output data up to the read cycle can be held as output data in the previous read cycle. For this reason, erroneous output of output data can be accurately prevented, and a higher reading speed can be expected. Further, the output latch circuit that operates during reset of the sense amplifier as in the related art becomes unnecessary, and the output transfer gate can be omitted, so that the circuit configuration can be simplified.

[Brief description of the drawings]

FIG. 1 is a partial circuit diagram of a semiconductor memory device showing an embodiment of the present invention.

FIG. 2 is a partial circuit diagram of a conventional semiconductor memory device.

FIG. 3 is an operation waveform diagram of FIG. 2;

FIG. 4 is a circuit diagram showing a configuration example of FIG. 1;

FIG. 5 is an operation waveform diagram of FIGS. 1 and 4;

[Explanation of symbols]

Reference Signs List 10 memory cell 30A sense amplifier 60 output circuit 100 setting circuit 110 control circuit BLa, BLb, BL1a, BL1b, BL2a, BL
2b Bit line WL Word line φa, φb Address transition detection pulse φu Control signal

Continuation of front page (58) Fields surveyed (Int.Cl. ⁶ , DB name) G11C 11/419 G11C 11/41

Claims (1)

(57) [Claims] A plurality of memory cells connected to respective intersections of a plurality of word lines and a plurality of bit line pairs selected by an address; a sense amplifier for detecting and amplifying a potential difference of the bit line pair after being reset by the address transition detection pulse, where
And an output circuit having a constant threshold potential and outputting output data based on the output of the sense amplifier.
The reset potential of the sense amplifier to the threshold potential.
Higher than the first potential, and in the second state,
The reset potential of the amplifier is set higher than the threshold potential.
A setting circuit for setting to a low second potential, the sense amplifier and the setting circuit being connected to the setting circuit;
In response to the output of the sense amplifier and the address transition detection pulse.
In response, the setting circuit is set to the first state or the second state.
And a control circuit .