JP2891766B2 - Input circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input circuit, and more particularly, to an input circuit for removing noise of a logic integrated circuit that inputs a noisy signal.

[Conventional technology]

Conventionally, when such a signal having a large amount of noise is input, the noise propagates to the internal circuit as it is, causing a malfunction. For this reason, noise has been removed by adding a capacitor to the input terminal to lower the high-frequency impedance to the noise source.

FIG. 3 shows an input circuit of a logic integrated circuit to which such a capacitor is added. FIG. 4 is a waveform diagram showing a situation of noise removal by adding a capacitor shown in FIG.

In FIG. 3, a conventional input circuit includes an input terminal 16 and
It has a capacitor 17, CMOS inverters 18, 19, and an output terminal 20 to an internal logic circuit.

Here, when the input signal shown in FIG. 4 is input to the input terminal 16, if there is no capacitor 17, the input waveform of the input terminal is propagated to the internal logic circuit 20 as it is. Here, when the capacitor 17 is added, the high-frequency impedance of the input is reduced, so that the noise is flattened. The signal becomes an input signal when the capacitor 17 is added as shown in FIG.

[Problems to be solved by the invention]

In order to reduce the intruding noise in the above-described conventional technology, it is necessary to add a capacitor 17 to the outside. Therefore, new noise is generated in the vicinity of the threshold value (the voltage V _{th at} the node D in FIG. 4), and it is difficult to completely prevent the intrusion of noise.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned drawbacks and completely eliminate the intrusion of input noise into an internal logic circuit without adding external components and without generating new noise due to dull input signals. An object of the present invention is to provide an input circuit capable of preventing the input circuit.

[Means for solving the problem]

The input circuit of the present invention includes a resistor and a MOS transistor connected in series between a power supply line and a ground line, and an integrated signal obtained by inputting an input signal from an input terminal through a coupling capacitor and a diode. Means for supplying a signal to the gate of the MOS transistor, a first level noise detection signal is output from the node between the MOS transistor and the resistor while the input signal is fluctuating, and the input signal is stably maintained at a constant level. A noise detection circuit that outputs a noise detection signal of a second level, a first inverter, and a first inverter.
A second inverter having an input terminal connected to the output terminal of the first inverter, a first transfer gate connected between the input terminal and the input terminal of the first inverter, an output terminal of the second inverter and a second transfer gate connected to the input terminal of the first inverter. A latch circuit having a second transfer gate connected between the input terminal of the first inverter and an output terminal connected to the output terminal of the second inverter, wherein the first transfer gate has noise. When the detection signal is at the first level, it is turned off and when it is at the second level, it is turned on. The second transfer gate is turned on when the noise detection signal is at the first level, and turned off when it is at the second level. I do.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing an input circuit according to one embodiment of the present invention;
FIG. 2 is a waveform chart showing the operation of FIG.

In FIG. 1, the input circuit of this embodiment includes a noise detection circuit 13, a latch circuit 14, an input terminal 1, and an output terminal 15.

In the present embodiment, the noise detection circuit 13 includes the capacitor 2,
4, a diode 3, resistors 5 and 7, and an inverter 8. The latch circuit 14 includes inverters 11 and 12 and transfer gates 9 and 10.

More specifically, in the input circuit of the present embodiment,
A first capacitor 2 connected to an input terminal 1;
A diode 3 having an anode connected to the other end of the capacitor 2, a second capacitor 4 and a first resistor 5 connected between a cathode of the diode 3 and the ground, and a cathode of the diode 3 serving as a gate electrode. An N-channel transistor 6 having a drain electrode connected to a second resistor having a source electrode grounded and the other end connected to a power supply;
A noise detection circuit 13 having a third inverter 8 whose input is connected to the drain electrode of the channel transistor 6 is provided. One terminal is connected to the input terminal 1, and the drain electrode of the N-channel transistor 6 has a high level. A first transfer gate 9 having a gate connected to turn on the first transfer gate 9; a first inverter 11 having an input connected to the other terminal of the first transfer gate 9;
The second inverter 12 whose input is connected to the inverter 11
And one terminal is connected to the second inverter 12, a gate is connected so that the drain electrode of the N-channel transistor 6 is turned off when the drain electrode is at a low level, and the other terminal is connected to the other of the first transfer gate 9. And a latch circuit 14 for connecting the output of the second inverter 12 to an internal circuit.

Next, the operation of the input circuit will be described. When the input signal propagates to the input terminal 1, the change is transmitted to the diode 3 via the capacitor 2 of the noise detection circuit 13, and charges the capacitor 4. Due to this charging, the N-channel transistor 6 is turned on by the potential of the node A generated at both ends of the capacitor 4, the drain potential of the node B decreases from the power supply voltage V _DD to near the ground (GND) level, and the input contains noise. During that time, the change is supplied via the capacitor 2, so that the charge is always accumulated in the capacitor 2 and the above-mentioned state is maintained. This drop in drain voltage causes the latch circuit
The transfer gate 9 of 14 is turned off, and the output of the inverter 8 becomes high level.
10 turns on. As a result, the output (node C) of the latch circuit 14 maintains the low level before the noise is included in the input signal. Here, when the input signal is stabilized at the high level, the supply of the electric charge to the capacitor 4 is stopped, and conversely, the resistance 5
As a result, the capacitor 4 starts discharging, and when the potential of the capacitor 4 falls below the threshold value of the N-channel transistor 6, the N-channel transistor 6 is turned off and the drain voltage returns to the high level as shown in the waveform of the node B. Thereby, the transfer gate 9 is turned on, and the output of the inverter 8 becomes low level. Then, the transfer gate 10 is turned off. Thus, the latch circuit 14
Outputs a stable high level of the input signal, so that the waveform of the node C from which noise is removed from the input signal is obtained.

〔The invention's effect〕

As described above, according to the present invention, by inputting a change in an input signal, the propagation of the input signal is interrupted, and the supply of the immediately preceding input level to the internal logic circuit is maintained until the change in the input signal converges. Therefore, it is possible to completely prevent input noise from invading the internal logic circuit without adding external components and without generating new noise due to dull input signals.

[Brief description of the drawings]

1 is a circuit diagram showing an input circuit according to one embodiment of the present invention, FIG. 2 is a waveform diagram showing the operation of FIG. 1, FIG. 3 is a circuit diagram showing a conventional noise prevention circuit, and FIG. FIG. 4 is a waveform chart showing the operation of FIG. 1,16 input terminals, 2,4,17 capacitors, 3 diodes, 5,7 resistors, 6 N-channel transistors, 8,11,12 inverters, 9,10 Transfer gate, 18, 19 CMOS inverter, 13 Noise detection circuit, 14 Latch circuit, 15, 20 Output terminal to internal logic circuit.

 ──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Tsukasa Uneuchi 1-403-3 Kosugi-cho, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Within NEC Ic Microcomputer System Co., Ltd. (56) References JP-A-47-44054 (JP) JP-A-2-180422 (JP, A) JP-A-53-147496 (JP, A)

Claims (1)

(57) [Claims] A resistor and a MOS transistor connected in series between a power supply line and a ground line, and a signal integrated by inputting an input signal from an input terminal via a coupling capacitor and a diode; Means for supplying a noise detection signal at a first level from a node between the MOS transistor and the resistor during a period in which the input signal fluctuates, and the input signal is stabilized at a constant level. A noise detection circuit that outputs the noise detection signal at a second level during a period of operation, a first inverter, a second inverter having an input terminal connected to an output terminal of the first inverter, A first transfer gate connected between an input terminal and an input terminal of the first inverter, a first transfer gate connected between an output terminal of the second inverter and an input terminal of the first inverter; A latch circuit including a second transfer gate connected between the second transfer gate and an output terminal connected to an output terminal of the second inverter; The second transfer gate is turned off when the noise detection signal is at the first level and cut off when the noise detection signal is at the second level. Input circuit.