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JP2890625B2 - Method for manufacturing multilayer wiring board - Google Patents

Method for manufacturing multilayer wiring board

Info

Publication number
JP2890625B2
JP2890625B2 JP5215590A JP5215590A JP2890625B2 JP 2890625 B2 JP2890625 B2 JP 2890625B2 JP 5215590 A JP5215590 A JP 5215590A JP 5215590 A JP5215590 A JP 5215590A JP 2890625 B2 JP2890625 B2 JP 2890625B2
Authority
JP
Japan
Prior art keywords
wiring board
resin
thickness
multilayer wiring
laminate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP5215590A
Other languages
Japanese (ja)
Other versions
JPH03254190A (en
Inventor
良範 浦口
修次 北川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=12906966&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=JP2890625(B2) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP5215590A priority Critical patent/JP2890625B2/en
Publication of JPH03254190A publication Critical patent/JPH03254190A/en
Application granted granted Critical
Publication of JP2890625B2 publication Critical patent/JP2890625B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Production Of Multi-Layered Print Wiring Board (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は電子機器・電気機器、コンピューター、通信
機器等に用いられる多層配線基板の製造方法に関するも
のである。
Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a multilayer wiring board used for electronic devices / electric devices, computers, communication devices, and the like.

〔従来の技術〕[Conventional technology]

従来の多層配線基板は所要枚数の回路形成した内層材
の各上面及び又は下面に樹脂層を配し、最外側に外層材
を配設した積層体を、成形ズレ防止枠や成形ズレ防止容
器に収納して積層成形したり、積層体の四隅に貫通孔を
開孔し成形ズレ防止ピンを挿入したりして積層成形時の
位置ズレを防止していた。しかし前者については成形サ
イズ、成形厚みが変更するたびに枠、容器を変更する必
要があり必要数を常備することは作業効率を低下させる
ものであり、後者についてはこれ又成形サイズ−成形厚
み毎に積層体上下に配設する成形プレートを準備する必
要があり、更に加えてこの時に使用する成形プレートは
積層成形前後の積層体厚みの変化をプレート厚みで調整
する必要があるため成形プレート厚みは大きいことが必
要で作業性を低下させる問題があった。
A conventional multilayer wiring board has a required number of circuit-formed inner layer materials each having a resin layer disposed on the upper surface and / or lower surface thereof, and a laminate having an outer layer material disposed on the outermost side in a molding prevention frame or a molding prevention container. They are stored and laminated and formed, or through holes are formed in the four corners of the laminated body, and pins for preventing displacement are inserted to prevent displacement during lamination. However, in the former case, it is necessary to change the frame and container each time the molding size and molding thickness are changed, and keeping the required number always reduces the work efficiency. It is necessary to prepare molding plates to be arranged above and below the laminate, and in addition, the molding plate used at this time needs to adjust the change in the thickness of the laminate before and after lamination molding with the plate thickness. There was a problem that it was necessary to be large and workability was reduced.

〔発明が解決しようとする問題点〕[Problems to be solved by the invention]

従来の技術で述べたように、従来の成形ズレ防止方法
においては作業効率が悪いという問題があった。
As described in the prior art, there is a problem that the working efficiency is poor in the conventional molding displacement prevention method.

本発明は従来の技術における上述の問題点に鑑みてな
されたもので、その目的とするところは作業効率がよ
く、且つ層間位置精度のよい多層配線基板の製造方法を
提供することにある。
SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems in the prior art, and an object of the present invention is to provide a method for manufacturing a multilayer wiring board with high work efficiency and high interlayer position accuracy.

〔問題点を解決するための手段〕[Means for solving the problem]

本発明は所要枚数の回路形成した内層材の各上面及び
又は下面に樹脂層を配した積層体をハトメピンにて前記
内層材及び樹脂層のそれぞれの厚みを合計した、積層体
厚み±0.15mmになるようにかしめた後、最外側に外層材
を配設し積層成形することを特徴とする多層配線基板の
製造方法のため、上記目的を達成することができたもの
で、以下本発明を詳細に説明する。
The present invention provides a laminate having a resin layer disposed on each upper surface and / or lower surface of a required number of circuit-formed inner layer materials, and adding the respective thicknesses of the inner layer material and the resin layer with eyelets to a laminate thickness of ± 0.15 mm. After caulking so as to form a multilayer wiring board, which is characterized by arranging an outer layer material on the outermost side and performing lamination molding, the above object can be achieved. Will be described.

本発明に用いる内層材としては、フエノール樹脂、ク
レゾール樹脂、エポキシ樹脂、不飽和ポリエステル樹
脂、メラミン樹脂、ポリイミド、ポリブタジエン、ポリ
アミド、ポリアミドイミド、ポリスルフオン、ポリフエ
ニレンサルフアイド、ポリフエニレンオキサイド、ポリ
ブチレンテレフタレート、ポリエチレンテレフタレー
ト、弗化樹脂等の単独、変性物、混合物等の樹脂と紙、
ガラス布、ガラス不織布、合成繊維布、合成繊維不織
布、木綿等の基材と銅、アルミニウム、鉄、ニッケル、
亜鉛等の単独、合金、複合箔とからなる片面又は両面金
属箔張積層板に電気回路を形成したものである。内層材
の上面及び又は下面に配設される樹脂層としては上記樹
脂の塗布層、樹脂含浸基材層、樹脂シート層等の単独、
複合層が用いられるが好ましくは樹脂層厚を均一化しや
すい樹脂含浸基材を用いることが望ましい。ハトメピン
としてはアルミニウム、銅、ニッケル、鉄、亜鉛、鉛等
の単独、合金、複合品からなる金属製又はポリカーボネ
ート、ポリプロピレン、ポリアミド、ポリブチレンテレ
フタレート、ポリエチレンテレフタレート、ポリフエニ
レンサルファイド等からなるプラスチック製の環状又は
棒状或いは逆T型状等のハトメピンを用いることがで
き、内層材、樹脂層からなる積層体の所要位置、好まし
くは四隅部を開孔しハトメピンを嵌合させるもので、か
しめ程度は積層体厚みの±0.15mmにかしめることが層間
位置精度向上のために必要であり、更に好ましくは積層
体厚みが0.8mmの場合は0.8±0.05mmに、1.2mmの場合は
1.2±0.05mmに、1.6mmの場合は1.5±0.05mmに、2.4mmの
場合は2.3±0.05mmであることが望ましい。外層材とし
ては片面金属箔張積層板や金属箔を用いるもので、積層
成形としてはプレス、多段プレス、マルチロール、ダブ
ルベルト等による加圧下積層成形や無圧積層成形の各れ
でもよく、特に限定するものではない。
Examples of the inner layer material used in the present invention include phenol resin, cresol resin, epoxy resin, unsaturated polyester resin, melamine resin, polyimide, polybutadiene, polyamide, polyamideimide, polysulfon, polyphenylene sulfide, polyphenylene oxide, and polybutylene. Terephthalate, polyethylene terephthalate, resin such as fluorinated resin alone, modified product, mixture and paper,
Substrates such as glass cloth, glass nonwoven fabric, synthetic fiber cloth, synthetic fiber nonwoven fabric, cotton, and copper, aluminum, iron, nickel,
An electric circuit is formed on a single-sided or double-sided metal foil-clad laminate made of a single, alloy, or composite foil of zinc or the like. As the resin layer disposed on the upper surface and / or the lower surface of the inner layer material, a coating layer of the above resin, a resin-impregnated base material layer, a resin sheet layer alone,
Although a composite layer is used, it is preferable to use a resin-impregnated base material that can easily make the resin layer thickness uniform. The eyelet pins are made of aluminum, copper, nickel, iron, zinc, lead, etc. alone, alloys, metals made of composite products or plastics made of polycarbonate, polypropylene, polyamide, polybutylene terephthalate, polyethylene terephthalate, polyphenylene sulfide, etc. An eyelet with a circular or rod-like shape or an inverted T-shape can be used, and the eyelet is fitted at a required position, preferably at four corners, of the laminated body composed of the inner layer material and the resin layer. It is necessary to caulk the body thickness to ± 0.15 mm in order to improve the interlayer position accuracy, more preferably 0.8 ± 0.05 mm when the laminate thickness is 0.8 mm, when it is 1.2 mm
It is desirable that the thickness be 1.2 ± 0.05 mm, 1.5 ± 0.05 mm for 1.6 mm, and 2.3 ± 0.05 mm for 2.4 mm. As the outer layer material, a single-sided metal foil-clad laminate or a metal foil is used, and as the lamination molding, any of press-forming, multi-stage pressing, multi-roll, lamination under pressure or non-pressure lamination may be used. It is not limited.

以下本発明を実施例にもとづいて説明する。 Hereinafter, the present invention will be described based on examples.

〔実施例1〕 厚み0.8mmの両面銅張ガラス布基材エポキシ樹脂積層
板の両面に電気回路を形成して内層材とし、該内層材の
上下面に厚み0.1mmのエポキシ樹脂含浸ガラス布を夫々
2枚づつ配した積層体の四隅部に直径3.1mmの孔を開孔
し、該開孔部に外径3.05mm、内径2.4mmで鍔部直径2mm、
高さ5.2mmの真鍮製逆T型ハトメピンを嵌合してから厚
みが1.2±0.05mmになるようにかしめた後、最外側に厚
み35ミクロンの銅箔を夫々配設し成形圧力30kg/cm2、16
5℃で90分間積層成形して4層配線基板を得た。
Example 1 An electric circuit was formed on both sides of a double-sided copper-clad glass cloth-based epoxy resin laminate having a thickness of 0.8 mm to form an inner layer material, and a 0.1 mm-thick epoxy resin impregnated glass cloth was formed on the upper and lower surfaces of the inner layer material. Holes with a diameter of 3.1 mm were opened at the four corners of the laminated body arranged two by two.
After fitting a 5.2 mm high brass inverted T-shaped eyelet pin and caulking so that the thickness becomes 1.2 ± 0.05 mm, copper foil with a thickness of 35 microns is arranged on the outermost side and forming pressure 30 kg / cm 2 , 16
Lamination molding was performed at 5 ° C. for 90 minutes to obtain a four-layer wiring board.

〔比較例3〕 実施例1と同じ積層体に実施例1と同じハトメピンを
嵌合してから厚みが1.2±0.25mmになるようにかしめた
以外は実施例1と同様に処理して4層配線基板を得た。
[Comparative Example 3] Except that the same eyelet pin as in Example 1 was fitted into the same laminate as in Example 1, and then caulked so as to have a thickness of 1.2 ± 0.25 mm, the same treatment as in Example 1 was performed to obtain four layers. A wiring board was obtained.

〔比較例1〕 実施例1と同じ内層材の上下面に、実施例1と同じ樹
脂含浸基材を夫々2枚づつ配した積層体の最外側に実施
例1と同じ外層材を配設し鉄製成形ズレ防止容器に収納
した以外は実施例1と同様に処理して4層配線基板を得
た。
[Comparative Example 1] The same outer layer material as in Example 1 was provided on the outermost surface of a laminate in which two of the same resin-impregnated base materials as in Example 1 were respectively disposed on the upper and lower surfaces of the same inner layer material as in Example 1. A four-layer wiring board was obtained by performing the same treatment as in Example 1 except that the four-layer wiring board was stored in an iron-made container for preventing displacement.

〔比較例2〕 比較例1と同じ積層体の四隅に貫通孔を開孔し成形ズ
レ防止ピンを挿入し、最外側に実施例と同じ外層材を配
設し、適応する成形プレートを用いた以外は実施例1と
同様に処理して4層配線基板を得た。
[Comparative Example 2] A through hole was formed at each of the four corners of the same laminate as in Comparative Example 1, and a pin for preventing slippage was inserted. Except for the above, a four-layer wiring board was obtained in the same manner as in Example 1.

実施例1及び比較例1、2、3の4層配線基板の作業
効率及び層間位置精度は第1表のようである。
Table 1 shows the working efficiency and interlayer position accuracy of the four-layer wiring boards of Example 1 and Comparative Examples 1, 2, and 3.

注 層間位置精度は1ボード当たり4点測定により100ボ
ード分(4×100)による。
Note The interlayer position accuracy is based on 100 boards (4 x 100) by measuring four points per board.

作業効率は比較例2を100とした場合の比である。 The work efficiency is a ratio when Comparative Example 2 is set to 100.

〔発明の効果〕〔The invention's effect〕

本発明は上述した如く構成されている。特許請求の範
囲に記載した構成を有する多層配線基板の製造方法にお
いては作業効率と層間位置精度が向上する効果がある。
The present invention is configured as described above. The method for manufacturing a multilayer wiring board having the configuration described in the claims has the effects of improving work efficiency and interlayer position accuracy.

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】所要枚数の回路形成した内層材の各上面及
び下面に樹脂層を配した積層体をハトメピンにて前記内
層材及び樹脂層のそれぞれの厚みを合計した積層体の厚
みの±0.15mmになるようにかしめた後、最外層に外層材
を配設し積層成形することを特徴とする多層配線基板の
製造方法。
1. A laminated body having a required number of circuit-formed inner layer materials and a resin layer disposed on each of the upper surface and lower surface thereof is provided with a grommet pin to add a thickness of ± 0.15 of the total thickness of the laminated material obtained by summing the thicknesses of the inner layer material and the resin layer. A method for manufacturing a multilayer wiring board, comprising: crimping to a thickness of 0.1 mm;
JP5215590A 1990-03-02 1990-03-02 Method for manufacturing multilayer wiring board Expired - Lifetime JP2890625B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5215590A JP2890625B2 (en) 1990-03-02 1990-03-02 Method for manufacturing multilayer wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5215590A JP2890625B2 (en) 1990-03-02 1990-03-02 Method for manufacturing multilayer wiring board

Publications (2)

Publication Number Publication Date
JPH03254190A JPH03254190A (en) 1991-11-13
JP2890625B2 true JP2890625B2 (en) 1999-05-17

Family

ID=12906966

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5215590A Expired - Lifetime JP2890625B2 (en) 1990-03-02 1990-03-02 Method for manufacturing multilayer wiring board

Country Status (1)

Country Link
JP (1) JP2890625B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5175694B2 (en) * 2008-11-21 2013-04-03 パナソニック株式会社 Multilayer board manufacturing method and multilayer printed wiring board manufacturing method

Also Published As

Publication number Publication date
JPH03254190A (en) 1991-11-13

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