JP2887972B2 - Method for manufacturing semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a highly integrated semiconductor integrated circuit device (IC), and more particularly to a method of manufacturing such an IC having a multilayer wiring layer.

[0002]

2. Description of the Related Art With the increase in the degree of integration of semiconductor elements formed in a semiconductor substrate, circuit wiring patterns formed on a substrate surface via an insulating film have become finer and more highly integrated.
A pattern with a line width of 1 μm or less has been required.
Regarding the miniaturization / high integration of the elements in the semiconductor substrate and the miniaturization / high integration of the circuit wiring pattern on the substrate surface, the definition of the real image of the light shielding mask formed on the photoresist film in the lithography process ( Resolution: Reso
lution) must be secured. For this reason, a light source having a short wavelength such as an excimer laser has come to be used as a light source of a reduction projection exposure apparatus (stepper) usually used for exposing a photoresist film. As is well known, this resolution increases almost directly in proportion to the shortening of the wavelength of the light source of the exposure apparatus. On the other hand, the resolution is determined by the numerical aperture (Numerica) of the lens of the exposure apparatus.
l Aperture (NA). That is, the resolution increases as the numerical aperture (NA) increases. Therefore, in the exposure apparatus, a light source having a short wavelength is used, and a method of increasing the numerical aperture has conventionally been adopted as the shortening of the wavelength has reached a limit as a practical problem. However, the depth of focus (DO) of the optical system of this exposure apparatus
Since F) is inversely proportional to the square of the numerical aperture, increasing the numerical aperture and increasing the resolution inevitably reduces the depth of focus,
The allowable range of the optimum focus in the exposure process is narrowed.

[0003]

Exposure of a photoresist film in a lithography process for forming an impurity diffusion layer in a semiconductor substrate is usually performed within substantially the same plane. Narrowing is not a problem. However, since the wiring layer formed on the substrate surface via the insulating film, particularly the photoresist film for forming each layer of the multilayer wiring layer accompanying the high integration, is formed on a plane with a step, the resist film is formed. It is difficult to put the whole in the above-mentioned tolerance. If the photoresist film is exposed in a state where even a part of the photoresist film deviates from the allowable range, the circuit pattern in that part causes a short circuit or disconnection of the circuit and lowers the yield rate of the product.

On the other hand, the above-mentioned reduction projection exposure apparatus is usually provided with an auto-focus apparatus so that the above-mentioned optimum focus is automatically determined. The step on the surface affects this light interference and impairs the accuracy of the distance measurement. Therefore, in the lithography processing of the IC surface including the step,
After the exposure and development of the photoresist film, a method is adopted in which the entire process pattern or the circuit pattern portion including the step is confirmed by observation with a microscope, and then the process proceeds to the next step. Instead of an actual circuit pattern, a predetermined check pattern (usually a line-and-line in which stripes and spaces are alternately arranged) is formed on the periphery of the chip.
A technique of confirming a space (Line and Space (L / S) repeating pattern, shown in Integrated Circuit Handbook (1968, Maruzen, P269, FIG. 6.109)) with a microscope is also employed. However, since the former method becomes more difficult to implement as the actual circuit pattern becomes more complicated, the latter method tends to be more generally adopted.

[0005] Even in the case of the latter method, the adverse effect of the step cannot be eliminated. That is, even if the optimum focus can be determined for the check pattern formed directly on the IC substrate, it cannot be determined whether or not the wiring patterns at different levels by the step difference are within the allowable range of the optimum focus. .

Accordingly, an object of the present invention is to provide a method of manufacturing a highly integrated IC including a multilayer wiring layer having a step.
It is an object of the present invention to provide a manufacturing method that makes it easy to check whether exposure and development of a photoresist film corresponding to each of these wiring layers have been performed with desired definition.

[0007]

A highly integrated IC according to the present invention has the check patterns on at least two of a plurality of levels respectively corresponding to the multilayer wiring layers, and the check patterns are simultaneously observed by a microscope. It is characterized by being placed as close as possible to the periphery of an IC chip. The plurality of check patterns formed at different levels of the multilayer wiring layer are formed on the periphery of the chip in parallel with the actual circuit pattern of each layer. If there is no restriction on the arrangement of the actual circuit patterns, the check pattern can be formed on the interlayer insulating film of these patterns or on the extended portion of an equivalent member substantially on the same plane as those patterns. If there is a restriction, a dummy multilayer wiring layer different from the actual circuit pattern is formed in parallel with each layer of the actual multilayer wiring layer, and the check pattern is placed at a position close to each of the dummy wiring layers. Form.

According to the present invention, in the step of forming the wiring pattern of each of the multilayer wiring layers on the surface of the highly integrated IC chip, the real image of the light-shielding mask corresponding to the wiring pattern formed on the photoresist film is within the allowable range of the optimum focus. Can be checked by observation with a microscope on at least two levels on the IC chip, so that a decrease in the resolution of the real image of the light-shielding mask can be avoided.

[0009]

Next, two embodiments of the present invention will be described with reference to the drawings. First, referring to FIG. 1 showing an embodiment in which the present invention is applied to manufacture of a highly integrated DRAM device, a photoresist is applied to the entire surface of a semiconductor substrate 1 made of silicon (Si), and then a mask pattern corresponding to an active region is applied. The photoresist film is exposed to light through the substrate, and the substrate surface other than those corresponding to the active regions is subjected to a field oxide film forming step. At the same time, the L / S pattern 2a is formed on the peripheral portion 1A of the field oxide film (FIG. 1A).
Since the L / S pattern 2a can be formed in the peripheral portion 1A of the field oxide film, the aperture for the active region is out of the range shown in FIG. 1A and is not shown.

Next, a step of forming a photoresist film on the entire surface of the field oxide film provided with the openings (FIG. 1A) and performing a desired patterning to form a gate insulating film in the openings. At the same time, L / S patterns 3a and 3b are respectively formed in parallel on the field oxide film peripheral portion 1A and the gate wiring layer peripheral portion 1B on the same plane as the field oxide film and the gate insulating film, respectively (FIG. 1 ( b)). At this time, the L / S pattern 2a formed on the peripheral portion 1A of the field oxide film is removed by etching (shown by a dotted line in FIG. 1B).

Further, a first polysilicon wiring layer connected to a drain region (or a source region, not shown) formed in each of the active regions is similarly formed with a photoresist film, and exposed to a wiring pattern. Simultaneously with the step of forming through development, L / S patterns 4a, 4b and 4 are formed on peripheral portions 1A to 1D which are respectively flush with the field oxide film, the gate wiring layer and the polysilicon wiring layer.
c is formed (FIG. 1C). In this step, the L / S patterns 3a and 3b formed in parallel with the gate wiring layer are removed by etching (shown by dotted lines in FIG. 1C).

Next, a second polysilicon wiring layer forming a capacitor connected to a source region (or a drain region, not shown) of each of the active regions is formed by forming a dielectric layer by an interlayer insulating layer. In parallel with the step of forming via, patterning with photoresist, L /
The S patterns 5a, 5b, 5c and 5d are formed on the peripheral portions 1A, 1B, 1C and 1D, respectively, on the same plane as the field oxide film, the gate wiring layer and the polysilicon wiring layer (FIG. 1 (d)). With this step, the L / S patterns 4a, 4b and 4c are removed (shown by dotted lines in FIG. 1D). The L / S patterns 2a, 3a, 3b,
4a to 4c and 5a to 5d are formed at positions close to each other so as to enter the field of view of the optical microscope.

The L / S pattern 5 through the series of steps described above
Semiconductor chip 1 on which a, 5b, 5c and 5d are formed
Referring to FIG. 2 which is an enlarged schematic view of the L / S pattern forming portion of FIG. 1 (d) and FIG. 3 which is a cross-sectional view thereof, the L / S patterns 5a, 5b, 5c and 5d correspond to the substrate 1 Of the field oxide film 7a, the gate wiring layer 7b, the first polysilicon wiring layer 7c, and the peripheral portion 1A of the second polysilicon wiring layer 7d having different levels from each other with the interlayer films 8b to 8d interposed therebetween with reference to the surface of The state formed in 1B, 1C and 1D is schematically shown.

In the above-described series of steps, it is checked whether or not the photoresist film for forming the gate wiring layer 7b (FIG. 3) is within the allowable range of the optimum focus of the exposure apparatus by the L / S pattern. This is done by checking the resolution of 3a and 3b simultaneously with a microscope (FIG. 1).
(B)). Similarly, the resolution of the L / S patterns 4a, 4b and 4c is checked with a microscope to check whether the formation of the field oxide film 7a, the gate wiring layer 7b, and the first polysilicon wiring layer 7c is within the above-mentioned allowable range. (FIG. 1C). Further, the field oxide film 7a to the second polysilicon wiring layer 7d
The check as to whether or not the values are within the allowable range is performed by checking the L / S patterns 5a, 5b, 5c and 5d with a microscope (FIG. 1D).
As described above, in this embodiment, whether or not the wiring pattern of the formed wiring layer is formed with a required resolution in a desired process can be easily confirmed at the stage of photoresist patterning. As a result of the confirmation, if the resolution is determined to be insufficient, the photoresist is re-applied, exposed, and developed for the chip. This can greatly improve the non-defective product rate.

Referring now to FIG. 4, a second embodiment of the present invention, shown in a sectional view similar to FIG. 3, shows a concave portion 9 (depth in FIG. L / S pattern 10a similar to that of the first embodiment is formed in the same manner as in the first embodiment.
0a and another L / S pattern 10b on the wiring layer are subjected to the resolution check by the microscope. Since each point is common to the first embodiment, further description is omitted, but this configuration is similar to that of the first embodiment.
It will be apparent that the present invention can be applied to IC devices other than RAM.

In the first and second embodiments, L /
For the S pattern, the width and the interval are each 0.4 to
A pattern composed of three stripes having a thickness of 0.8 μm and a length of about 10 times the width was used. The magnification of the microscope for confirmation is preferably about 20 to 100 times.
A 0-fold one was used.

[0017]

As described above, according to the present invention, the L / L formed at a plurality of places having a height difference on a semiconductor chip is obtained.
By placing the S pattern in the same field of view of the optical microscope and confirming its shape, it is easy to determine in advance whether or not the entire semiconductor chip surface is within the focal depth of the exposure light before performing exposure with the reduced projection exposure apparatus. Since the inspection can be performed, it is not necessary to correct the depth of focus each time.

[Brief description of the drawings]

FIG. 1 is a view for explaining a first embodiment of the present invention, and FIGS. 1A to 1D are plan views of an IC chip for explaining a manufacturing process of a DRAM having a MOS structure.

FIG. 2 is an enlarged plan view schematically showing a part of the plan view of FIG. 1 (d).

FIG. 3 is a vertical sectional view taken along line XX of FIG. 2;

FIG. 4 is a longitudinal sectional view of an IC chip for explaining a second embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 1A Field oxide film peripheral part 1B Gate wiring layer peripheral part 1C First polysilicon wiring layer peripheral part 1D Second polysilicon wiring layer peripheral part 2a, 3a, 3b, 4a-4c, 5a-5d L / S
Pattern 7a field oxide film 7b gate wiring layer 7c first polysilicon wiring layer 7d second polysilicon wiring layer 8b-8d interlayer film 9 recess 10a, 10b L / S pattern

Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 21/30 541P

Claims (3)

(57) [Claims] 1. A semiconductor substrate including a plurality of impurity diffusion regions formed at a high density therein and electrically connected to the diffusion regions, and formed in a layered manner on the surface of the semiconductor substrate via an insulator film. A semiconductor integrated circuit device having a surface including a plurality of formed conductor wiring layers and a surface portion having a plurality of heights defined by at least one of the insulating film and the wiring layer with reference to the substrate surface The production method, wherein at least two surface portions having substantially the same height as at least two predetermined heights of the plurality of heights, respectively, and wherein no surface is electrically coupled with the conductor wiring layer Forming a photoresist film for lithography processing for forming the wiring layer at a position adjacent to each other in the portion, and forming the photoresist film on a predetermined line and A method for manufacturing a semiconductor integrated circuit device, comprising: exposing respective space patterns through a light-shielding mask and developing respective real images of the line and space patterns; and simultaneously inspecting the resolution of the real images with a microscope. 2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is a dynamic RAM having a MOS structure, and the surface portion is formed in parallel with the formation of the plurality of conductor wiring layers and the insulator film. 2. A method for manufacturing a semiconductor integrated circuit device according to item 1. 3. The step of etching the substrate prior to the formation of the diffusion region so as to form a recess defining at least one of the plurality of heights at a position corresponding to the surface portion of the substrate. The method for manufacturing a semiconductor integrated circuit device according to claim 1.