JP2886956B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a semiconductor device, and more particularly to control of a step-down circuit of a semiconductor device. When a high voltage used in a high-speed test or the like is applied, the high voltage is applied to each internal circuit as it is. High-speed testing can be performed, and when a normal external voltage is applied, the reduced internal voltage can be applied to each internal circuit.The purpose is to perform high-speed testing very efficiently. In a semiconductor device having a step-down voltage generating circuit for supplying a step-down voltage to an internal circuit, when the external voltage is equal to or higher than a predetermined voltage, the step-down operation of the step-down voltage generating circuit is invalidated to reduce the external voltage to the internal voltage. The configuration is such that an invalidation circuit for supplying the circuit is provided.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to control of a step-down voltage generation circuit (hereinafter, referred to as a "step-down circuit") of a semiconductor device.

In a semiconductor device, an external voltage is stepped down by a step-down circuit in accordance with miniaturization of an internal circuit, and the stepped-down voltage is used as an internal voltage in each internal circuit. On the other hand, in a high-speed test or the like for checking the life of a semiconductor device, a high voltage is applied to an internal circuit. Therefore, when performing a high-speed test, it is desirable that the applied high voltage is not affected by the step-down circuit.

[Related Art] In recent years, high integration of a semiconductor device has been achieved with miniaturization of internal circuits and the like. Since the breakdown voltage of the internal circuit decreases as the internal circuit is miniaturized, it is necessary to reduce the internal voltage. To this end, as shown in FIG. 5, a semiconductor device is provided with a step-down circuit 3 which steps down an external voltage VCC applied from a pad 1 to generate an internal voltage VINT and supplies it to each internal circuit 2.

[Problems to be Solved by the Invention] However, as shown in FIG. 6, the step-down circuit 3 only generates the internal voltage VINT which is uniformly lower than the external voltage VCC by the step-down voltage ΔV. Even if a high voltage is applied to the pad 1 from the outside, the voltage is reduced by the step-down circuit 3 so that a high-speed test cannot be performed. Accordingly, the step-down voltage ΔV is anticipated in view of the step-down voltage ΔV of the step-down circuit 3.
It was performed by applying a high voltage that was increased by a certain amount. Therefore,
When a high-speed test is performed, a high voltage obtained by adding a step-down voltage ΔV to a voltage to be always applied for the test must be created one by one, which is very troublesome.

The present invention has been made in order to solve the above-mentioned problems, and has an object to apply a high voltage used in a high-speed test or the like to the high voltage as it is applied to each internal circuit to perform a high-speed test. An object of the present invention is to provide a semiconductor device capable of performing a high-speed test very efficiently by applying a reduced internal voltage to each internal circuit when a normal external voltage is applied.

[Means for Solving the Problems] FIG. 1 is a principle explanatory diagram for explaining the principle of the present invention.

The step-down circuit 11 receives an external voltage VCC from the pad 12,
The external voltage VCC is uniformly reduced by a predetermined voltage drop ΔV, and the reduced voltage is applied to the internal circuit 13 as the internal voltage VINT.

Then, as shown in FIG.
The external voltage Vcc is applied from the pad 12, the voltage value of the external voltage Vcc applied to the pad 12 is detected, and the external voltage Vcc is a predetermined voltage as an applied test high voltage for a high-speed test or the like.
When the voltage is equal to or higher than Vd, the activation signal φ is output to the step-down circuit 11. Then, the step-down operation of the step-down circuit 11 is invalidated by the activation signal φ.

[Operation] As shown in FIG. 2, a predetermined voltage Vd
When the test high voltage is applied to the pad 12, the activation signal φ output from the invalidation circuit 14
Is disabled. Therefore, a high test voltage is applied to the internal circuit 13 to perform a high-speed test and the like.

On the other hand, when a normal external voltage lower than the predetermined voltage Vd as the test high voltage is applied to the pad 12, the invalidation circuit 14 does not output the activation signal φ unless it is a high voltage for a high-speed test or the like. As a result, the step-down circuit 11 normally operates with the external voltage VCC.
Is reduced and applied to the internal circuit 13.

Embodiment Hereinafter, a second embodiment of the semiconductor device according to the present invention will be described.
This will be described with reference to FIGS.

As shown in FIG. 3, a pad 12 is provided inside the semiconductor device.
An external voltage Vcc is supplied via an external voltage Vcc. The drain terminal of an NMOS transistor T1 constituting a step-down circuit 11 as a step-down voltage generating circuit is connected to the external voltage VCC. The gate terminal of the NMOS transistor T1 is connected to the external voltage VCC, and the lease terminal of the NMOS transistor T1 is connected to the internal circuit 13 via the invalidation circuit 14.

Therefore, the NOMS transistor T1 has the external voltage VCC high.
In the state of the level, the voltage is always turned on, the voltage is reduced to a predetermined internal voltage VINT based on the voltage drop by the NMOS transistor T1, and is supplied to the internal circuit 13 via the invalidation circuit 14.

Next, the configuration of the invalidation circuit 14 will be described in detail. The source terminal of the PMOS transistor T2 is connected to the external voltage VCC, and the drain terminal is connected to the internal circuit 13. The drain terminal of the NMOS transistor T3 whose source terminal is connected to the internal circuit 13 is connected to the step-down circuit.
The source terminal of the NMOS transistor T1 in 11 is connected.

That is, the internal voltage VINT stepped down to a predetermined voltage by the NMOS transistor T1 is supplied to the internal circuit 13 via the NMOS transistor T3.

Further, NMOS transistors T4a to T4d each having a gate terminal connected to its own drain terminal are connected in series to the external voltage VCC, and the source terminal of the NMOS transistor T4d is grounded via a resistor R1.

Further, one end of the resistor R2 is connected to the external voltage VCC, and the other end is connected to the drain terminal of the NMOS transistor T5. The source terminal of the NMOS transistor T5 is grounded, and the gate terminal is connected to the resistor R1 and the NMOS.
It is connected between the source terminal of the transistor T4d.

Accordingly, the gate terminal of the NMOS transistor T5 has an external voltage V determined by the NMOS transistors T4a to T4d and the resistor R1.
The divided voltage of CC is applied.

The voltage drop in the ON state of the NMOS transistors T4a to T4d is larger than the voltage drop of the resistor R1, and in the normal state, the NMOS transistors T4a to T4d and the resistor R1 are turned off so that the NMOS transistor T5 is turned off. Divides the external voltage VCC.

Further, the PMOS transistor T2 and the NMOS transistor T3
Is connected between the resistor R2 and the drain terminal of the NMOS transistor T5.

Since the NMOS transistor T5 is normally in the off state, the gate terminals of the NMOS transistor T3 and the PMOS transistor T2 are at the H level, the NMOS transistor T3 is in the on state, and the PMOS transistor T4 is in the off state. as a result,
The internal voltage VINT stepped down by the NMOS transistor T1 of the step-down circuit 11 is supplied to the internal circuit 13 via the NMOS transistor T3.
It is supplied to.

On the other hand, as shown in FIG. 4, when the external voltage VCC gradually rises, the potential of the resistor R1 gradually rises, and when the voltage of the external voltage VCC becomes higher than or equal to a predetermined voltage Vd for a high-speed test, the same occurs. The voltage of the resistor R1 is a gate voltage at which the NMOS transistor T5 turns on. Therefore, the potential of the drain terminal of the NMOS transistor T5 becomes L level, turning off the NMOS transistor T3 and turning on the PMOS transistor T2. Therefore, in this case, the external voltage VCC, that is, the voltage Vd for the high-speed test is directly supplied to the internal circuit 13.

Next, the operation of the semiconductor device configured as described above will be described.

When performing an acceleration test or the like of the semiconductor device configured as described above, a high voltage exceeding a predetermined voltage Vd is supplied as an external voltage VCC through the pad 12. Then, the potential of the resistor R1 increases, so that the NMOS transistor T5 is turned on.

Therefore, the NMOS transistor T5 in the invalidation circuit 14
The potential of the drain terminal becomes L level, the NMOS transistor T3 is turned off, and the PMOS transistor T2 is turned on. As a result, the internal voltage VINT stepped down from the step-down circuit 11 becomes the NMOS
Not supplied to the internal circuit 13 due to the turning off of the transistor T3,
A high voltage for a high-speed test is supplied to the internal circuit 13 as an internal voltage VINT via the PMOS transistor T2.

Therefore, unlike the past, when performing a high-speed test, the step-down circuit
There is no need to supply a voltage anticipating the step-down voltage ΔV by the pad 11 to the pad 12, and a high-speed test can be performed very efficiently.

In a normal use state, the potential of the resistor R1 of the invalidation circuit 14 is small due to the external voltage VCC, so that the NMOS transistor T5 cannot be turned on.

As a result, the potential of the drain terminal of the NMOS transistor T5 becomes H level.
The OS transistor T2 is turned off, and the external voltage VCC is not directly supplied to the internal circuit 13 from the PMOS transistor T2. Then, the external voltage VCC is stepped down to a predetermined voltage by the NMOS transistor T1 of the step-down circuit 11, and
The internal voltage VINT is applied to the internal circuit 13 via the OS transistor T3.
Can be supplied as

[Effects of the Invention] As described above in detail, according to the present invention, when a high voltage used in a high-speed test or the like is applied, the high voltage is applied to each internal circuit as it is to perform a high-speed test. Is applied, the reduced internal voltage can be applied to each internal circuit, and a high-speed test can be performed very efficiently.

[Brief description of the drawings]

1 is a diagram illustrating the principle of the present invention, FIG. 2 is a characteristic diagram based on the principle diagram, FIG. 3 is an electric circuit diagram of a semiconductor device embodying the present invention, and FIG. FIG. 5 is a characteristic diagram for disabling the step-down circuit, FIG. 5 is a configuration diagram showing a conventional semiconductor device, and FIG. 6 is a characteristic diagram of the conventional semiconductor device. In the figure, 11 is a step-down circuit (step-down voltage generating circuit), 13 is an internal circuit, 14 is a nullification circuit, VCC is an external voltage, and VINT is an internal voltage.

Continuation of the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 27 / 04,21 / 822

Claims (1)

(57) [Claims] 1. A semiconductor device having a step-down voltage generation circuit for stepping down an external voltage and supplying a step-down voltage to an internal circuit, wherein the step-down voltage generation circuit includes a step-down circuit when the external voltage is equal to or higher than a predetermined voltage. A semiconductor device comprising an invalidating circuit for invalidating an operation and supplying the external voltage to the internal circuit.