JP2882714B2 - State selection device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a state selecting device for indicating, for example, whether or not a buffer memory is empty in a circuit having a buffer memory.

[0002]

2. Description of the Related Art With the spread of digital communication in recent years,
The necessity of a system using a buffer memory is increasing. FIG. 6 is an example of a conventional circuit using a buffer memory, and is a block diagram showing a switching circuit for performing line switching of eight lines. 1-0 to 1-7 are data inputs, 2 is a multiplexing circuit, 3 is a buffer memory for holding 128 data,
4 is a decomposition circuit, 5-0 to 5-7 are data outputs, 6 is a control circuit, and 7 is an empty address queue circuit as a state selection device.

[0003] The eight-line switching circuit is configured as described above, and the data input to the data inputs 1-0 to 1-7 are:
The data is multiplexed by the multiplexing circuit 2 and written into the buffer memory 3. The written data is output to the data outputs 5-0 to 5-7 by the decomposing circuit 4 in accordance with the destination information included in the data, thereby performing circuit switching. When writing data to the buffer memory 3, the control circuit 6 manages which of the 128 addresses to write in the buffer memory. An empty address (= empty address) containing no data in the buffer memory 3 is stored in the empty address queue circuit 7, and the control circuit 6
Write data to this free address. The free address queue circuit 7 is a circuit for storing a maximum of 128 free addresses, and reads or writes free addresses under the control of the control circuit 6. This free address has a 7-bit length in order to distinguish 128 addresses in the buffer memory 3.

FIG. 7 is a block diagram showing the empty address queue circuit 7.
Is a block diagram showing 128 empty 128-bit addresses. 7, reference numeral 50 denotes a free address input, 51 denotes an input latch circuit, 8 denotes a store cell array for storing a free address, and 11 denotes a write to which address of the store cell array 8 is to be written with a free address. An address counter circuit, 12 is a read address counter circuit for holding an empty address from which address of the store cell array 8 is read, 9 is an output latch circuit, 10 is an empty address output, 13 is a write signal, and 14 is a write signal. This is a read signal.

The conventional free address queue circuit 7 is constructed as described above. For example, when writing a free address, the input latch circuit 51 reads a new free address from the free address input 50 by the write signal 13 and reads it. Store empty address in cell array 8
At the address held by the write address counter 11. The initial value of the write address counter 11 is “0”, and the value of the write address counter 11 is incremented by one each time an empty address is written to the store cell array 8 and incremented to 127. From ". Therefore, empty addresses are written in ascending order from the first address of the store cell array 8.

When an empty address is read, an empty address is read from the address stored in the read address counter 12 of the store cell array 8 by a read signal 14 and passed to an empty address output 10 through an output latch 9. Output. Read address counter 12
The initial value is also "0", and every time an empty address is read from the store cell array 8, the value of the read address counter 12 is incremented by one, and when it is incremented to 127, it is incremented from "0" again. Therefore, the empty address is stored in the store cell array 8
Are read from the first address in ascending order, and are read in the same order as the order in which they were written to the store cell array 8.

By the above operation, the empty address is written by the write signal 13 and the empty address is read by the read signal 14.
An empty address queue circuit 7 capable of storing 28 can be realized.

[0008]

In the empty address queue circuit 7 as the conventional state selection device as described above,
Since the store cell array 8 holds 128 free addresses of 7-bit length, (7 × 128 =) 8
A store cell array 8 as large as 96 bits was required. Therefore, there is a problem that the circuit size of the free address queue circuit 7 as a whole increases, and the area and the power consumption when the free address queue circuit 7 is formed into an LSI increase.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and a circuit size is reduced by reducing a required memory capacity, and a state selection in which both area and power consumption in the case of an LSI are small is small. The aim is to obtain a device.

[0010]

According to a first aspect of the present invention, there is provided a state selecting apparatus, comprising: a plurality of flip-flop circuits provided corresponding to the number of memories; and a plurality of bit lengths for distinguishing the memories. The decoder circuit 16 decodes data taken in from the outside into bits corresponding to the number of the flip-flop circuits 18 and supplies the bits to the flip-flop circuit 18. A bit selection circuit 20 for selecting one bit out of the bit information of the above, and an encoder circuit 22 for performing an inverse conversion of the output of the bit selection circuit 20 with respect to the decoder circuit 16.

In the state selection device according to the second invention, the bit selection circuit 20 outputs only the selected bit as "1" and outputs the non-selected bit as "0".
A bit search circuit 30 composed of serially connected OR circuits 26-1 to 26-127 and hierarchized;
T circuits 27-1 to 27-127 and AND circuits 28-1 to 28-1
28-127, the bit search circuit 30
And a correction circuit 24 for correcting the output of

The state selecting device according to a third aspect of the present invention has a configuration in which the encoder circuit 22 separately encodes upper bits and lower bits separately.

[0013]

According to the first aspect of the invention, the data taken in from the outside is decoded by the decoder circuit into bits corresponding to the number of flip-flop circuits. And
The decoded bit information is stored in the flip-flop circuit 18. When reading the bit information, first, the bit selection circuit 20 selects one bit from the bit information stored in the flip-flop circuit 18. Then, the selected bit information is converted by the encoder circuit 22 in a manner reverse to that of the decoder circuit 16.

In the second invention, the bit search circuit 3
With 0, data is searched one bit at a time, and a value of “0” is output until a bit of value “1” is first found. A bit having a first value of “1” and a bit higher than that bit are output. The value "1" is output. Then, the output of the bit search circuit 30 is corrected by the correction circuit 24, and only the output of the bit which first becomes "1" is set to "1", and the outputs of the other bits are output to "0". .

In the third invention, the encoder circuit 2
2, the bit information is encoded into upper bits and lower bits.

[0016]

[Embodiment 1] FIG. 1 is a circuit block diagram showing an embodiment of the present invention, in which 50, 51, 9, 10, 13,.
Reference numeral 14 is exactly the same as the conventional circuit. 16 is a decoder circuit for decoding a 7-bit address input from the input latch circuit 51 into 128 bits, 15 is an input of the decoder circuit 16, 17 is an output of the decoder circuit 16,
18 is a 128-bit flip-flop circuit for storing 128 free addresses, 19 is the output of the flip-flop circuit 18, 20 is the bit selection circuit, 21 is the output of the bit selection circuit 20, and 22 is the 128-bit address of 7 bits. And 23 is an output of the encoder circuit 22.

In the vacant address queue circuit as the state selection device configured as described above, the 128-bit flip-flop circuit 18 corresponds to each of the 128 addresses of the buffer memory 3 and has one bit. The flip-flop circuit 18 holds whether or not the address of the corresponding buffer memory 3 is a free address.
That is, if the value of the flip-flop circuit 18 is “1”, it indicates that the address of the buffer memory 3 corresponding to the flip-flop circuit 18 is a free address, and the value of the flip-flop circuit 18 is “0”. If there,
The address of the buffer memory 3 corresponding to the flip-flop circuit 18 indicates that it is not a free address.

When writing an empty address into the flip-flop circuit 18, a new empty address is first read into the input latch circuit 51 from the empty address input 50 by the write signal 13, and sent to the decoder circuit 16. The decoder circuit 16 decodes the input 7-bit address into 128 bits. 7 bits to 128
Decoding into bits means expanding 7 bits into 128-bit information. In this 128-bit information, only the value of the bit corresponding to the input 7-bit address is “1” (or “0”). "), And the values of the other bits are all" 0 "(or" 1 "). With this decode circuit output 17, the 1-bit value of the flip-flop circuit 18 corresponding to the input empty address is set to "1". When reading an empty address, the bit selection circuit 20 first selects one empty address stored in the flip-flop circuit 18. This bit selection circuit 20 outputs only one bit of a 128-bit input in which a plurality of bits are “1” as “1” and outputs the other bit as “0”, thereby outputting the flip-flop. One empty address stored in the circuit 18 is selected. The selected vacant address is the reverse operation of the decoding performed by the encoder circuit 22 to encode it into a 7-bit address. This empty address is output to the empty address output 10 through the output latch circuit 9 by the read signal 14. At the same time, by feeding back the bit selection circuit output 21 to the flip-flop circuit 18,
One bit of the flip-flop circuit 18 corresponding to the read empty address is reset from "1" to "0".
With the above operation, a free address queue circuit 7 holding 128 free addresses is obtained.

In the empty address queue circuit, the empty address is set to "1" in the flip-flop circuit 18.
, But may be stored as “0”.

In the above embodiment, 128 free addresses having a 7-bit length are stored. However, the present invention can be extended to store any free addresses of any length.

Further, in the above description, the case where the present invention is used for storing free addresses in the buffer memory 3 has been described, but it goes without saying that the present invention can be used for storing other data. For example, in a device having a plurality of memories, the present invention can be applied if the content of the memory is specified such as whether the storage capacity of the memory is equal to or more than a set level or which memory stores specific data. it can. Anything can be applied as long as it selects a binary state.

Embodiment 2 FIG. FIG. 2 is a circuit diagram showing a circuit configuration of a bit selection circuit 20 used in the state selection device of the present invention. Reference numerals 19 and 21 are exactly the same as those in the first embodiment shown in FIG. Numeral 30 denotes the first half of the bit selection circuit 20, and the value of the data input from the bit selection circuit inputs 19-0 to 19-127 is "1" from the least significant bit to the most significant bit.
, A bit search circuit for searching for a bit 31-0
31 to 127 are output of a bit search circuit, 24 is a correction circuit for correcting the searched result, and 26-1 to 26-127 are O
R circuit, 27-1 to 27-127 are NOT circuits, 28-
1-28-127 are AND circuits. The bit selection circuit 20 configured as described above has a bit selection circuit input 19
−0 to 19-127, the 128-bit data from the least significant bit input 19-0 to the most significant bit input 1
9-127 is searched one bit at a time, only the output of the bit which first becomes "1" is set to "1", and the output of the other bits is set to "0" and output.

As shown in FIG. 2, the bit selection circuit 20
The bit search circuit 30 includes a bit search circuit 30 and a correction circuit 24.
-127 is searched one bit at a time from the least significant bit input 19-0 to the most significant bit input 19-127, and outputs a value of "0" until the first bit having a value of "1" is found,
The bit whose first value is “1” (that is, the bit whose value is “1”)
Is the least significant bit) and bits higher than that bit, the value of "1" is set to the bit search circuit outputs 31-0 to 31-.
127. This bit search circuit 30
Is composed of OR circuits 26-1 to 26-127 connected in series. The correction circuit 24 sets only the output value of the bit whose bit value is “1” in the bit search circuit output 31 and the previous bit value is “0” to “1”.
And the value of the output of the other bits is "0". The correction circuit 24 can be constituted by a NOT circuit 27 and an AND circuit 28. By connecting the above-described bit search circuit 30 and the correction circuit 24 in series, only the least significant bit value among the bits having the value “1” in the 128-bit bit selection circuit input 19 is output as “1”. , A circuit that outputs the value of the other bit as “0” can be obtained. That is, the bit selection circuit 20 that selects the lowest free address from the free addresses stored in the flip-flop circuit 18 can be obtained.

In the second embodiment shown in FIG. 2, the case where the present invention is used for the bit selection circuit 20 of the empty address queue circuit 7 has been described, but it is also used for a circuit for selecting one bit from a plurality of other bits. It goes without saying that you can do it.

Embodiment 3 FIG. In the bit selection circuit 20 according to the second embodiment shown in FIG. 2, since 127 OR circuits 26-1 to 26-127 are connected in series in the bit search circuit 30, a delay of 127 OR circuits at the maximum is provided. As a result, the circuit operation of the bit selection circuit becomes slow. Therefore, the bit selection circuit 20 is speeded up by hierarchizing the bit search circuit 30 as shown in FIG. FIG. 3 is a circuit diagram showing a bit search circuit 30 in the bit selection circuit 20. Reference numerals 19 and 31 are exactly the same as those in the second embodiment shown in FIG. 32-0 to 32-31 are 4-bit bit search circuits; 33-0 to 33-127 are 4-bit bit search circuit outputs; 34 is a 31-bit bit search circuit;
35-31 are mask signals, 36-1 to 36-31 are mask circuits, and 37, 38 and 39 are OR circuits. In the bit search circuit configured as described above, the 128-bit input 19 is divided into 32 4-bit blocks,
A 4-bit bit search circuit 32-0 to 32 for each block
-31 is provided. In the lower 4 bits of the 4-bit search, the outputs 33-3, 33-7, and 33 of the most significant bit are output.
If the value of −11,..., 33-127 is “1”,
If there is a bit whose value is “1” in the four bits of the input 19 of the block and the value of the output of the most significant bit is “0”, the value is “4” in the four bits that are the input 19 of the block. It can be seen that there is no 1 "bit. Therefore, each of the most significant bit outputs 33-
By configuring a 31-bit bit search circuit 34 having inputs of 3, 33-7, 33-11,..., And 33-127, the least significant block among the blocks including the input 19 whose value is “1” And the output 35 of the bit search circuit 34 corresponding to the higher-level block becomes "1", and the other outputs become "0". Therefore, this bit search circuit 34
Of the 4-bit search circuit output 33
Is provided, a bit search circuit of 128 bits as a whole can be configured. If the mask signal 35 is “0”, the mask circuit 36 outputs the 4-bit bit search circuit output 33 as it is, and outputs the mask signal 3
If 5 is "1", all bits are set to "1" and output.

In the bit search circuit of the third embodiment shown in FIG.
A 128-bit bit search circuit is formed by the bit search circuit 32 for bits and the bit search circuit 34 for 31 bits.
A 28-bit bit search circuit can also be configured.

In the bit search circuit of the third embodiment shown in FIG.
Although the bit search circuit 32 has a two-layer structure in which 32 bit search circuits 34 are provided for 32 bits, the bit search circuit can be formed in an arbitrary hierarchy.

In the second embodiment shown in FIG. 2 and the third embodiment shown in FIG.
Although a 128-bit bit selection circuit and a 128-bit bit search circuit have been described, the present invention can be extended to a bit selection circuit with an arbitrary number of bits and a bit search circuit with an arbitrary number of bits.

Embodiment 4 FIG. The circuit diagram of FIG. 4 is a circuit diagram of an encoder circuit that encodes addresses from 128 bits to the lower 4 bits. Reference numerals 21 and 23 are exactly the same as the circuit diagram of the empty address queue circuit of the first embodiment in FIG. . 40 is an 8-input OR circuit, OR1 to OR15 are OR circuits
The circuit output, 41 is an encoder circuit for encoding from 16 bits to 4 bits, and 42 is an 8-input OR circuit. The circuit diagram of FIG. 5 is a circuit diagram of an encoder circuit that encodes the upper 3 bits of the address from 128 bits.
Reference numerals 1 and 23 are exactly the same as the circuit diagram of the empty address queue circuit of the first embodiment shown in FIG. 43 is a 16-bit bit search circuit, 44 is the output of the most significant bit of the bit search circuit 44, 48 is an encoder circuit for encoding from 8 bits to 3 bits, and 49 is a 4-input OR circuit. FIG.
The encoder circuit of FIG. 5 and the encoder circuit of FIG.
An encoder circuit for encoding an 8-bit to 7-bit address is configured.

The circuit shown in FIG. 4 first divides a 128-bit input 21 into eight blocks of 16-bit units, and ORs 40 bits between these eight blocks by an OR circuit 40. However, only the logical sum of the lowest inputs 21-0, 21-16 and 21-32 to 21-112 of each block is not obtained. This is because, when these inputs are encoded, all the lower 4 bits become "0", so that it is not necessary for the input of the encoder circuit 41 for encoding from 16 bits to 4 bits. The logically ORed 15-bit output is encoded by an encoder circuit 41 which encodes the 16-bit to 4-bit address.
Only 3-0 to 23-3 can be encoded.

In the circuit shown in FIG. 5, first, the input 21 of 128 bits is divided into eight blocks in units of 16 bits as in the circuit shown in FIG. The input of each block is input to the bit search circuit 43 shown in the second and third embodiments of the 16-bit input. If the most significant output 44 of the bit search circuit 43 is "1", "1" is included in the 16-bit block.
It can be seen that there is a bit of Therefore, by encoding the 8 bits of the output 44 of the most significant bit of each of the eight bit search circuits 43 into an address of 3 bits, the encoder circuit 48 encodes the 128 bits of the input 21 to the upper 3 bits 23-4 to 23-7 can be encoded. In the circuit of FIG. 5, there is no bit search circuit for the first block (the block whose input is 21-0 to 21-15). This is because when encoding that the first block is "1", the values of the above three bits are all "0", and are not necessary for the input of the encoder circuit 48.

An encoder circuit that obtains a 7-bit address by concatenating the lower 4 bits and the upper 3 bits of the address obtained by the circuit of FIG. 4 and the circuit of FIG. 5 and encodes the address from 128 bits to 7 bits Can be configured. As described above, by dividing and realizing the encoder circuit into two small-scale encoder circuits,
An encoder circuit having a smaller circuit size than a conventional encoder circuit can be obtained.

In the fourth embodiment, the encoder circuit for encoding from 128 bits to 7 bits is divided into two encoder circuits for encoding the lower 4 bits and the upper 3 bits from 128 bits, respectively. It can be divided into encoder circuits.

In the fourth embodiment, the encoder circuit for encoding from 128 bits to 7 bits has been described. However, the encoder circuit for encoding from an arbitrary number of bits to an arbitrary number of bits can be extended.

In the fourth embodiment, the present invention is applied to an empty address
Although the case where the present invention is used for the encoder circuit of the queue circuit has been described, it goes without saying that the present invention can be used for other encoder circuits.

Embodiment 5 FIG. In the second, third and fourth embodiments, a bit search circuit having the same configuration is used. Therefore, by using the bit search circuit with the bit selection circuit and the encoder circuit, the circuit scale of the entire empty address / queue circuit can be reduced.

[0037]

According to the invention the first as the foregoing, 1 for one vacant by the flip-flop circuit of the bit can be stored, the circuit of the entire state selection device can reduce the capacity of the memory required The scale can be reduced. Further, both the area and the power consumption when the state selection device is formed into an LSI can be reduced. Even better
In addition, empty addresses are flip-flop
And has a bit selection circuit.
Write to a specific address,
Can be applied to applications that read from
You.

According to the second aspect of the present invention, since the bit selection circuit is configured using the hierarchized bit search circuit, a bit selection circuit that operates at high speed can be obtained.

According to the third aspect of the present invention, since the upper bits and the lower bits are separately encoded, the encoding can be performed at a high speed and an encoder circuit having a small circuit size can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a bit selection circuit according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a bit search circuit of a bit selection circuit according to a third embodiment of the present invention.

FIG. 4 is a circuit diagram of an encoder circuit that encodes lower 4 bits of an encoder circuit according to a fourth embodiment of the present invention.

FIG. 5 is a circuit diagram of an encoder circuit that encodes upper three bits of an encoder circuit according to a fourth embodiment of the present invention.

FIG. 6 is a block diagram of a switching circuit showing a circuit using a conventional buffer memory.

FIG. 7 is a block diagram showing a conventional empty address queue circuit.

[Explanation of symbols]

 Reference Signs List 3 buffer memory 7 free address / queue circuit 16 decoder circuit 18 flip-flop circuit 20 bit selection circuit 22 encoder circuit 24 correction circuit 26 OR circuit 27 NOT circuit 28 AND circuit 30 bit search circuit

Claims (3)

(57) [Claims] A plurality of flip-flop circuits provided corresponding to the number of the memories in a state selection device for selecting one of binary states such as whether or not a plurality of memories are empty; And a decoder circuit for decoding data taken in from outside as a plurality of bits in order to distinguish the memories from each other into bits corresponding to the number of the flip-flop circuits and supplying the bits to the flip-flop circuits; A bit selection circuit for selecting one bit of the one bit information stored in the flip-flop circuit, and an output of the bit selection circuit,
A state selection device comprising: an encoder circuit that performs a reverse conversion to the decoder circuit. 2. The bit selection circuit outputs only selected bits as "1" and outputs non-selected bits as "0". The bit selection circuit is composed of serially connected OR circuits, and is a hierarchical bit search circuit. And a correction circuit comprising a NOT circuit and an AND circuit for correcting the output of the bit search circuit.
Item. 3. The state selection device according to claim 2, wherein the encoder circuit is configured to separately encode upper bits and lower bits separately.